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4 Design and Implementation of Lossless High Speed Data Compression Using VHDL

The objective of the project is to design a lossless data compression system which operates in high-speed to achieve high compression rate. By using architecture of compressor, The Data compression rates are significantly improved. Also inherent scalability of architecture is possible.

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Kiran Kumar P
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181 views2 pages

4 Design and Implementation of Lossless High Speed Data Compression Using VHDL

The objective of the project is to design a lossless data compression system which operates in high-speed to achieve high compression rate. By using architecture of compressor, The Data compression rates are significantly improved. Also inherent scalability of architecture is possible.

Uploaded by

Kiran Kumar P
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOC, PDF, TXT or read online on Scribd
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Design and implementation of lossless high speed data compression using VHDL

Description : With the increase in silicon densities, it is becoming feasible for compression systems to be implemented in a single chip. A 32-bit system with memory architecture is based on having data compression and decompression engines working on data at the same time. The objective of the project is to design a lossless data compression system which operates in high-speed to achieve high compression rate. By using architecture of compressor, the data compression rates are significantly improved. Also inherent scalability of architecture is possible. The main parts of the system are the Xmatchpro based data compressor and the control blocks providing control signals for the Data compressor, allowing appropriate control of the routing of data into and from the system. The Data compressor can process four bytes of data into and from a block of data every clock cycle. This is to ensure that adequate data is present for compressor to process rather than being in an idle state.

TOOL USED: Xilinx ISE LANGUAGE USED: VHDL

Block Diagram of 32 Bit Compression System

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