Project 5 Report Objective: Use the VLSI CAD tools to design and implement the SRAM consisting of 32 words,

16 bit per word, and analyze it. (This SRAM will be used as the program-storing ROM for the 8-bit RISC processor.) Tasks: Building SRAM with 5 to 32 address decoders and S ram memory area . Circuit/Block Diagram:

32x16 S RAM diagram:

1 bit RAM: I am using this design for 1bit S RAM

Schematic Design: 1 bit S RAM: for this design I modified the sizes of each transistor to make memory work appropriately. In this design the size of larger invertor is p:4.5um n:2.7um(length 600nm); weaker invertor :p: 2.25um, n:1.5um (length 2.4um). Reading NMOS size : W=10.8um L=600nm.

Address decoder:

The following diagram shows the 5 to 32 address decoder schematic design. In this design I used 32 6input and gates and 4 invertors.

Bit slice:

For this homework, I use bitslice method to reduce the amount of work, also made it easy for later expansion. In this design 1 bit slice contains the same digit of memory from all 32 locations. And in the end I put a invertor to invert the information back.

32X16 S RAM: For the 32x16 S RAM, it contains 16 bitslices and two address decoders. All the control signals are coming from decoders and connected horizontally and data goes vertically.

Layout Design:

Layout for 1bit SRAM In this design i extended all the signals to make it convenient for later connection. Also all the control signals goes horizontally and data path goes vertically.

Bitslice : in bitslice design, there are 32 of 1bit S RAM connected vertically each of them comes from different memory locations..

Address decoder: in this design, i intended to make if long rectangle shape to fit the bitslice design and all the control signals come out from right hand side. HYPERLINK "slot: "

32X16 SRAM In this final design, all 16 bitslices and 2 decoders are connected.

Simulation: 5 to 32 add simulation: in this simulation i ran through all the cases and we could see that all outputs coming out sequentially.

32x16SRAM simulation: In this simulation in used this HSP file.

Writing : At first clock i wrote 0101010101010101 to location 0 then 10101010101010 to location

31(when wrceb=0, write)

Reading: After writing, I enable the reading decoder, and read from location 0 and 31. from the waveform we could see the data coming out with delay.

Data Sheet/User's Guide:

Answers to Questions: 8. For your 32x16 SRAM, explain the data writing time. How do you measure the writing time from the simulation result? Please explain. What is the worst case data writing time of your 32x16 SRAM? Please explain the worst case data writing time. I add an additional output X to the SRAM to measure the writing time. First i write 010101010101 to location 31, right after that I write 101010101010 to the same location. The time from starting of writing signal till the the change of X, will indicate the writing time. From the wave form we could see the writing time is 3.5ns.

9. Moreover, please explain data writing setup time and hold time. What are the worst case data writing setup time and hold time of your SRAM? How fast can you repeat the data writing of one location to another location in your 32x16 SRAM (write cycle time)? For my design, the fast clock cycle I could have is around 7ns, therefore the max speed will be around 143MHZ 10. For your 32x16 SRAM, explain the data reading time. How do you measure the data reading time from the simulation result, please explain. What is the worst case data reading time of your 32x16 SRAM? Please explain the worst case data reading time. How fast can you repeat the data reading of one location to another location in your 32x16 SRAM (read cycle time)? In the simulation , I measured the reading time by measuring the time from the change of reading address to the reading data coming out. To make it the worst case, i store 01010101010101 in location 0 and 101010101010 in 31. and the delay i measured is about 6ns.

11. Which component is the slowest? Why does it take so long? How can we make it faster? Design the .hsp file to demonstrate the fastest writing and reading times of the 32x16 SRAM while maintaining the correct output result. What limits the maximum speed of operation? Show the simulation plot to substantiate your answer. In this design the slowest component is 1bit SRAM. Due to the large capacitance in the output terminals, the outputs charge up slow. The following diagram shows that for the single bit slice the output changes with a 4.8ns delay.

12. How many transistors are used in your 32x16 SRAM design? pmos = 1500 , nmos = 2524 , total = 4024

13. Did you use static, dynamic, or pass transistor logic? In this design I used static logic. 14. Which SRAM cell did you use for the 32x16 SRAM? Show your SRAM cell circuit. I used cell number 3 with two NMOS. 15. Are there any errors in schematic? No error exists. 16. Is there an error in layout? Does your layout pass the DRC checking without errors? No error exists. 17. Is there a miss match on the schematic versus layout? Does your design pass the LVS checking without errors? All layout matched with the schematics. 18. Extract the circuit from the layout including the parasitic capacitances. Then hspice simulate the extracted circuit

netlist. What is the worst case output signal rise time, fall time, and delay time? The worst case delay time is from which input to which output? Explain the signal path for the worst case delay time (this is called critical signal path)? Worst case delay time: T = __6.4____ nSec. 19. What is the total layout height and width? What is the total layout area measured in um**2? X = 514 um, Y =663 um,

Area: A = __340782____ um**2 20. What is the AT**2 measure of your design? AT**2 = __12268152_________ um**2 nSec**2

Conclusion: in this Hw, my design works correctly. However the delay time is too long. The only way to fix it is to increase the size of transistors and adding extra buffer to the terminals. And that will also go above the space limit. More improvements will be needed to discus later.