VHDL Cypress

VHDL Training
PROGRAMMABLE LOGIC DESIGN WITH VHDL

1997 Cypress Semiconductor, rev 2.5.3
VHDL Training
Why Use VHDL?

Quick Time-to-Market Allows designers to quickly develop designs requiring tens of thousands of logic gates Provides powerful high-level constructs for describing complex logic Supports modular design methodology and multiple levels of hierarchy One language for design and simulation Allows creation of device-independent designs that are portable to multiple vendors. Allows user to pick any synthesis tool, vendor, or device
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PLD Design Flow

Design Entry Schematic Capture/HDL or Both Front-End Simulation (optional) Design Compilation Synthesis, Fitting/Place&Route Design Verification Back-End Simulation (optional) Device Programming
VHDL Training
Design Entry
Schematic Simulation
Text
Design Compilation
Synthesis Fitting Place&Route
Front End
Sim. Model
Design Verification
JEDEC File
Simulation Programmer
Prog. File
Back End
VHDL Training
VHDL Design Descriptions

VHDL design descriptions (referred to as "design entities") consist of an ENTITY declaration and ARCHITECTURE body pair The ENTITY declaration describes the design I/O
The ARCHITECTURE body describes the content of the design
VHDL Training
VHDL Entity/Architecture Pairs: 2-Input And Function

ENTITY and2 IS PORT ( a,b : IN std_logic; f: OUT std_logic); END and2; ARCHITECTURE behavioral OF and2 IS BEGIN f <= a AND b; END behavioral;
VHDL Training
The Entity
A BLACK BOX The ENTITY describes the periphery of the black box (i.e., the design I/O)
BLACK_BOX rst q[7:0] co
d[7:0]
clk
VHDL Training
Example Entity declaration

ENTITY black_box IS PORT ( clk, rst: IN std_logic; d: IN std_logic_vector(7 DOWNTO 0); q: OUT std_logic_vector(7 DOWNTO 0); co: OUT std_logic); END black_box;
BLACK_BOX
More shortly
rst d[7:0] clk
q[7:0] co
VHDL Training
The Entity Declaration

ENTITY entity_name IS PORT ( -- optional generics name : mode type ; ... ) ; END entity_name;
entity_name is an arbitrary name generics are used for defining parameterized components name is the signal/port identifier and may be a comma separate list for ports of identical modes and types mode describes the direction the data is flowing type indicates the set of values the port name may be assigned
VHDL Training
Ports
The Entity (BLACK BOX) has PORTS PORTS are points of communication PORTS are often associated with the device pins PORTS are a special class of SIGNAL PORTS have an associated SIGNAL name, mode, and type
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VHDL Training
PORT modes
A ports MODE is the direction data is transferred: IN Data goes into the entity but not out
OUT
INOUT
Data goes out of the entity but not in (and is not used internally)
Data is bi-directional (goes into and out of the entity)
BUFFER Data that goes out of the entity and is also fed-back internally within the entity
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VHDL Training
IEEE 1076 Types

VHDL is a strongly typed language (you cannot assign a signal of one type to the signal of another type) bit - a signal of type bit that can only take values of '0' or '1' bit_vector - a grouping of bits (each can be '0' or '1')
SIGNAL a: BIT_VECTOR(0 TO 3); -- ascending range SIGNAL b: BIT_VECTOR(3 DOWNTO 0); -- descending range a <= "0111"; -- double quotes used for vectors b <= "0101"; This means that: a(0) = '0' b(0) = '1' a(1) = '1' b(1) = '0' a(2) = '1' b(2) = '1' a(3) = '1' b(3) = '0'
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VHDL Training
IEEE 1076 TYPES (contd.)

INTEGER useful as index holders for loops, constants, generics, or high-level modeling BOOLEAN can take values TRUE or FALSE ENUMERATED has user defined set of possible values, e.g., TYPE states IS (start, slow, fast, stop);
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VHDL Training
IEEE 1164
"Multi-value logic system for VHDL interoperability" A package created as an aid to VHDL users Nine values as opposed to two ('0' and '1') Allows increased flexibility in behavioral VHDL coding, synthesis, and simulation std_logic and std_logic_vector are used as opposed to bit and bit_vector when a multi-valued logic system is required. std_logic and std_logic_vector are used when tri-state logic is required.
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VHDL Training
1164 Types
std_logic and std_logic_vector are the industry standard logic type for digital design All 9 values are valid in a VHDL simulator, however only: 0 -- Forcing 0 1 -- Forcing 1 Z -- High Impedance L -- Weak 0 H -- Weak 1 - -- Dont care are recognized for logic synthesis
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VHDL Training
Entity Declaration Example

LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY black_box IS PORT ( clk, rst: IN std_logic; d: IN std_logic_vector(7 DOWNTO 0); q: OUT std_logic_vector(7 DOWNTO 0); co: OUT std_logic); END black_box; BLACK_BOX MODE TYPE rst d[7:0] clk co q[7:0]
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VHDL Training
Exercise #1: The Entity

Write an entity declaration for the following: Port D is a 12-bit bus, input only Port OE and CLK are each input bits Port AD is a 12-bit, three-state bi-directional bus Port A is a 12-bit bus, output only Port INT is a three-state output Port AS is an output also used internally
my_design
d[11:0]
oe clk
ad[11:0]
a[11:0] int as
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VHDL Training
Exercise #1: Solution

LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY my_design IS PORT ( d: IN std_logic_vector(11 DOWNTO 0); oe, clk: IN std_logic; ad: INOUT std_logic_vector(11 DOWNTO 0); a: OUT std_logic_vector(11 DOWNTO 0); int: OUT std_logic; my_design as: BUFFER std_logic); END my_design; ad[11:0] d[11:0] -- In this presentation, VHDL keywords a[11:0] oe -- are highlighted in bold, CAPITALS; int clk as -- however, VHDL is not case sensitive: -- clock, Clock, CLOCK all refer to the -- same signal, -- means a comment
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VHDL Training
The Architecture
Architectures describe what is in the black box (i.e., the structure or behavior of entities) Descriptions can be either a combination of Structural descriptions Instantiations (placements of logic much like in a schematic and their connections) of building blocks referred to as components Behavioral/Dataflow descriptions Algorithmic (or high-level) descriptions:
IF a = b THEN state <= state5;
Boolean equations (also referred to as dataflow):

x <= (a OR b) AND c;
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VHDL Training
The Architecture Declaration

ARCHITECTURE arch_name OF entity_name IS -- optional signal declarations, etc. BEGIN --VHDL statements END arch_name;
arch_name is an arbitrary name optional signal declarations are used for signals local to the architecture body (that is, not the entitys I/O). entity_name is the entity name statements describe the function or contents of the entity
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VHDL Training
Architecture Body Styles : Behavioral

ENTITY compare IS PORT ( a, b: IN std_logic_vector(0 TO 3); equals: OUT std_logic); END compare; ARCHITECTURE behavior OF compare IS BEGIN comp: PROCESS (a,b) BEGIN IF a = b THEN equals <= '1' ; ELSE equals <= '0' ; END IF ; END PROCESS comp; END behavior;
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VHDL Training
Architecture Body Styles : Dataflow

ENTITY compare IS PORT ( a, b: IN std_logic_vector(0 TO 3); equals: OUT std_logic); END compare;
ARCHITECTURE dataflow OF compare IS BEGIN equals <= '1' WHEN a = b ELSE '0' ; END dataflow;
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VHDL Training
Architecture Body Styles : Structural

ENTITY compare IS PORT ( a, b: IN std_logic_vector(0 TO 3); equals: OUT std_logic); END compare; USE WORK.gatespkg.ALL ; ARCHITECTURE structure OF compare IS SIGNAL x : std_logic_vector (0 to 3) ; BEGIN u0: xnor2 PORT MAP (a(0),b(0),x(0)) ; u1: xnor2 PORT MAP (a(1),b(1),x(1)) ; u2: xnor2 PORT MAP (a(2),b(2),x(2)) ; u3: xnor2 PORT MAP (a(3),b(3),x(3)) ; u4: and4 PORT MAP (x(0),x(1),x(2),x(3),equals) ; END structure;
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VHDL Training
Comparing Architecture Styles

These examples synthesize to equivalent circuits In more elaborate designs, some descriptions may yield more efficient circuits sloppy code = inefficient results (see section 3.3.4) Use styles that make your designs easier to describe and maintain Behavioral/Dataflow exploit module generation (described later) Structural descriptions may make the design less portable (may rely on a library of vendor-specific components)
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VHDL Training
Mixing Architecture Styles

The various styles may be mixed in one architecture.
ENTITY logic IS PORT ( a,b,c: IN std_logic; f: OUT std_logic); END logic; LOGIC
a b
d g1 f
c USE WORK.gatespkg.ALL; ARCHITECTURE archlogic OF logic IS SIGNAL d: std_logic; BEGIN Behavioral/Dataflow d <= a AND b; Structural g1: nor2 PORT MAP (c, d, f); END archlogic;
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VHDL Training
VHDL Statements
There are two types of statements Sequential Though hardware is concurrent, it may be modeled with algorithms, by a series of sequential statements By definition, sequential statements are grouped using a process statement. Concurrent Statements outside of a process are evaluated concurrently during simulation Processes are concurrent statements
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VHDL Training
Concurrent Statements
Concurrent statements include: boolean equations conditional/selective signal assignments (when/else, with/select) instantiations Examples of concurrent statements:
-- Examples of boolean equations x <= (a AND (NOT sel1)) OR (b AND sel1); g <= NOT (y AND sel2); -- Examples of conditional assignments y <= d WHEN (sel1 = '1') ELSE c; h <= '0' WHEN (x = '1' AND sel2 = '0') ELSE '1'; -- Examples of instantiation inst: nand2 PORT MAP (h, g, f);
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VHDL Training
The Process Statement

Used to construct algorithms/group sequential statements Statements within a process are sequential statements they execute sequentially during simulation An architecture can contain multiple processes. Each process is executed concurrently Processes may be used to model combinational or synchronous logic
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VHDL Training
The Process (contd.)

label: PROCESS (sensitivity list) -- variable declarations BEGIN -- sequential statements END PROCESS label ;
The process label and variable declarations are optional The process executes when one of the signals in the sensitivity list has an event (changes value).
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VHDL Training
Process (contd.)
Processes are executing or suspended (active or inactive/awake or asleep) A process typically has a sensitivity list When a signal in the sensitivity list changes value, the process is executed by the simulator e.g., a process with a clock signal in its sensitivity list becomes active on changes of the clock signal All signal assignments occur at the END PROCESS statement in terms of simulation The process is then suspended until there is an event (change in value) on a signal in the sensitivity list
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VHDL Training
Combinational Logic
Can be described with concurrent statements e.g. with-select-when, when-else, boolean equations, component instantiatons Can be described with sequential statements e.g. if-then-else, case-when
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VHDL Training
Combinational Logic w/ Boolean Equations

Boolean Equations can be used in both concurrent and sequential signal assignment statements. A 4-1 multiplexer is shown below
s
x <= (a AND NOT(s(1)) AND NOT(s(0))) OR (b AND NOT(s(1)) AND s(0)) OR (c AND s(1) AND NOT(s(0))) OR (d AND s(1) AND s(0)) ;
a b c d
mux
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VHDL Training
Selective Signal Assignment: with-select-when

Assignment based on a selection signal WHEN clauses must be mutually exclusive Use a WHEN OTHERS to avoid latches Only one reference to the signal, only one assignment operator (<=)
WITH selection_signal SELECT signal_name <= value_1 WHEN value_1 of selection_signal, value_2 WHEN value_2 of selection_signal, ... value_n WHEN value_n of selection_signal, value_x WHEN OTHERS;
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VHDL Training
Combinational Logic w/ Selective Signal Assignment

The same 4-1 multiplexer is shown below
with s select x <= a when 00 , b when 01 , c when 10 , d when others ;
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VHDL Training
More on with-select-when
You can use a range of values
with int_value select x <= a when 0 to 3, b when 4 | 6 | 8 , c when 10 , d when others ;
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VHDL Training
Conditional Signal Assignment: when-else

Signal is assigned a value based on conditions Any simple expression can be a condition Priority goes in order of appearance Only one reference to the signal, only one assignment operator (<=) Use a final ELSE to avoid latches
signal_name <= value_1 value_2 ... value_n value_x
WHEN condition1 ELSE WHEN condition2 ELSE
WHEN conditionn ELSE ;

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VHDL Training
Combinational Logic w/ Conditional Signal Assignment

The same 4-1 multiplexer is shown below
x <= a when (s = 00) else b when (s = 01) else c when (s = 10) else d;
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VHDL Training
Combinational Logic w/ Conditional Signal Assignment

The when conditions do not have to be mutually exclusive (as in with-select-when) A priority encoder is shown below j <= w when (a = 1) else x when (b = 1) else y when (c = 1) else z when (d = 1) else 0 ;
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VHDL Training
Combinational Logic w/ Sequential Statements

Grouped together with Processes Processes are concurrent with one another and with concurrent statements Order of sequential statements does make a difference in synthesis
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VHDL Training
Sequential Statements if-then-else

Used to select a set of statements to be executed Selection based on a boolean evaluation of a condition or set of conditions IF condition(s) THEN do something; ELSIF condition_2 THEN -- optional do something different; ELSE -- optional do something completely different; END IF ;
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VHDL Training
if-then-else
Absence of ELSE results in implicit memory 4-1 mux shown below mux4_1: process (a, b, c, d, s) begin if s = 00 then x <= a ; elsif s = 01 then x <= b ; elsif s = 10 then x <= c ; else x <= d ; end process mux4_1 ;
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VHDL Training
Sequentional Statements: Case-When

CASE selection_signal WHEN value_1_of_selection_signal => (do something) -- set of statements 1 WHEN value_2_of_selection_signal => (do something) -- set of statements 2 ... WHEN value_N_of_selection_signal => (do something) -- set of statements N WHEN OTHERS => (do something) -- default action END CASE ;
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VHDL Training
The CASE Statement: 4-1 Mux

ARCHITECTURE archdesign OF design IS SIGNAL s: std_logic_vector(0 TO 1); BEGIN mux4_1: PROCESS (a,b,c,d,s) BEGIN CASE s IS WHEN "00" => x <= a; WHEN "01" => x <= b; WHEN "10 => x <= c; WHEN OTHERS => x <= d; END CASE; END PROCESS mux4_1; END archdesign;
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VHDL Training
Sequential Statements: An Example

mux: PROCESS (a, b, s) BEGIN IF s = '0' THEN x <= a; ELSE x <= b; END IF; END PROCESS mux; s a(3 DOWNTO 0) b(3 DOWNTO 0) x(3 DOWNTO 0)
Note: logic within a process can be registered or combinatorial Note: the order of the signals in the sensitivity list is not important
Note: the process mux is sensitive to signals a, b, and s; i.e., whenever one or more of those signals changes value, the statements inside of the process are executed
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VHDL Training
Signal Assignment in Processes

Which Circuit is Correct?
PROCESS BEGIN WAIT UNTIL clock = '1' ; -- implied sensitivity list b <= a; c <= b; END PROCESS ;
a a
clock clock
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VHDL Training
Signal Assignment in Processes (contd.)

Signals are not updated immediately. Rather, they are scheduled. The signals are not updated until time advances (after the End Process statement) Therefore, two registers will be synthesized Note: In some instances, the use of concurrent statements outside the process may alleviate the problem, but this is not possible with registered logic.
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VHDL Training
VARIABLES
When a concurrent signal assignment cannot be used, the previous problem can be avoided using a VARIABLE Variables can only exist within a PROCESS, they cannot be used to communicate information between processes Variables can be of any valid data type The value assigned to a variable is available immediately The variable assignment statement is used to assign values to variables, e.g.,
c := a AND b;
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VHDL Training
Using Variables vs. Signals

Solution using a variable within a process:
-- assume a and c are signals defined elsewhere PROCESS VARIABLE b : std_logic ; BEGIN WAIT UNTIL clock = '1' ; b := a ; -- this is immediate c <= b ; -- this is scheduled END PROCESS ;
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VHDL Training
Native Operators
Logical - defined for type bit, bit_vector, boolean* AND, NAND OR, NOR XOR, XNOR NOT Relational - defined for types bit, bit_vector, integer* = (equal to) /= (not equal to) < (less than) <= (less than or equal to) > (greater than) >= (greater than or equal to) * overloaded for std_logic, std_logic_vector
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VHDL Training
Native Operators (contd.)

Unary Arithmetic - defined for type integer* - (arithmetic negate) Arithmetic - defined for type integer* + (addition), * (multiplication) - (subtraction) Concatenation - defined for strings & Note, a STRING is any sequence of characters, therefore a std_logic_vector is an example of a STRING * overloaded for std_logic, std_logic_vector
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VHDL Training
Overloaded Operators
In VHDL, the scope of all of the previous operators can be extended (or overloaded) to accept any type supported by the language, e.g.,
----assume a declaration of a 16-bit vector as SIGNAL pc IS std_logic_vector(15 DOWNTO 0); then a valid signal assignment is pc <= pc + 3; assuming the '+' operator has been overloaded to accept std_logic_vector and integer operands
The std_logic_1164 package defines overloaded logical operators (AND, OR, NOT, etc.,) for the std_logic and std_logic_vector types In this training, you will learn to use overloaded operators, but not to define them
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VHDL Training
Module Generation
In Warp release 4.0, a package called std_arith can be used to overload the arithmetic (+, -, etc.) and relational operators (=, /=, <, etc.,) for std_logic, std_logic_vector and integer types Using this package causes adders, counters, comparators, etc., to automatically replace the operators in the design. These are optimized for the target architecture and synthesis goal (area/speed) This is known as module generation
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VHDL Training
Using Tri-State Logic

ENTITY test_three IS PORT( oe : in std_logic; data : out std_logic_vector(0 to 7)); END test_three; ARCHITECTURE archtest_three OF test_three IS BEGIN PROCESS (oe) BEGIN IF (oe = '1') THEN data <= "01100100"; ELSE data <= "ZZZZZZZZ"; END IF; END PROCESS; END archtest_three;
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VHDL Training
Behavioral Dont Cares

Warp uses explicit "dont care" conditions to produce optimal logic equations
IF (a = '1') AND (b = '1') THEN x <= c; ELSE x <= '-'; END IF;
Produces the equation x = c To assign dont cares in VHDL: mysig <= '-'; 'X' means "unknown" and is not useful for synthesis
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VHDL Training
Comparing Vectors to Strings -more on don't cares Comparing "1101" to "11-1" will return FALSE Use std_match(a,"string") Must include std_arith package Example:
... signal a : stdlogic_vector (1 to 4) ; ... IF (std_match(a,"10-1")) THEN x <= '1' ; END IF ;

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VHDL Training
Legal VHDL Identifiers

Letters, digits, and underscores only (first character must be a letter) The last character cannot be an underscore Two underscores in succession are not allowed Using reserved words is not allowed Examples Legal tx_clk, Three_State_Enable, sel7D, HIT_1124 Not Legal _tx_clk, 8B10B, large#num, register, clk_
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VHDL Training
Exercise #2: Architecture Declaration of a Comparator

The entity declaration is as follows:
a(0 TO 3) LIBRARY ieee; USE ieee.std_logic_1164.ALL; b(0 TO 3) ENTITY compare IS PORT ( a, b: IN std_logic_vector(0 TO 3); aeqb: OUT std_logic); END compare;
aeqb
Write an architecture that causes aeqb to be asserted when a is equal to b
Multiple solutions exist

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VHDL Training
Three possible solutions

Concurrent statement solution using a conditional assignment:
ARCHITECTURE archcompare OF compare IS BEGIN aeqb <= '1' WHEN a = b ELSE '0'; END archcompare;
Concurrent statement solution using boolean equations:

ARCHITECTURE archcompare OF compare IS BEGIN aeqb <= NOT( (a(0) XOR b(0)) OR (a(1) XOR b(1)) OR (a(2) XOR b(2)) OR (a(3) XOR b(3))); END archcompare;
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VHDL Training
Three possible solutions (contd.)

Solution using a process with sequential statements:
ARCHITECTURE archcompare OF compare IS BEGIN comp: PROCESS (a, b) BEGIN IF a = b THEN aeqb <= '1'; a(0 TO 3) ELSE aeqb <= '0'; b(0 TO 3) END IF; END PROCESS comp; END archcompare;
aeqb
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VHDL Training
Warp Tools: Galaxy

Menus Project Management Compiler Options Control File Compiling a Design Error Tracking
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VHDL Training
Menus
Project Menu - Creating, opening, saving projects Files menu - Adding/deleting files from a project, file ordering, locking down pins, nodes, and FF locations Info menu - Report file and control file viewing/editing, tool versions, source file statistics Search menu - Allows searching of all VHDL and project files Tools Menu - Launches Nova Fonts Menu - Sets fonts for editor and error tracking Help - On-line help
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VHDL Training
Project Menu
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VHDL Training
Files Menu
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Project Management
Galaxy project terminology Creating a project Adding/Deleting files from a project File ordering
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VHDL Training
Galaxy Project Terminology

Project - The VHDL design files, project file, synthesis control file, report file, and compiler outputs form the Galaxy project Project File (.wpr) - A binary file that stores information regarding: user environment (fonts etc.) synthesis options order of compilation for design files library names and locations Project Directory - The directory where the project file and source files reside
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VHDL Training
A New Design
First step in a new design is to create a project Project->New Second step: Edit design files in the VHDL editor Third step: Add design files to the project Only .vhd files in the same directory as the project (.wpr) will be available Files added/removed by Files->Add, Files -> Add all and Files->Remove File ordering controlled by Files->Move Up and Files->Move Down Top level file should be at the bottom of the list
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VHDL Training
Compiler Options - Generic

Used for selecting global synthesis and reporting options
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VHDL Training
Compiler Options - Generic

Optimization - effort level of compiler Exhaustive is highest level of optimization Run Options - error and message reporting Using Quiet option speeds up compilation! Goal Global area or speed Goal directives applied at lower levels have precedence
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VHDL Training
Compiler Options - Device

Used to select target device, device-specific synthesis options, and timing simulation outputs for PLDs/CPLDs
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VHDL Training
Compiler Options - Device

Selecting a target device Output formats JEDEC Normal - required for programmers Post-JEDEC Sim VHDL and Verilog timing models for PLDs/CPLDs
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VHDL Training
Compiling a design
Smart Compile Compiles all project files in specified order Knows if a file has been modified Makes recompiling large designs easy Compile Selected Compiles only the selected file Useful for code verification or to simply compile a file to a library
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VHDL Training
Error Tracking
Galaxy has an integrated VHDL syntax error tracking/location mechanism Highlighting an error and clicking on magnifying glass launches editor with cursor at location of error Up and down arrows bring you to previous/next error
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VHDL Training
Control File (.ctl)

Holds all synthesis directives for the design Allows VHDL files to be device-independent Automatically included in the project directory Must have same base name as top-level file Can edit file from Info->Control File Supports simpler directive syntax Supports use of wildcards You can place a directive on all signals/entities
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VHDL Training
VHDL Editor
Used for editing design files Allows searching all project files Provides VHDL Browser (VHDL templates) Allows you to compile the file you are editing by using VHDL->Compile A much improved editor will be available with release 4.2 (send in those registration cards)
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VHDL Training
Report File
Two output options: detailed or concise (default) Shows where UltraGenTM modules were synthesized Shows timing, device resource utilization, and pinout.
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VHDL Training
Back Annotation
Back Annotation means passing design information back to a previous design stage Physical Information back annotation Pin numbers (schematic or control file) FLASH370 node numbers (control file) Simulation value back annotation (schematic) For control file, use Files->Annotate in Galaxy
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VHDL Training
On-line Help and Documentation

On-line help is available from the Help menu in Galaxy Shows how to create projects and compile designs Describes the use of compiler options and synthesis directives All Warp documentation is also available on-line (700+ pages!) Files are in Adobe Acrobat format User can install Acrobat reader from Warp CD
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VHDL Training
Exercise #3: The Schematic

en(0) dir status[7:0] gnd dir data[7:0]
CY74FCT245T CY74FCT373T CY74FCT373T nOE T/R CY74FCT373T nOE LE nOE LE
gnd en(1)
nOE LE
control[7:0]
en(2) en(3)
addr[1:0] nvalid dir en[0:3]

PLD
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VHDL Training
Exercise #3
Use Warp to compile the VHDL design description of the truth table below:
addr nvalid en(0) en(1) en(2) en(3) dir L H H H H H H H
b"00" b"00" b"01" b"01" b"10" b"10" b"11" b"11"
'0' '1' '0' '1' '0' '1' '0' '1'
L L H L L L L L
H H H H L H H H
L L L L L L H L
L H H H L H H H
Write the Architecture for the given Entity (next) Save design in file named ex3.vhd
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VHDL Training
Exercise #3: The Entity Declaration

the entity declaration is as follows:
LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY ex3 IS PORT ( addr: IN std_logic_vector(1 DOWNTO 0); nvalid: IN std_logic; en: BUFFER std_logic_vector(0 TO 3); dir: OUT std_logic ); addr END ex3;
nvalid
dir en
PLD
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VHDL Training
Exercise #3: Instructions

Synthesize the design using Warp Click on the Galaxy icon in the Warp R4 group Create a new project Use the VHDL Editor to create your file click on new in the Edit portion of the Galaxy window optionally, open ex3.vhd Select the Add... item from the Edit menu to add your .vhd file to the project. Highlight the file and click on set top Use the device menu to select the 22v10 as the target device
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VHDL Training
Exercise #3 Instructions (contd.)

Click on smart in the compile section of Galaxy Correct any VHDL syntax errors Click on the magnifying glass button to locate your error. Save and re-compile until all errors are gone Simulate the design using the Nova functional simulator Select Nova from the Tools menu Use Nova Quick Reference handout for simulation (please review first)
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VHDL Training
Exercise #3: Solution The Architecture

The architecture is as follows:
ARCHITECTURE archex3 OF ex3 IS BEGIN en(0) <= '0' WHEN (addr = "00" AND nvalid = '0') ELSE '1'; en(1) <= (NOT addr(1)) AND addr(0) AND (NOT nvalid) ; en(2) <= '0' WHEN (addr = "10" AND nvalid = '0') ELSE '1'; en(3) <= addr(1) AND addr(0) AND (NOT nvalid); dir <= '0' WHEN (addr = "00" AND nvalid = '0') OR (addr = "10" AND nvalid = '0') ELSE '1' ; END archex3;
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VHDL Training
Aggregates and Subscripts

Aggregate assignment concatenates signals together Good for creating a bus from several inputs Concatenation operator can be used as well Same number of array elements on both sides of <=
tmp <= (a,b,c,d); tmp <= a & b & c & d;
Signals can be pulled from larger vectors Good for grouping outputs as an alias Sizes on both sides must match
rw <= ctrl(0); ce <= ctrl(1); oe <= ctrl(2); highcount <= count(7 DOWNTO 4);
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VHDL Training
Exercise #3: Alternate Solution

Using With/Select and aggregates
ARCHITECTURE archex3 OF ex3 IS SIGNAL control : std_logic_vector(2 DOWNTO 0); SIGNAL outputs : std_logic_vector(0 TO 4); BEGIN control <= addr & nvalid; WITH control SELECT outputs <= "00100" WHEN "000", "10101" WHEN "001", "11101" WHEN "010", "10101" WHEN "011", "10000" WHEN "100", "10101" WHEN "101", "10111" WHEN "110", "10101" WHEN "111", "-----" WHEN OTHERS; en <= outputs(0 TO 3); dir <= outputs(4); END archex3;
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VHDL Training
Designs that use Registers

There are two methods of utilizing and generating flip-flops: Instantiate (place) a flip-flop or a component that contains a flip-flop Use a process that is sensitive to a clock edge
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Instantiating a registered component

Example: Using LPM library
LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE WORK.lpmpkg.all ; ENTITY registered IS PORT ( d, clk: IN std_logic; q: OUT std_logic); END registered;
d clk
ARCHITECTURE archregistered OF registered IS BEGIN flipflop: Mff generic map (lpm_width=>1,lpm_fftyp=>lpm_dff) PORT MAP (data=>d,clock=>clk,enable=>one,q=>q); END archregistered;
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Registers in Behavioral VHDL

Example: a D-type flip-flop
ENTITY registered IS PORT ( d, clk: IN std_logic; q: OUT std_logic); END registered; ARCHITECTURE archregistered OF registered IS BEGIN flipflop: PROCESS (clk) BEGIN IF clkEVENT AND clk = '1' THEN q <= d; END IF; END PROCESS flipflop; END archregistered;
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VHDL Training
Registers in Behavioral VHDL

The synthesis compiler infers that a register is to be created for which signal q is the output because The clock (clk) is in the sensitivity list The construct, clkevent and clk = 1, appears in the process The clkevent and clk = 1 statement implies that subsequent signal assignments occur on the risingedge of the clock The absence of an else clause in the if-then statement implies that if the clkevent and clk = 1 condition is not fulfilled (i.e. not a rising-edge), q will retain its value until the next assignment occurs (this is referred to as implied memory)
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VHDL Training
A Registered Process (1)

A 4-bit counter with synchronous reset
USE WORK.std_arith.ALL; ... upcount: PROCESS (clk) BEGIN IF clkEVENT AND clk= '1' THEN IF reset = '1' THEN count <= "0000"; -- or x"0" instead ELSE count <= count + 1; END IF; END IF; END PROCESS upcount;
This process is only sensitive to changes in clk, i.e., it will become active only when the clock transitions
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A 4-bit counter with asynchronous reset
USE WORK.std_arith.ALL; ...
upcount: PROCESS (clk, rst) BEGIN IF rst = '1' THEN

count <= x"0";
ELSIF clkEVENT AND clk = '1' THEN count <= count + 1; END IF; END PROCESS upcount;
This process is sensitive to changes in both clk and rst, i.e., it will become active during clock or reset transitions.
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VHDL Training

A 4-bit loadable counter with asynchronous reset
USE WORK.std_arith.ALL; ...
upcount: PROCESS (clk, rst) BEGIN IF rst = '1' THEN count <= x"0" ; ELSIF clkEVENT AND clk = '1' THEN IF load = '1' THEN count <= data; ELSE count <= count + 1; END IF; END IF;
END PROCESS upcount;

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The WAIT statement

This is another method to activate a process The WAIT statement is a sequential statement which suspends the execution of a process until the condition specified becomes valid (true) i.e., an implied sensitivity list, e.g.,
sync: PROCESS BEGIN WAIT UNTIL clock='1'; IF enable='1' THEN q_out <= d_in; ELSE q_out <= '0'; END IF; END PROCESS sync;
enable d_in clock

D Q
q_out
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Implicit memory
Signals in VHDL have a current value and may be scheduled for a future value If the future value of a signal cannot be determined, a latch will be synthesized to preserve its current value Advantages: Simplifies the creation of memory in logic design Disadvantages: Can generate unwanted latches, e.g., when all of the options in a conditional sequential statement are not specified
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Implicit memory: Example of incomplete specification

ARCHITECTURE archincomplete OF incomplete IS BEGIN im_mem: PROCESS (a,b) BEGIN IF a = '1' THEN c <= b;
a c b
END IF;
END PROCESS im_mem; END archincomplete;
Note: the incomplete specification of the IF...THEN... statement causes a latch to be synthesized to store the previous state of c
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Implicit memory: Example of complete specification

ARCHITECTURE archcomplete OF complete IS BEGIN no_mem: PROCESS (a, b) BEGIN IF a = '1' THEN c <= b; ELSE c <= '0'; END IF; END PROCESS no_mem; END archcomplete;
a b
The conditional statement is fully specified, and this causes the process to synthesize to a single gate
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The rules to avoid implicit memory

To avoid the generation of unexpected latches always terminate an IF...THEN... statement with an ELSE clause cover all alternatives in a CASE statement define every alternative individually, or terminate the CASE statement with a WHEN OTHERS... clause, e.g.,
CASE select IS WHEN b"100" => key x <= a WHEN b"010" => key WHEN b"001" => key WHEN OTHERS => key END CASE;
<= first; AND b; <= second; <= third; <= none;
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VHDL Training
Exercise #4
Making use of the previous examples, write an entity/architecture pair for the following design:
ENC
COUNTER
DATA LD CLOCK
DIN LD ENC
COUNT Q
4
COMPARATOR
RST
RESET (sync)
P P=Q Q
REGISTER
DIN ENR Q ENR

4
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Exercise #4: Instructions

The target device is a CY7C371I-110JC Compile, synthesize, and simulate your solution with Warp Create a new project for this exercise in the directory Select New from the File menu in Galaxy Hints: Use 2 processes and a concurrent statement Use code for register, counter, and comparator shown previously Incorporate count enable logic in count process
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LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY ex4 IS PORT ( clock, reset, enc, enr, ld: IN std_logic; data: IN std_logic_vector (3 DOWNTO 0); count: BUFFER std_logic_vector(3 DOWNTO 0)); END ex4; USE WORK.std_arith.ALL; -- for counter and ultragen ARCHITECTURE archex4 OF ex4 IS SIGNAL comp: std_logic; SIGNAL regout: std_logic_vector (3 DOWNTO 0); BEGIN reg: PROCESS (clock) BEGIN IF clock'EVENT AND clock = '1' THEN IF enr = '1' THEN regout <= data; END IF; END IF; END PROCESS reg;
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VHDL Training
Exercise #4: Solution (contd.)

cntr: PROCESS (clock) BEGIN IF clock'EVENT AND clock = '1' THEN IF reset = '1' THEN count <= "0000"; ELSIF ld = '1' THEN count <= data; ELSIF enc = '1' AND comp = '0' THEN count <= count + 1; END IF; END IF; END PROCESS cntr; comp <= '1' WHEN regout = count ELSE '0'; END archex4;
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State machines
Moore Machines A finite state machine in which the outputs change due to a change of state Mealy Machines A finite state machine in which the outputs can change asynchronously i.e., an input can cause an output to change immediately
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Moore machines
Outputs may change only with a change of state Multiple implementations include: Arbitrary state assignment outputs must be decoded from the state bits combinatorial decode registered decode Specific state assignment outputs may be encoded within the state bits one-hot encoding
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Moore state machine implementations (1)

Outputs decoded from state bits Combinatorial decode Outputs are decoded combinatorially from the current state outputscomb = f(present state)
Inputs
Logic
State Registers
Output Logic
Outputs
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Moore state machine implementations (2)

Outputs decoded from state bits Registered decode Outputs are registered; decode of outputs is in parallel with decode of next state outputsreg = f(previous state, inputs)
Next State Logic
Current State
State Registers
Inputs
Output Logic
Output Outputs Registers
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Moore State Machine Implementations (3)

Outputs encoded within state bits Example:
State s1 s2 s3 Output 1 0 1 0 Output 2 0 0 1 State Encoding 00 01 10
Note: Both bits of the state encoding are used as outputs
Inputs
Logic
State Registers
Outputs
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Example: A wait state generator

State diagram:
PWAIT
RESET (async) IDLE 00 REQ retry_out='1' REQ RETRY 01 PWAIT ack_out='1'
ACK 10
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Example: The entity declaration

The entity declaration remains essentially the same for each implementation (except for the entity name) e.g.,
LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY moore1 IS PORT ( clock, reset: IN std_logic; req, pwait: IN std_logic; retry_out, ack_out: OUT std_logic); END moore1;
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Example: Solution 1
Combinatorial outputs decoded from the state bits
ARCHITECTURE archmoore1 OF moore1 IS TYPE fsm_states IS (idle, retry, ack); SIGNAL wait_gen : fsm_states; BEGIN fsm: PROCESS (clock, reset) BEGIN IF reset = '1' THEN wait_gen <= idle; -- asynchronous reset ELSIF clock'EVENT AND clock = '1' THEN CASE wait_gen IS WHEN idle => IF req = '0' THEN wait_gen <= retry; ELSE wait_gen <= idle; END IF; WHEN retry => IF pwait='1' THEN wait_gen <= ack; ELSE wait_gen <= retry; END IF;
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Example: Solution 1 (contd.)

WHEN ack => wait_gen <= idle; WHEN OTHERS => wait_gen <= idle; END CASE; END IF; END PROCESS fsm; retry_out <= '1' WHEN (wait_gen = retry) ELSE '0'; ack_out <= '1' WHEN (wait_gen = ack) ELSE '0'; END archmoore1;
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Registered outputs decoded from the state bits

ARCHITECTURE archmoore2 OF moore2 IS TYPE fsm_states IS (idle, retry, ack); SIGNAL wait_gen: fsm_states; BEGIN fsm: PROCESS (clock, reset) BEGIN IF reset = '1' THEN wait_gen <= idle; retry_out <= '0'; ack_out <= '0'; ELSIF clock'EVENT AND clock = '1' THEN retry_out <= '0'; -- a default assignment, could do ack_out too CASE wait_gen IS WHEN idle => IF req = '0' THEN wait_gen <= retry; retry_out <= '1'; ack_out <= '0'; ELSE wait_gen <= idle; ack_out <= '0'; END IF;
Example: Solution 2
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WHEN retry => IF pwait = '1' THEN wait_gen <= ack; ack_out <= '1'; ELSE wait_gen <= retry; retry_out <= '1'; ack_out <= '0'; END IF; => wait_gen <= idle; ack_out <= '0';
WHEN ack
WHEN OTHERS => wait_gen <= idle; ack_out <= '0'; --END CASE; -END IF; -END PROCESS fsm; -END archmoore2; --
note must define what happens to ack_out here or a latch will be synthesized to preserve its current state
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Example: Solution 3
Outputs encoded within the state bits
ARCHITECTURE archmoore3 OF moore3 IS SIGNAL wait_gen: std_logic_vector(1 DOWNTO 0); CONSTANT idle: std_logic_vector(1 DOWNTO 0) := CONSTANT retry: std_logic_vector(1 DOWNTO 0) := CONSTANT ack: std_logic_vector(1 DOWNTO 0) := BEGIN fsm: PROCESS (clock, reset) BEGIN IF reset = '1' THEN wait_gen <= idle; ELSIF clock'EVENT AND clock = '1' THEN CASE wait_gen IS WHEN idle => IF req = '0' THEN wait_gen <= ELSE wait_gen <= END IF;
"00"; "01"; "10";
retry; idle;
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WHEN retry => IF pwait = '1' THEN wait_gen <= ack; ELSE wait_gen <= retry; END IF; WHEN ack => wait_gen <= idle; WHEN OTHERS => wait_gen <= idle; END CASE; END IF; END PROCESS fsm; retry_out <= wait_gen(0); ack_out <= wait_gen(1); END archmoore3;
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State Machines: One-hot Encoding

One state per flip-flop in FPGA-type architectures reduces the next state logic requires fewer levels of logic cells enables high-speed state machines (> 100MHz) in CPLDs reduces the number of product terms can eliminate expander product terms (i.e. reduce delays, and increase operating speed) but, uses more macrocells
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Example: One-hot-one Solution

ARCHITECTURE archmoore4 OF moore4 IS TYPE fsm_states IS (idle, retry, ack); ATTRIBUTE state_encoding OF fsm_states:TYPE IS one_hot_one; SIGNAL wait_gen: fsm_states; BEGIN fsm: PROCESS (clock, reset) BEGIN IF reset = '1' THEN wait_gen <= idle; ELSIF clock'EVENT AND clock = '1' THEN CASE wait_gen IS WHEN idle => IF req = '0' THEN wait_gen <= retry; ELSE wait_gen <= idle; END IF;
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Example: One-hot-one Solution (contd.)

=> IF pwait = '1' THEN wait_gen <= ack; ELSE wait_gen <= retry; END IF; WHEN ack => wait_gen <= idle; WHEN OTHERS => wait_gen <= idle; END CASE; END IF; END PROCESS fsm; -- Assign state outputs retry_out <= '1' WHEN (wait_gen = retry) ELSE '0'; ack_out <= '1' WHEN (wait_gen = ack) ELSE '0'; END archmoore4; WHEN retry
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Moore Machines: Summary

Outputs decoded from the state bits flexibility during the design process using enumerated types allows automatic state assignment during compilation Outputs encoded within the state bits manual state assignment using constants the state registers and the outputs are merged reduces the number of registers but, may require more product terms One-Hot encoding reduces next state decode logic high speed operation but, uses more registers
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Mealy Machines
Outputs may change with a change of state OR with a change of inputs Mealy outputs are non-registered because they are functions of the present inputs
State Registers
Inputs
Logic
Outputs
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Example: The Wait State Generator

State diagram:
PWAIT
RESET (async)
IDLE 0 REQ RETRY 1 RETRY_OUT='1' if, ENABLE='0'
REQ PWAIT
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Example: Mealy Machine Solution

ARCHITECTURE archmealy1 OF mealy1 IS TYPE fsm_states IS (idle, retry); SIGNAL wait_gen: fsm_states; BEGIN fsm: PROCESS (clock, reset) BEGIN IF reset = '1' THEN wait_gen <= idle; ELSIF clock'EVENT AND clock = '1' THEN CASE wait_gen IS WHEN idle => IF req = '0' THEN wait_gen <= retry; ELSE wait_gen <= idle; END IF; WHEN retry => IF pwait = '1' THEN wait_gen <= idle; ELSE wait_gen <= retry; END IF; WHEN OTHERS => wait_gen <= idle; END CASE; END IF; END PROCESS fsm; retry_out <= '1' WHEN (wait_gen = retry AND enable='0') ELSE '0'; END archmealy1;
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Exercise #5
Design a state machine to implement the function shown below:
RESET POS
hold
POS RESET
sample
extend
clear='0' track='1'
track='1' if, busy='0'
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LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY ex5 IS PORT ( clock, pos, busy, reset: IN std_logic; clear, track: OUT std_logic); END ex5; ARCHITECTURE archex5 OF ex5 IS TYPE states IS (hold, sample, extend); ATTRIBUTE state_encoding OF states:TYPE IS one_hot_one; SIGNAL fsm: states; BEGIN clear <= '0' WHEN fsm = sample ELSE '1'; track <= '1' WHEN (fsm = sample) OR (fsm = extend AND busy = '0') ELSE '0';
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Exercise #5: Solution (contd.)

sync: PROCESS (clock) BEGIN IF clock'EVENT AND clock = '1' THEN IF reset = '1' THEN fsm <= hold; -- synchronous reset ELSE CASE fsm IS WHEN hold => IF pos = '0' THEN fsm <= sample; ELSE fsm <= hold; END IF; WHEN sample => fsm <= extend; WHEN extend => fsm <= hold; WHEN OTHERS => fsm <= hold; END CASE; END IF; -- reset = '1' END IF; -- clk'EVENT AND clk = '1' END PROCESS sync; END archex5;
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Hierarchical design methodology

Advantages: Allows the re-use of common building blocks Components (VHDL models or schematic symbols) can be created, tested and held for later use Smaller components can be more easily integrated with other blocks Designs are more readable Designs are more portable The design task can be split among several members of a team
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VHDL Training

PROGRAMMABLE LOGIC DESIGN WITH VHDL

Why Use VHDL?

PLD Design Flow

1997 Cypress Semiconductor, rev 2.5.3

Synthesis Fitting Place&Route

1997 Cypress Semiconductor, rev 2.5.3

VHDL Design Descriptions

The ARCHITECTURE body describes the content of the design

1997 Cypress Semiconductor, rev 2.5.3

VHDL Entity/Architecture Pairs: 2-Input And Function

1997 Cypress Semiconductor, rev 2.5.3

1997 Cypress Semiconductor, rev 2.5.3

Example Entity declaration

rst d[7:0] clk

1997 Cypress Semiconductor, rev 2.5.3

The Entity Declaration

1997 Cypress Semiconductor, rev 2.5.3

1997 Cypress Semiconductor, rev 2.5.3

IEEE 1076 Types

1997 Cypress Semiconductor, rev 2.5.3

IEEE 1076 TYPES (contd.)

1997 Cypress Semiconductor, rev 2.5.3

1997 Cypress Semiconductor, rev 2.5.3

Entity Declaration Example

1997 Cypress Semiconductor, rev 2.5.3

Exercise #1: The Entity

1997 Cypress Semiconductor, rev 2.5.3

Exercise #1: Solution

Boolean equations (also referred to as dataflow):

The Architecture Declaration

1997 Cypress Semiconductor, rev 2.5.3

Architecture Body Styles : Behavioral

1997 Cypress Semiconductor, rev 2.5.3

Architecture Body Styles : Dataflow

1997 Cypress Semiconductor, rev 2.5.3

Architecture Body Styles : Structural

1997 Cypress Semiconductor, rev 2.5.3

Comparing Architecture Styles

Mixing Architecture Styles

The Process Statement

1997 Cypress Semiconductor, rev 2.5.3

The Process (contd.)

1997 Cypress Semiconductor, rev 2.5.3

Combinational Logic w/ Boolean Equations

1997 Cypress Semiconductor, rev 2.5.3

Selective Signal Assignment: with-select-when

Combinational Logic w/ Selective Signal Assignment

with s select x <= a when 00 , b when 01 , c when 10 , d when others ;

1997 Cypress Semiconductor, rev 2.5.3

with int_value select x <= a when 0 to 3, b when 4 | 6 | 8 , c when 10 , d when others ;

1997 Cypress Semiconductor, rev 2.5.3

Conditional Signal Assignment: when-else

WHEN condition1 ELSE WHEN condition2 ELSE

WHEN conditionn ELSE ;

Combinational Logic w/ Conditional Signal Assignment

1997 Cypress Semiconductor, rev 2.5.3

Combinational Logic w/ Conditional Signal Assignment

Combinational Logic w/ Sequential Statements

1997 Cypress Semiconductor, rev 2.5.3