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VHDL Tutorial Chapter 8

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49 views9 pages

VHDL Tutorial Chapter 8

Uploaded by

wizardvenkat
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPT, PDF, TXT or read online on Scribd
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Programming Mechanics

Sudhakar Yalamanchili, Georgia Institute of Technology, 2006

(1)

Design Units
Basic unit of VHDL programming is a design unit which is one of the following
package header

Primary Design Units

entity binding

configuration

Secondary Design Units

architecture-3 architecture-2 architecture-1

package body

(2)

Name Spaces
Multiple instances of a name can exist
Local names are the default Provide the full path name for a name

Visibility of names
Visibility of a name follows the hierarchy
Declared in a package all design units that use the package Entity in architectures used for this entity Architecture processes used in the architecture Process in the process Subprogram subprogram

(3)

Compilation, Naming and Linking

Design File

VHDL Analyzer

Library WORK
full_adder vhd .

Library STD
textio.vhd

Library IEEE
std_logic_11 64.vhd

half_adder vhd .

standard .vhd

.....
Sources and analyzed design units

Design unit names are used to construct intermediate file names The libraries WORK and STD
(4)

Project Management
Use packages to separate synthesizable from simulatable Change secondary design units without recompilation of the design hieararchy Use several configurations
Record/compare different architectures

(5)

Basic Steps: Simulation


Analysis (Compilation) and Analysis Order Primary vs. secondary design units Organization of design units and files

architecture structural of full_adder is component half_adder is port (a, b : in std_logic; sum, carry : out std_logic); end component half_adder; component or_2 is port (a, b : in std_logic; c : out std_logic); end component or_2; signal s1, s2, s3 : std_logic; begin H1: half_adder port map (a => In1, b => In2, sum => s1, carry=> s3); H2: half_adder port map (a => s1, b => c_in, sum => sum, carry => s2); O1: or_2 port map (a => s2, b => s3, c => c_out); end architecture structural;

(6)

Compilation Dependencies
entity board is port (.

dependency
Micro 3284

entity micro3284 is port (..

Compilation dependencies follow hardware dependencies


Changes in the interface Architecture changes can be insulated

Note that recompilation is interpreted as a change


Locating architectures and entities in the same file Creates dependencies that may not in fact exist

(7)

Basic Steps: Simulation


Elaboration Of the hierarchy produces a netlist of processes
s1 s3 s5

s2

s4

s6

Of declarations
Generics and type checking

Storage allocation Initialization

(8)

Basic Steps: Simulation


Initialization
All processes are executed until suspended by wait statements or sensitivity lists All nets initialized to default or user specified values Initialize simulation time

Simulation
Discrete event simulation Two step model of time
Set net values Execute all affected processes and schedule new values for nets

Simulator step time

(9)

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