Scribd
Upload
38 views

VHDL Course Contents

This course outline covers digital system design using VHDL over 13 weeks. Students will learn VHDL concepts and language features, and apply them in weekly labs to design systems like multiplexers, decoders, counters, adders, multipliers, and finite state machines. Later labs involve hierarchical design, subprograms, testbenches, and reusable parameterized designs. The course aims to teach hardware modeling, VHDL, and designing for Xilinx FPGAs through hands-on projects.

Uploaded by

Ahmed Saeed
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as PDF, TXT or read online on Scribd
38 views

VHDL Course Contents

This course outline covers digital system design using VHDL over 13 weeks. Students will learn VHDL concepts and language features, and apply them in weekly labs to design systems like multiplexers, decoders, counters, adders, multipliers, and finite state machines. Later labs involve hierarchical design, subprograms, testbenches, and reusable parameterized designs. The course aims to teach hardware modeling, VHDL, and designing for Xilinx FPGAs through hands-on projects.

Uploaded by

Ahmed Saeed
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 1

Course Outlines

DigitalSystemDesignusingVHDL

Eng. Ahmed Saeed

HardwareModelingOverview DesignMethodology VHDLLanguageConcepts SignalsandDataTypes VHDLOperatorsandExpressions Lab1:VHDLSimulationandRTLVerification ConcurrentStatements Lab2:MUXs,Decoders,andE3coder SequentialStatements ControlledOperationStatements Lab3:Dlatch,DFF,andCounterwithload BehavioraltoRTLCoding AdvancedProcessStatements Lab4:AddersandMultipliers FiniteStateMachines Lab5:Finitestatemachinesexamples Lab6:Differentexamples HierarchicalDesign Lab7:connectingcomponents Modeling&Simulation:Subprograms,DesignAttributes,AccessTypes& Blocks Lab8:Modeling TestbenchStimulus Lab9:ModelTestbench UtilizingTextIO Lab10:TextIOTestbench RTLDesign Lab11:RTLandScalableDesign DesignReuseandParameterizedDesign Lab12:FSMandScalableDesign TargetingXilinxFPGAs Lab13:ImplementandDownload Project

You might also like