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Folded Cascode Opamp

This document describes testbench circuits to characterize the performance of a folded cascode op amp design, including: open loop gain, phase margin, unity gain bandwidth, slew rate, common mode input range, offset voltage, output swing, total harmonic distortion, settling time, equivalent input noise, and closed loop response. Seven test circuits are shown to measure these key parameters.

Uploaded by

sinamahani
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© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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99 views6 pages

Folded Cascode Opamp

This document describes testbench circuits to characterize the performance of a folded cascode op amp design, including: open loop gain, phase margin, unity gain bandwidth, slew rate, common mode input range, offset voltage, output swing, total harmonic distortion, settling time, equivalent input noise, and closed loop response. Seven test circuits are shown to measure these key parameters.

Uploaded by

sinamahani
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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Designing Folded Cascode Op Amp with testbench Circuits

By

: sina mahani (90413333)

Parameters
Open loop DC-Gain Phase Margin Unity Gain BW Slew Rate Common-mode Input Range Output Voltage Swing THD Voltage Offset load capacitors power dissipation Settling time Total output noise voltage(for 1kHz) Equivalent input noise at vin(for 1kHz) 54 dB 65.8 1.32 MHz 630 MHz 330 1.2 *226 mv or 2.4

7.87% 175.3 v 919.64 mv 0.5 pF 1.3 mwatt (without bias circuit) ______ 6.9n sq v/hz 167n /rt hz

Folded Cascode Opamp with CMFB


V DD

M9

M10 1.2V MF1 d1 gf1 MF2

d2

vg4 M3 M4 gf2

In+

M1 s1

M2

v in
In-

V O
500uA
OUTOUT+

gf3 MF5 MF3 MF4 MF6

V O

sf3

V CM
MF9

sf4

M11

c1

c2

M5

M6

MF10

vg6

500uA

s11

s5

s6

M12

M7

M8

MF7

MF8

vg8

GND
2

1. Test circuit for calculating Open-loop gain, Phase Margin, Unity-gain, 3dB frequency and Total output noise
Vdd 1.8V VCC R3 1G
Vi+

Vss 0V

Vo+ Vi+

Vo+

Vdd

AC

+
Vs

E1

C3

Vi+

R7
0

Vo+
S 0

1G

VoR8

E
S1

+
E2

C4

1
Vi-

1G VoVo-

Vss

Vi-

Vi-

1G R4

VS1 1.2V

1. Test circuit for calculating Input Common-mode Range


Vdd 1.8V VCC Vss 0V R4 500k
VC7

Vin+

Vo+

R7 E
O
S 0

Vo+ 1G

Vdd

E1

C7

Vi+ 500k

R9 Vo+ HB3 VoR10

VS

E
s1

C8 E2

R8 500k

1G Vo-

Vss

ViVin-

Vo-

VC8

500k R3

1.2V VS1

2. Test circuit for calculating Offset-voltage


Vdd 1.8V VCC R4 500k
VC7

Vss 0V

294uv
R7 E
0 Vi+

Vo+
Vo+

Vdd

E3

C7

Vi+ 500k

R11 Vo+ HB3 VoR12

1G

O
S

Vin

E
s1

+
E4

C8

R8
Vi-

1G Vo-

Vss

Vi-

Vo-

500k

294uv
VC8

500k R3

1.2V Vin1

3. Test circuit for calculating Output Swing


Vdd 1.8V VCC R1 100k
VC3

Vss 0V

R2 E
OV Vin
S

Vo+

Vdd

E1

C3

Vi+ 1k

R7 Vo+ HB1 VoR8

1G

E
S1

+
E2

C4

R3 1k

1G Vo-

Vss

Vi-

VC4

100k R4

1.2V Vin1

4. Test circuit for calculating slew rate


Vdd 1.8V VCC R1 0.1K
Vc3

Vss

0V

Vo+ Vi+

R2 E

Vo+

Vdd

AC

+
Vin

E1

C3

Vi+ 0.1K

Vo+
S

Vo-

E
s1

+
E2

C4

R3 0.1K
Vi-

Vss

Vi-

VoVo-

Vc4

0.1K R4

1.2V

Vin1

5. Test circuit for calculating Settling Time


Vdd 1.8V VCC R1 0.1K
Vc3

Vss

0V

Vo+ Vi+

R2 E

Vo+

Vdd

AC

+
Vin

E1

C3

Vi+ 0.1K

Vo+
S

Vo-

E
s1

+
E2

C4

R3 0.1K
Vi-

Vss

Vi-

VoVo-

Vc4

0.1K R4

1.2V

Vin1

6. Test circuit for calculating Total Harmonic Distortion


Vdd 1.8V VCC R4 10k
VC1

Vss 0V

R1 E

Vo+

Vdd

AC

E1

C1

Vi+ 10k

R3 Vo+ HB1 VoR6

1G

Vs

E
S1

+
E2

C2

R2 10k

1G Vo-

Vss

Vi-

VC2

10k R5

1.2V Vs1

7. Test circuit for Close-Loop


Vdd 1.8V VCC R1
VC3

Vss 0V

500K

R2 E
0 AC

VoVi+

Vdd

- + E1
Vin
S

C3

Vi+ 100K

Vo+ VoC4 1 R3 100K


VC4 ViVo+

- + E2 E
s1

Vss
500K R4

Vi-

1.2V VS1

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