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Cac B tach song thuc hin trn Simulink cua Matlab

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M ngun chuong trinh VHDL
Khi DE2: la khi kt ni cac khi khac thanh mt h thng
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
USE ieee.std_logic_unsigned.all;
USE work.float_types.all;
USE work.float_components.all;
USE work.float_constants.all;
USE work.sram_types.all;
USE work.sram_components.all;
USE work.lfsr_components.all;
USE work.ann_types.all;
USE work.ann_components.all;
USE work.detector_components.all;
USE work.display_types.all;
USE work.display_components.all;
USE work.lcd_types.all;
USE work.lcd_components.all;
USE work.transmitter_components.all;
USE work.awgn_components.all;
USE work.cordiccos_components.all;
USE work.receiver_components.all;
USE work.sign_components.all;
USE work.pattern_constants.all;
USE work.data_types.all;
USE work.sum_signal_types.all;
USE work.despread_user_types.all;
ENTITY de2 IS
PORT (
-------------------- Clock Input --------------------
-- CLOCK_27 : IN STD_LOGIC; -- On Board 27 MHz
CLOCK_50 : IN STD_LOGIC; -- On Board 50 MHz
-- EXT_CLOCK : IN STD_LOGIC; -- External Clock
-------------------- Push Button --------------------
KEY : IN STD_LOGIC_VECTOR(3 DOWNTO 0); -- Pushbutton[3:0]
-------------------- DPDT Switch --------------------
SW : IN STD_LOGIC_VECTOR(17 DOWNTO 0); -- Toggle Switch[17:0]
------------------------ LED ------------------------
LEDG : OUT STD_LOGIC_VECTOR(8 DOWNTO 0); -- LED Green[8:0]
LEDR : OUT STD_LOGIC_VECTOR(17 DOWNTO 0); -- LED Red[17:0]
-------------------- SRAM Interface ----------------
SRAM_DQ : INOUT STD_LOGIC_VECTOR(15 DOWNTO 0); --SRAM Data bus 16 Bits
SRAM_ADDR : OUT STD_LOGIC_VECTOR(17 DOWNTO 0);
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--SRAM Address bus 18 Bits
SRAM_UB_N : OUT STD_LOGIC; --SRAM High-byte Data Mask
SRAM_LB_N : OUT STD_LOGIC; --SRAM Low-byte Data Mask
SRAM_WE_N : OUT STD_LOGIC; --SRAM Write Enable
SRAM_CE_N : OUT STD_LOGIC; --S RAM Chip Enable
SRAM_OE_N : OUT STD_LOGIC; --SRAM Output Enable
-------------------- LCD Module 16X2 ----------------
LCD_ON : OUT STD_LOGIC; -- LCD Power ON/OFF
LCD_BLON : OUT STD_LOGIC; -- LCD Back Light ON/OFF
LCD_RW : OUT STD_LOGIC; -- LCD Read/Write Select; 0 = Write; 1 = Read
LCD_EN : OUT STD_LOGIC; -- LCD Enable
LCD_RS : OUT STD_LOGIC; -- LCD Command/Data Select; 0 = Command; 1 = Data
LCD_DATA : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0) -- LCD Data bus 8 bits
);
END ENTITY de2;
ARCHITECTURE de2 OF de2 IS
-- detector nhan dang vector mau nao da duoc phat
signal detector_ready : std_logic := '0';
signal detector_inputs : despread_user_vector(3 downto 0) ;
signal detector_outputs : std_logic_vector(11 downto 0);
signal detector_training_mse : float := float_half; -- ham muc tieu duoc chon bang switch
signal detector_training_mse_sel,receiver_sel : std_logic := '0';
signal detector_mse16 : float ;
-- ann
signal ann_alpha : float ; -- := float_1_10; -- toc ho hoc 0.1
signal ann_inputs : float_vector(4 - 1 downto 0) := (others => float_zero);
signal ann_outputs : float_vector(4 - 1 downto 0) := (others => float_zero);
signal ann_targets : float_vector(4- 1 downto 0) := (others => float_zero);
signal ann_ready : std_logic := '0';
signal ann_mse : float := float_zero;
signal ann_mode : ann_mode := idle;
-- alu
SIGNAL float_alu_ready : STD_LOGIC := '0';
SIGNAL float_alu_a, float_alu_b, float_alu_c : float := float_zero;
SIGNAL float_alu_mode,float_alu_mode_trans,float_alu_mode_receiver,
float_alu_mode_ann,float_alu_mode_det,float_alu_mode_awgn,
float_alu_mode_cordiccos : float_alu_mode := idle;
SIGNAL float_alu_a_trans, float_alu_b_trans: float := float_zero;
SIGNAL float_alu_a_receiver, float_alu_b_receiver: float := float_zero;
SIGNAL float_alu_a_ann, float_alu_b_ann: float := float_zero;
SIGNAL float_alu_a_det, float_alu_b_det: float := float_zero;
SIGNAL float_alu_a_awgn, float_alu_b_awgn: float := float_zero;
SIGNAL float_alu_a_cordiccos, float_alu_b_cordiccos: float := float_zero;
-- sram
signal sram_address : sram_address := (others=>'0');
signal sram_input : sram_data := (others=>'0');
signal sram_output : sram_data := (others=>'0');
signal sram_mode : sram_mode := read;
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signal sram_ready : std_logic := '0';
-- lfsr
signal lfsr_output : std_logic_vector(15 downto 0) := (others=>'0');
-- lcd
signal lcd_dd : CHAR_VECTOR(0 to 31) := (others => x"00");
-- display
signal display_mode : display_mode := training;
signal display_mode_sel : STD_LOGIC_VECTOR(2 downto 0) := "000";
-- signal user_data: CHAR_VECTOR (1 downto 0); -- user1 va user 0

-- transmitter
signal trans_inputs :data_vector(4 - 1 downto 0); -- trans_inputs(i)(j) i la so user, j(std_logic)
-- la so bit cua user do
signal trans_outputs :sum_signal_vector (2 downto 0);
-- trans_outputs(i)(j) i la so luong nhom pn = so
-- luong phat user, j kieu float la so luong bit cua 1 pn
signal trans_ready : std_logic := '0';
-- awgn
signal awgn_inputs, awgn_outputs: sum_signal_vector (2 downto 0);
-- ung voi 3 bit duoc phat cua moi user
signal xigman : float := float_zero;
signal awgn_ready : std_logic := '0';
-- cordiccos
signal cordiccos_inputs, cordiccos_outputs : float ;
signal cordiccos_ready : std_logic :='1'; -- trang thai bao san sang hoat dong
signal cordiccos_enable : std_logic :='0'; -- khong mo cho hoat dong
-- receiver
signal receiver_inputs :sum_signal_vector (2 downto 0);
-- receiver_inputs(i)(j) giong trans_outputs(i)(j)
-- la mot i la so luong nhom pn, j(float) so luong bit cua 1 pn
signal receiver_outputs :despread_user_vector(3 downto 0);
-- receiver_outputs(i)(j) i la so user,
-- j (float) so bit phat cua user do
signal receiver_ready : std_logic := '0';
-- sign
signal sign_inputs :despread_user_vector(3 downto 0);
-- sign_inputs(i)(j) giong receiver_outputs(i)(j) i la so user,
-- j (float) so bit phat cua user do
signal sign_outputs :std_logic_vector (11 downto 0);
-- sign_outputs(i) i la so luong tong bit phat tuong ung voi 4 user
signal sign_ready : std_logic := '0';
-- de2
signal temp_ledr : std_logic_vector(11 downto 0):= (others=>'0');
signal char_snr : char_vector (0 to 1);
signal insnr : std_logic_vector (3 downto 0);

BEGIN
-- transmitter
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transmitter0: transmitter
port map (
NOT KEY(0) OR NOT KEY(2), -- key2 tinh toan cac ngo vao moi khoi huan luyen lai
CLOCK_50,
trans_inputs,
trans_outputs,
trans_ready,

float_alu_a_trans,
float_alu_b_trans,
float_alu_c,
float_alu_mode_trans,
float_alu_ready,

detector_ready -- chay sau khi da huan luyen xong
);

-- cordiccos
cordiccos0: cordiccos
port map (
NOT KEY(0) OR NOT KEY(2), -- tinh toan cac bit moi ma khong can huan luyen lai mang
CLOCK_50,
cordiccos_inputs,
cordiccos_outputs,
cordiccos_enable,
cordiccos_ready,

float_alu_a_cordiccos, -- ngo vao khong duoc noi da chieu
float_alu_b_cordiccos,
float_alu_c,
float_alu_mode_cordiccos,
float_alu_ready
);

-- awgn
awgn0: awgn
port map (
NOT KEY(0) OR NOT KEY(2), -- tinh toan cac bit moi ma khong can huan luyen lai mang
CLOCK_50,
awgn_inputs,
xigman,
awgn_outputs,
awgn_ready,

float_alu_a_awgn,-- ngo vao khong duoc noi da chieu
float_alu_b_awgn,
float_alu_c,
float_alu_mode_awgn,
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float_alu_ready,

cordiccos_inputs,
cordiccos_outputs,
cordiccos_enable,
cordiccos_ready,

trans_ready, -- awgn chay sau khoi transmitter
lfsr_output
);

-- receiver
receiver0: receiver
port map (
NOT KEY(0) OR NOT KEY(2), -- tinh toan cac bit moi ma khong can huan luyen lai mang
CLOCK_50,
receiver_inputs,
receiver_outputs,
receiver_ready,

float_alu_a_receiver, -- ngo vao khong duoc noi da chieu
float_alu_b_receiver,
float_alu_c,
float_alu_mode_receiver,
float_alu_ready,

awgn_ready
);

-- alu
float_alu0 : float_alu
port map (
NOT KEY(0) OR NOT KEY(2),
CLOCK_50,

float_alu_a,
float_alu_b,
float_alu_c,
float_alu_mode,

float_alu_ready
);

-- SRAM
sram0 : sram
port map (
NOT KEY(0),
CLOCK_50,
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sram_address,
sram_input,
sram_output,
sram_mode,
sram_ready,
SRAM_DQ,
SRAM_ADDR,
SRAM_UB_N,
SRAM_LB_N,
SRAM_WE_N,
SRAM_CE_N,
SRAM_OE_N
);

-- LFSR
lfsr0 : lfsr
port map(
NOT KEY(0),
CLOCK_50,
lfsr_output
);

-- ann
ann0 : ann
generic map (
4,
8,
4
)
port map (
NOT KEY(0) OR NOT KEY(1),
CLOCK_50,
ann_mode,
ann_alpha,
ann_inputs,
ann_targets,
ann_outputs,
ann_mse,
ann_ready,

float_alu_a_ann,
float_alu_b_ann,
float_alu_c,
float_alu_mode_ann,
float_alu_ready,

sram_address,
sram_input,
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sram_output,
sram_mode,
sram_ready,

lfsr_output
);

-- detector
detector0 : detector
generic map (
4,
8,
4
)
port map (
NOT KEY(0) OR NOT KEY(1),
CLOCK_50,
NOT KEY(3),
PATTERN_TRAINING_DATA,
PATTERN_TRAINING_TARGET,
detector_training_mse,
detector_inputs,
detector_outputs,
detector_ready,
detector_mse16, --hien thi mse

ann_mode,
ann_alpha,
ann_inputs,
ann_targets,
ann_outputs,
ann_mse,
ann_ready,

float_alu_a_det,
float_alu_b_det,
float_alu_c,
float_alu_mode_det,
float_alu_ready
);

-- lcd
lcd0 : lcd
port map (
NOT KEY(0),
CLOCK_50,
lcd_dd,
LCD_ON,
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LCD_BLON,
LCD_RW,
LCD_EN,
LCD_RS,
LCD_DATA
);

-- display
display0 : display
port map (
NOT KEY(0),
CLOCK_50,
display_mode,
SW(1), -- hien thi bo thu duoc lua chon
char_snr,
lcd_dd
);
-- sign : quyet dinh nguong
sign0 : sign
port map (
NOT KEY(0) OR NOT KEY(2),
CLOCK_50,
sign_inputs,
sign_outputs,
sign_ready,
receiver_ready
);
-- noi cac khoi voi nhau
awgn_inputs <= trans_outputs;
receiver_inputs <= awgn_outputs;
sign_inputs <= receiver_outputs;
detector_inputs <= receiver_outputs;
-- chon chon khoi alu
process (float_alu_a,float_alu_b,float_alu_mode,
float_alu_a_ann,float_alu_b_ann,float_alu_mode_ann,
float_alu_a_trans,float_alu_b_trans,float_alu_mode_trans,
float_alu_a_receiver,float_alu_b_receiver,float_alu_mode_receiver,
float_alu_a_det,float_alu_b_det,float_alu_mode_det,
float_alu_a_awgn,float_alu_b_awgn,float_alu_mode_awgn,
float_alu_a_cordiccos,float_alu_b_cordiccos,float_alu_mode_cordiccos,
ann_ready, detector_ready, trans_ready, receiver_ready,
awgn_ready, cordiccos_enable)
begin
if ann_ready ='0' then -- khoi detector chua huan luyen xong
float_alu_a <= float_alu_a_ann; -- cho phep ann dieu khien alu
float_alu_b <= float_alu_b_ann;
float_alu_mode <= float_alu_mode_ann;
elsif detector_ready= '0' then
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float_alu_a <= float_alu_a_det; -- sau khi huan luyen ann tinh tong mse
float_alu_b <= float_alu_b_det;
float_alu_mode <= float_alu_mode_det;
elsif trans_ready ='0' then
float_alu_a <= float_alu_a_trans; -- cho phep transmitter dieu khien alu
float_alu_b <= float_alu_b_trans;
float_alu_mode <= float_alu_mode_trans;
elsif awgn_ready ='0' then
if cordiccos_enable='0' then -- co enable cordiccos khong neu co phai chuyen khoi alu
float_alu_a <= float_alu_a_awgn;
float_alu_b <= float_alu_b_awgn;
float_alu_mode <= float_alu_mode_awgn;
else
float_alu_a <= float_alu_a_cordiccos; -- cho phep awgn chay
float_alu_b <= float_alu_b_cordiccos;
float_alu_mode <= float_alu_mode_cordiccos;
end if;
elsif receiver_ready ='0' then
float_alu_a <= float_alu_a_receiver; -- cho phep receiver dieu khien alu
float_alu_b <= float_alu_b_receiver;
float_alu_mode <= float_alu_mode_receiver;
else
float_alu_a <= float_alu_a_ann; -- cac truong hop con lai ann dieu khien alu
float_alu_b <= float_alu_b_ann;
float_alu_mode <= float_alu_mode_ann;
end if;
end process;
-- display mode select
display_mode_sel <= detector_ready & ann_ready & not KEY(3);
with display_mode_sel select
display_mode <=
training when "000"|"001"|"010"|"011",
running when "100"|"101"|"111",
idle when "110";
-- bits indicator
LEDG(8) <= detector_ready; -- huan luyen xong led 8 mau xanh se hien thi
LEDR(5) <= trans_ready;
LEDR(4) <= awgn_ready;
LEDR(3) <= receiver_ready;
-- mean squared error display
LEDR(2 downto 0) <= detector_mse16(31 downto 29);
LEDG(7 downto 0) <= detector_mse16(28 downto 21); -- 8so
-- training accuracy select
detector_training_mse_sel <= SW(0); -- co the dung 1 sw de lua chon con 1 switch
-- la quyet dinh coi no la matched filter hay neural
with detector_training_mse_sel select
detector_training_mse <=
float_1_10 when '0', -- 0.1/16
Trang 160
float_1_4 when '1'; -- 0.25/16
-- lua chon matched filter hay neural network detector
receiver_sel <= SW(1); -- lua chon bo thu
with receiver_sel select
temp_ledr(11 downto 0) <= -- output user_data display
detector_outputs when '0', -- bo thu ann va phai hien thi neural net
sign_outputs when '1'; -- bo thu matched filter hien thi matched filter
-- input switch
trans_inputs(3) <= SW(17 downto 15);
trans_inputs(2) <= SW(14 downto 12);
trans_inputs(1) <= SW(11 downto 9);
trans_inputs(0) <= SW(8 downto 6);
insnr <= SW(5 downto 2);
---------------------------------------
LEDR(17 downto 6) <= temp_ledr(11 downto 0);
-- hien thi so dB
snr0: PROCESS (insnr, xigman, char_snr )
BEGIN
CASE insnr IS
WHEN "0000" => xigman <= float_one; -- 1
char_snr(0) <= x"30"; char_snr(1)<=x"30"; -- gia tri 00 dB
WHEN "0001" => xigman <= float_7943; -- 0.7943
char_snr(0) <= x"30"; char_snr(1)<=x"32"; -- gia tri 02 dB
WHEN "0010" => xigman <= float_6310; -- 0.6310
char_snr(0) <= x"30"; char_snr(1)<=x"34"; -- gia tri 04 dB
WHEN "0011" => xigman <= float_5012; -- 0.5012
char_snr(0) <= x"30"; char_snr(1)<=x"36"; -- gia tri 06 dB
WHEN "0100" => xigman <= float_3981; -- 0.3981
char_snr(0) <= x"30"; char_snr(1)<=x"38"; -- gia tri 08 dB
WHEN "0101" => xigman <= float_3162; -- 0.3162
char_snr(0) <= x"31"; char_snr(1)<=x"30"; -- gia tri 10 dB
WHEN "0110" => xigman <= float_2512; -- 0.2512
char_snr(0) <= x"31"; char_snr(1)<=x"32"; -- gia tri 12 dB
WHEN "0111" => xigman <= float_1995; -- 0.1995
char_snr(0) <= x"31"; char_snr(1)<=x"34"; -- gia tri 14 dB
WHEN "1000" => xigman <= float_1585; -- 0.1585
char_snr(0) <= x"31"; char_snr(1)<=x"36"; -- gia tri 16 dB
WHEN "1001" => xigman <= float_1259; -- 0.1259
char_snr(0) <= x"31"; char_snr(1)<=x"38"; -- gia tri 18 dB
WHEN OTHERS => xigman <= float_1000; -- 0.1000
char_snr(0) <= x"32"; char_snr(1)<=x"30"; -- gia tri 20 dB
END CASE;
END PROCESS;
END ARCHITECTURE de2;




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Chuong trinh khi Detector
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.float_types.all;
USE work.ann_types.all;
USE work.pattern_types.all;
USE work.despread_user_types.all;
USE work.data_types.all;
USE work.target_types.all;
PACKAGE detector_components IS
COMPONENT detector IS
GENERIC (
N_I : INTEGER := 4; -- number input neuron
N_H : INTEGER := 8; -- number of hidrent neuron
N_O : INTEGER := 4 -- number of output neuron
);
PORT (
reset, clock, go : IN STD_LOGIC; -- bit go quyet dinh idle hay run
training_data : IN pattern_vector(0 to 16-1); -- tong so mau la 16 mau
training_target : IN target_vector(0 to 16-1); -- 4 bit ra tuong ung voi 16 mau
training_mse : IN FLOAT;
inputs : IN despread_user_vector(3 downto 0);
-- inputs(i)(j) i la user, j(float) so bit 1 user phat di
outputs : OUT std_logic_vector(11 downto 0); -- inputs(i)(j) i la user, j(float)
-- so bit 1 user phat di mang neural lam ro mau
ready : OUT STD_LOGIC;
mse16 : OUT FLOAT;

ann_mode : INOUT ann_mode;
ann_alpha : OUT float;
ann_inputs : OUT float_vector(4 - 1 downto 0); -- mang 4 ngo vao
ann_targets : OUT float_vector(4 - 1 downto 0);
ann_outputs : IN float_vector(4 - 1 downto 0);
ann_mse : IN float;
ann_ready : IN STD_LOGIC;

float_alu_a : OUT float;
float_alu_b : OUT float;
float_alu_c : IN float;
float_alu_mode : INOUT float_alu_mode;
float_alu_ready : IN STD_LOGIC

);
END COMPONENT detector;
END PACKAGE detector_components;

LIBRARY ieee;
Trang 162
USE ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
USE work.float_types.all;
USE work.float_constants.all;
USE work.float_components.all;
USE work.ann_types.all;
USE work.pattern_types.all;
USE work.despread_user_types.all;
USE work.data_types.all;
USE work.target_types.all;

ENTITY detector IS
GENERIC (
N_I : INTEGER := 4;
N_H : INTEGER := 8;
N_O : INTEGER := 4
);
PORT (
reset, clock, go : IN STD_LOGIC;
training_data : IN pattern_vector(0 to 16-1); -- tong so mau la 16 mau
training_target : IN target_vector(0 to 16-1 ); -- 4 bit ra tuong ung voi 16 mau
training_mse : IN FLOAT; -- hang so muc tieu
inputs : IN despread_user_vector(3 downto 0); -- inputs(i)(j) i la user, j(float)
-- so bit 1 user phat di
outputs : OUT std_logic_vector (11 downto 0); -- inputs(i)(j) i la user, j(float) so
-- bit 1 user phat di mang neural lam ro mau
ready : OUT STD_LOGIC;
mse16 : OUT FLOAT;

ann_mode : INOUT ann_mode;
ann_alpha : OUT float;
ann_inputs : OUT float_vector(4 - 1 downto 0);
ann_targets : OUT float_vector(4 - 1 downto 0);
ann_outputs : IN float_vector(4 - 1 downto 0);
ann_mse : IN float; -- sai so tinh tu mang neuron
ann_ready : IN STD_LOGIC;

float_alu_a : OUT float;
float_alu_b : OUT float;
float_alu_c : IN float;
float_alu_mode : INOUT float_alu_mode;
float_alu_ready : IN STD_LOGIC
);
END ENTITY detector;
ARCHITECTURE detector OF detector IS
constant alpha : float := float_1_10; -- thiet lap toc do hoc la 0.1
Trang 163

signal i,j,k : integer range 0 to 32 := 0;
signal epoch : integer range 0 to 3000 := 0;

type states is
( init,
train,
train_validate,
train_validate_wait,
train_validate_complete,
mse_compare,
mse_compare_wait,
mse_compare_wait_complete,
new_epoch,
init_weight,
run,
run_complete,
run_validate,
run_sign_decide_wait,
run_sign_decide_wait_complete,
run_sign_decide_user_complete,
run_bit_complete,
idle );
signal state : states := init;

signal fp_cmp_enable, fp_cmp_agb : std_logic := '0';
signal fp_cmp_a, fp_cmp_b : float := float_zero;
signal temp_outputs: data_vector(4-1 downto 0); --data_vector(i)(j) i la so
-- luong user, j(bit) l so luong bit phat cua 1 user
signal mse: float:= float_zero;
BEGIN
ann_alpha <= alpha;
fp_cmp0 : fp_cmp port map (reset, fp_cmp_enable, clock, fp_cmp_a, fp_cmp_b,
fp_cmp_agb); -- su dung bo so sanh
fsm : PROCESS(clock, reset) IS
BEGIN
IF (reset = '1') THEN
ready <= '0';
state <= init;
mse <= float_zero;
epoch <= 0;
ELSIF (clock = '1' AND clock'event) THEN
IF (ann_mode /= idle) THEN -- phai thuc hien xong
ann_mode <= idle; -- vi ann_mode la inout nen moi co truong hop nay
ELSIF (float_alu_mode /= idle) THEN
float_alu_mode <= idle;
ELSIF (ann_ready = '0' OR float_alu_ready ='0') THEN -- khoi nay chay truoc
ELSE
Trang 164
CASE state IS
WHEN init =>
ready <= '0';
state <= train;
j <= 0; -- lay tung khoi 4 so float
k <= 0;
i <= 0; -- vhdl khong phan biet chu hoa chu thuong
epoch <= 0;
mse <= float_zero ;
WHEN train =>
ann_inputs <= training_data(j); --j so luong mau trong tap mau
-- ann_inputs(0) la user0
FOR i IN 0 to 4-1 LOOP
IF (training_target(k)(i)='1') THEN -- j= so luong mau
ann_targets(i) <= float_none; -- -1
-- training_target(0) la ngo ra mong muon user0
ELSE
ann_targets(i) <= float_one; -- +1
END IF;
END LOOP;
ann_mode <= learn; -- chuyen sang trang thai hoc
state <= train_validate ;
WHEN train_validate =>
float_alu_a <= mse; -- tong loi sau 16 lan huan luyen
float_alu_b <= ann_mse; -- loi mse 1 lan huan luyen
float_alu_mode <= add;
state <= train_validate_wait;
WHEN train_validate_wait => -- no lam
mse <= float_alu_c;
state <= train_validate_complete;
WHEN train_validate_complete =>
IF (k = 16-1) THEN -- vong lap k chay khoang 2 lan reset
k <= 0;
ELSE
k <= k + 1;
END IF;
IF (j = 16 - 1) THEN -- neu j= 15 tuc la da het mau huan luyen
j <= 0; -- j chinh la so mau can huan luyen
state <= mse_compare;
mse16 <= mse; -- lay ngo ra mse16 hien thi sai so cho de nhin
ELSE
j <= j + 1;
state <= train;
END IF;
WHEN mse_compare =>
fp_cmp_a <= training_mse ; -- hang so muc tieu mong muon dat duoc
fp_cmp_b <= mse; -- loi binh phuong cua 16 mau
fp_cmp_enable <= '1';
Trang 165
state <= mse_compare_wait;
WHEN mse_compare_wait => -- no lam
state <= mse_compare_wait_complete;
WHEN mse_compare_wait_complete =>
fp_cmp_enable <= '0';
IF (fp_cmp_agb = '0') THEN -- tuc la training_mse(hsh luyen) < mse thi tiep
-- tuc huan luyen cho toi khi nao nho hon moi thoi
mse <= float_zero; -- bat dau lai chu ky huan luyen (epoch)moi
state <= new_epoch;
ELSE
j <= 0; -- reset j
ready <= '1';
mse16 <= mse; -- lay ngo ra mse16
state <= idle; -- huan luyen xong chuyen sang idle
END IF;
WHEN new_epoch =>
IF epoch = 2000 THEN -- mot epoch la mot lan huan luyen het 16 mau
epoch <= 0;
state <= init_weight;
ELSE
epoch <= epoch + 1;
state <= train; -- tiep tuc huan luyen
END IF;
WHEN init_weight =>
ann_mode <= init;
state <= train; -- tiep tuc huan luyen

-- j da reset
WHEN run =>
FOR i IN 0 TO 4-1 LOOP
ann_inputs(i) <= inputs(i)(j); -- user thu i, va bit thu j cua user do
END LOOP;
ann_mode <= run; -- cho ann chay, ngoi cho cho no san sang ann_ready='1'
state <= run_complete;
WHEN run_complete =>
i <= 0; -- reset i
state <= run_validate;
WHEN run_validate =>
fp_cmp_a <= ann_outputs(i); -- i ngo ra cua neuron thu i
fp_cmp_b <= float_zero; -- so sanh voi 0 neu >= thi la bit 1 va nguoc lai
fp_cmp_enable <= '1';
state <= run_sign_decide_wait;
WHEN run_sign_decide_wait =>
state <= run_sign_decide_wait_complete;
WHEN run_sign_decide_wait_complete =>
fp_cmp_enable <= '0';
IF (fp_cmp_agb = '1') THEN -- neu a > 0 thi ngo ra do la bit 0
temp_outputs(i)(j) <= '0'; -- i la so user, j la bit thu tu cua user do,
Trang 166
-- 0 giai ma chuyen sang gia tri std luon
ELSE
temp_outputs(i)(j) <= '1'; -- 1
END IF;
state <= run_sign_decide_user_complete; -- het 1 luot 4 user chua
WHEN run_sign_decide_user_complete =>
IF (i = 4 - 1) THEN -- i =4 tat ca ngo ra mang neural deu duoc xet,
-- het 1 luot user
i <= 0;
state <= run_bit_complete; -- het tat ca cac bit trong 1 user chua
ELSE
i <= i + 1;
state <= run_validate; -- chay theo user
END IF;
WHEN run_bit_complete =>
IF j = 3-1 THEN -- chay theo bit phat ton so co 3bit phat tren mot user
j <= 0;
state <= idle; -- xong tat ca cac bit trong user
outputs <= temp_outputs(3)(2downto 0)&
temp_outputs(2)(2 downto 0)&
temp_outputs(1)(2 downto 0)&
temp_outputs(0)(2 downto 0);-- up date lai ngo ra co su thay doi vi tri
ELSE
j <= j + 1;
state <= run;
END IF;

-- i, j da reset
WHEN idle =>
IF (go = '1') THEN -- bit go =1 thi luon o vi tri run (KEY(3))
state <= run;
ELSE
state <= idle;
END IF;
WHEN others =>
state <= init;
END CASE;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE detector;
Khi TRANSMITTER
LIBRARY ieee;
USE ieee.std_logic_1164.all;
package data_types is
subtype data is std_logic_vector(2 downto 0); -- data la 3 switch gat truoc khi trai pho
Trang 167
-- hay bang tan goc, luon la subtype
type data_vector is array( NATURAL range <> ) of data ;
-- data_vector(i)(j) i la so luong user,
-- j(bit) l so luong bit phat cua 1 user
end package data_types;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
package pn_types is
subtype pn is std_logic_vector(0 to 14); -- mot ma pn (pseudo noise) co 15 bit la chuoi
--m sequence da thuc sinh bac 4
type pn_vector is array( NATURAL range <> ) of pn;
-- pn_vector(i)(j) i la so luong nhom pn,
--j(bit) la so bit cua mot ma pn
end package pn_types;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.pn_types.all;
package user_types is
subtype user is pn_vector(2 downto 0); -- la du lieu sau khi trai pho mot user
--co 3 nhom pn, 1 pn co 7 bit
type user_vector is array( NATURAL range <> ) of user;
-- user_vector(i)(j) la so luong user,
--j so luong nhom pn cua mot user
end package user_types;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.float_types.all;
package sum_signal_types is
subtype sum_signal is float_vector(14 downto 0); -- tuong ung voi chieu
-- dai cua mot ma pn
type sum_signal_vector is array( NATURAL range <> ) of sum_signal;
-- sum_signal_vector(i)(j) i so bit cua mot user
--phat di,(vi da tinh tong cac user 4 thanh 1),
--j la do loi trai pho pn tuong ung voi 1 bit
end package sum_signal_types;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.float_types.all;
USE work.data_types.all;
USE work.pn_types.all;
USE work.user_types.all;
USE work.sum_signal_types.all;

PACKAGE transmitter_components IS
COMPONENT transmitter IS
PORT (
reset, clock: IN STD_LOGIC;
inputs : IN data_vector(4 - 1 downto 0); -- truoc khi trai pho
Trang 168
outputs : OUT sum_signal_vector (2 downto 0);
-- sum_signal_vector(i)(j) i so bit cua mot user phat
--di,(vi da tinh tong cac user 4 thanh 1),
--j la do loi trai pho pn tuong ung voi 1 bit
ready : OUT STD_LOGIC;
float_alu_a : OUT float;
float_alu_b : OUT float;
float_alu_c : IN float;
float_alu_mode : INOUT float_alu_mode; -- che do cua alu
float_alu_ready : IN STD_LOGIC; -- alu da san sang hoat dong
detector_ready : IN STD_LOGIC
);
END COMPONENT transmitter;
END PACKAGE transmitter_components;

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.float_types.all;
USE work.data_types.all;
USE work.pn_types.all;
USE work.user_types.all;
USE work.sum_signal_types.all;
USE work.float_constants.all;

ENTITY transmitter IS
PORT (
reset, clock: IN STD_LOGIC;
inputs : IN data_vector(4 - 1 downto 0); -- tx_data du lieu phat di
outputs : OUT sum_signal_vector (2 downto 0);
ready : OUT STD_LOGIC;
float_alu_a : OUT float;
float_alu_b : OUT float;
float_alu_c : IN float;
float_alu_mode : INOUT float_alu_mode; -- float_alu_mode da dinh nghia trong float
float_alu_ready : IN STD_LOGIC;

detector_ready : IN STD_LOGIC
);
END ENTITY transmitter;

ARCHITECTURE transmitter OF transmitter IS
type states is
( init,
spread_spectrum,
spread_spectrum_complete,
sum_channel_add,
sum_channel_add_complete,
sum_channel_pn_complete,
Trang 169
sum_channel_user_complete,
sum_channel_pn_group_complete,
idle );
signal state : states := init;
-- user data after spreading
signal tx_user: user_vector(3 downto 0); -- tuong ung voi 4 user, moi user co 4 pn_vector
--tuong ung voi 4 bit data, mot pn co 7 std_logic
signal i,j,k : integer range 0 to 20;
-- pseudo noise code
-- constant pn0: pn := "1101 0111 1000 100";
-- constant pn1: pn := "1011 0110 1101 101";
-- constant pn2: pn := "0011 1101 0110 010";
-- constant pn3: pn := "1001 1110 0111 100";
constant pn: pn_vector(3 downto 0) := ("100111100111100","001111010110010",
"101101101101101","110101111000100");
-- sum signal y(t)
signal y : sum_signal_vector (2 downto 0):= (others =>(float_zero, float_zero, float_zero,
float_zero, float_zero, float_zero, float_zero, float_zero, float_zero, float_zero, float_zero,
float_zero, float_zero, float_zero, float_zero)) ;
-- co 4 user, moi user mang 7 float tuong ung voi chieu dai pn
-- y(0) la tong tat ca ca bit0, cua user0, user1, user2, user3
BEGIN
outputs <= y; -- theo dung thu tu giam dan
fsm : PROCESS(clock, reset) IS
BEGIN
IF (reset = '1') THEN
ready <= '0';
state <= init;
y <= (others =>(float_zero, float_zero, float_zero, float_zero, float_zero,
float_zero, float_zero, float_zero, float_zero, float_zero,
float_zero, float_zero, float_zero, float_zero, float_zero)) ;
ELSIF (clock = '1' AND clock'event) THEN
IF (float_alu_mode /= idle) THEN -- cho cho toi khi no roi
float_alu_mode <= idle ;
ELSIF (float_alu_ready = '0' or detector_ready='0') THEN
-- transmitter chay sau khoi detector phai
--huan luyen xong hay ready='1'
ELSE
CASE state IS
WHEN init =>
ready <= '0'; -- chu hoan thanh cong viec
state <= spread_spectrum;
y <= (others =>(float_zero, float_zero, float_zero, float_zero, float_zero,
float_zero, float_zero, float_zero, float_zero, float_zero,
float_zero, float_zero, float_zero, float_zero, float_zero)) ;
-- khoi tao gan kieu khac vao trong
--phai gan kieu tin hieu
i <= 0;
Trang 170
WHEN spread_spectrum =>
-- user(i)
for j in 0 to 3-1 loop -- chay xong vong for thi toan bo bit
--cua user0 da duoc trai pho
if inputs(i)(j) ='0' then -- i la user, j la bit gat cua user do
tx_user(i)(j) <= pn(i); -- bit 0 thi khong dao bit 1 thi dao ma pn
else
tx_user(i)(j) <= not pn(i); -- j so nhom pn
end if;
end loop;
state <= spread_spectrum_complete;
WHEN spread_spectrum_complete =>
if i = 4 - 1 then -- da het 4 user chua
i <= 0; -- reset i,j
j <= 0;
state <= sum_channel_add ; -- di tinh kenh truyen tong
else
i <= i+1; -- tang len trai pho user tiep theo
state <= spread_spectrum;
end if;
WHEN sum_channel_add => -- tinh tin hieu tren kenh truyen chung
if tx_user(i)(j)(k)='1' then -- i la user, j la nhom pn, k bit trong mot pn
float_alu_a <= float_2582; -- 1/sqrt(15)
else
float_alu_a <= float_n2582; -- -1/sqrt(15)
end if;
float_alu_b <= y(j)(k); -- tinh tong thu nhat cua cac bit0 trong 4 user chi con
--2 thong so j la nhom pn, k(float) so bit trong mot pn
float_alu_mode <= add; -- user da mat
state <= sum_channel_add_complete;
WHEN sum_channel_add_complete =>
y(j)(k) <= float_alu_c; -- ket qua luu lai y(j)(k) j la so bit phat cua mot
--user(so nhom pn), k la bit trong mot pn
state <= sum_channel_pn_complete; -- het so bit cua mot pn chua
WHEN sum_channel_pn_complete =>
if k= 15-1 then -- cong het so bit pn0 trong user0
--vao nhom pn0 cua y0
k <= 0;
state <= sum_channel_user_complete;
else
k <= k + 1;
state <= sum_channel_add;
end if;
WHEN sum_channel_user_complete => -- cong lai theo user
if i= 4-1 then -- tang so user quay lai cho toi khi
--het 4 user
i <= 0;
state <= sum_channel_pn_group_complete;
Trang 171
else
i <= i + 1;
state <= sum_channel_add;
end if;
WHEN sum_channel_pn_group_complete =>
if j= 3-1 then -- tang so nhom pn, quay lai cho toi khi het 3 nhom pn
j <= 0;
state <= idle;
else
j <= j + 1;
state <= sum_channel_add; -- quay lai cong tiep
end if;
WHEN idle =>
ready <= '1'; -- da sang sang tuc la da tinh toan xong
state <= idle; -- nhay tai cho
WHEN others =>
state <= init;
END CASE;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE transmitter;
Khi AWGN
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.float_types.all;
USE work.float_constants.all;
USE work.float_components.all;
USE work.despread_user_types.all;
USE work.data_types.all;
USE work.sum_signal_types.all;

PACKAGE awgn_components IS
COMPONENT awgn IS
PORT (
reset, clock: IN STD_LOGIC ;
inputs : IN sum_signal_vector (2 downto 0); -- kenh truyen chung co 3 mau tuong ung
--voi 3 bit duoc phat moi user
xigman : IN float ; -- 4 bit nhap muc do nhieu trang
outputs : OUT sum_signal_vector (2 downto 0); -- 12 bit cua 4 user theo thu tu, moi
-- user phat 3 bit
ready : OUT STD_LOGIC ; -- 12 thong bao minh da lam xong viec

float_alu_a : OUT float;
float_alu_b : OUT float;
float_alu_c : IN float;
Trang 172
float_alu_mode : INOUT float_alu_mode; -- che do cua alu
float_alu_ready : IN STD_LOGIC; -- alu da san sang hoat dong
cordiccos_beta : OUT float;
cordiccos_out : IN float;
cordiccos_enable : OUT STD_LOGIC; -- dieu khien cordiccos
cordiccos_ready : IN STD_LOGIC; -- tinh xong chua
transmitter_ready : IN STD_LOGIC; -- chay sau khoi receiver
lfsr_output : IN STD_LOGIC_VECTOR(15 downto 0)
);
END COMPONENT awgn;
END PACKAGE awgn_components;

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.float_types.all;
USE work.float_constants.all;
USE work.float_components.all;
USE work.despread_user_types.all;
USE work.data_types.all;
USE work.sum_signal_types.all;
ENTITY awgn IS
PORT (
reset, clock: IN STD_LOGIC ;
inputs : IN sum_signal_vector (2 downto 0); -- kenh truyen chung co 3 mau tuong ung
--voi 3 bit duoc phat moi user
xigman : IN float ; -- 4 bit nhap muc do nhieu trang
outputs : OUT sum_signal_vector (2 downto 0); -- 12 bit cua 4 user theo thu tu,
--moi user phat 3 bit
ready : OUT STD_LOGIC ; -- 12 thong bao minh da lam xong viec
float_alu_a : OUT float;
float_alu_b : OUT float;
float_alu_c : IN float;
float_alu_mode : INOUT float_alu_mode; -- che do cua alu
float_alu_ready : IN STD_LOGIC; -- alu da san sang hoat dong

cordiccos_beta : OUT float;
cordiccos_out : IN float;
cordiccos_enable : OUT STD_LOGIC; -- dieu khien cordiccos
cordiccos_ready : IN STD_LOGIC; -- tinh xong chua

transmitter_ready : IN STD_LOGIC; -- chay sau khoi receiver
lfsr_output : IN STD_LOGIC_VECTOR(15 downto 0)
);
END ENTITY awgn;

ARCHITECTURE awgn OF awgn IS
signal temp,x1,x2,fx1,fx2,n : float := float_zero;
signal i,j : integer range 0 to 16;
Trang 173
--signal temp_outputs: data_vector(3 downto 0);
type states is
( init,
init_variables,
calculate_fx1_log,
calculate_fx1_log_complete,
calculate_negative_fx1,
calculate_nfx1_sqrt,
calculate_nfx1_sqrt_complete,
calculate_fx2_beta_mul,
calculate_fx2_beta_mul_complete,
calculate_fx2_cos_wait, -- cho tinh ham cos
calculate_fx2_cos_complete,
calculate_fx2_sqrt2_mul,
calculate_fx2_sqrt2_mul_complete,
calculate_n_mul,
calculate_n_mul_complete,
calculate_n_xigman_mul,
calculate_n_xigman_mul_complete,
calculate_signal_noise_add,
calculate_signal_noise_add_complete,
pncode_complete,
bits_complete,
idle );
signal state : states := init;

BEGIN
fsm : PROCESS(clock, reset) IS
BEGIN
IF (reset = '1') THEN
ready <= '0';
state <= init;
ELSIF (clock = '1' AND clock'event) THEN
IF (float_alu_mode /= idle) THEN -- cho cho troi khi alu roi
float_alu_mode <= idle ;
ELSIF (float_alu_ready = '0' or transmitter_ready = '0' ) THEN
-- receiver chay sau transmitter
ELSE
CASE state IS
WHEN init =>
ready <= '0'; -- chu hoan thanh cong viec
i <= 0;
j <= 0;
cordiccos_enable <= '0'; -- chac chan khong chay cordiccos
state <= init_variables;
-- khoi tao bien ngau nhien x1 x2
WHEN init_variables =>
x1 <= '0' & "011111" & lfsr_output(15) & '0' & lfsr_output(14 downto 0)
Trang 174
& "00000000";
x2 <= '0' & "011111" & lfsr_output(6) & '0' & lfsr_output(15 downto 7)&
lfsr_output(5 downto 0) & "00000000";
-- 8 so exess nho thua 01111111 thi e-127 chac chan am va so se be thua 1
state <= calculate_fx1_log;
-- tinh gia tri cua fx1= sqrt(-log(x1))
WHEN calculate_fx1_log =>
float_alu_a <= x1;
float_alu_mode <= log;
state <= calculate_fx1_log_complete;
WHEN calculate_fx1_log_complete =>
fx1 <= float_alu_c;
state <= calculate_negative_fx1;
WHEN calculate_negative_fx1 =>
fx1(31) <= not fx1(31); -- hoac gan luon '0' cung duoc vi chac duong
state <= calculate_nfx1_sqrt;
WHEN calculate_nfx1_sqrt =>
float_alu_a <= fx1;
float_alu_mode <= sqrt;
state <= calculate_nfx1_sqrt_complete;
WHEN calculate_nfx1_sqrt_complete =>
fx1 <= float_alu_c;
state <= calculate_fx2_beta_mul;
-- tinh gia tri fx2=sqrt(2)cos(2pix2)
-- tinh beta= 2pi*x2
WHEN calculate_fx2_beta_mul =>
float_alu_a <= x2;
float_alu_b <= float_2pi;
float_alu_mode <= mul;
state <= calculate_fx2_beta_mul_complete;
WHEN calculate_fx2_beta_mul_complete =>
cordiccos_beta <= float_alu_c; -- ket qua luu lai bien beta
cordiccos_enable <= '1'; -- mo tinh toan ham cos, dong thoi chuyen alu
--qua do luon
state <= calculate_fx2_cos_wait;
WHEN calculate_fx2_cos_wait=>
IF cordiccos_ready='0' THEN
state <= calculate_fx2_cos_wait;
ELSE
state <= calculate_fx2_cos_complete; -- roi vao vong lap
END IF;
WHEN calculate_fx2_cos_complete =>
cordiccos_enable <= '0'; -- khoi cordiccos ready, ngung ham cos
--chuyen modecos ve init va lay lai bo alu
fx2 <= cordiccos_out; -- lay gia tri ham
state <= calculate_fx2_sqrt2_mul;
WHEN calculate_fx2_sqrt2_mul =>
float_alu_a <= fx2;
Trang 175
float_alu_b <= float_sqrt2;
float_alu_mode <= mul;
state <= calculate_fx2_sqrt2_mul_complete;
WHEN calculate_fx2_sqrt2_mul_complete =>
fx2 <= float_alu_c; -- ket qua luu lai bien fx2
state <= calculate_n_mul;
-- tinh gia tri n=fx1*fx2;
WHEN calculate_n_mul =>
float_alu_a <= fx2;
float_alu_b <= fx1;
float_alu_mode <= mul;
state <= calculate_n_mul_complete;
WHEN calculate_n_mul_complete =>
n <= float_alu_c; -- ket qua luu lai bien fx2
state <= calculate_n_xigman_mul;
-- tinh them do lech chuan xigman*n
WHEN calculate_n_xigman_mul =>
float_alu_a <= xigman;
float_alu_b <= n;
float_alu_mode <= mul;
state <= calculate_n_xigman_mul_complete;
WHEN calculate_n_xigman_mul_complete =>
temp <= float_alu_c; -- ket qua luu lai temp
state <= calculate_signal_noise_add;
WHEN calculate_signal_noise_add =>
float_alu_a <= inputs(i)(j); -- sum_signal_vector(i)(j) i so bit cua mot
--user phat di,(vi da tinh tong cac user 4
--thanh 1), j la do loi trai pho pn tuong
--ung voi 1 bit
float_alu_b <= temp; -- xigman*n
float_alu_mode <= add;
state <= calculate_signal_noise_add_complete;
WHEN calculate_signal_noise_add_complete =>
outputs(i)(j) <= float_alu_c; -- luu vao tin hieu co nhieu
state <= pncode_complete; -- xem da het chieu dai mot ma pn chua
WHEN pncode_complete =>
if j= 15-1 then
j <= 0;
state <= bits_complete;
else
j <= j+1;
state <= init_variables; -- quay lai khoi tao tinh tiep
end if;
WHEN bits_complete => -- xem coi het cac bit chua
if i= 3-1 then
i <= 0;
state <= idle; -- hoan tat cuoi cung
else
Trang 176
i <= i+1;
state <= init_variables; -- quay lai khoi tao tinh tiep
end if; -- ket thuc phep tinh
WHEN idle =>
ready <= '1'; -- da sang sang tuc la da tinh toan xong
state <= idle; -- nhay tai cho
WHEN others =>
state <= init;
END CASE;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE awgn;
Khi RECEIVER
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.float_types.all;
package despread_user_types is
subtype despread_user is float_vector(2 downto 0); -- tuong ung voi 3 bit phat
type despread_user_vector is array( NATURAL range <> ) of despread_user;
-- depread_user_vector(i)(j) i la so user,
-- j(float) la so du lieu cua 1 user
end package despread_user_types;

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.float_types.all;
USE work.despread_user_types.all;
USE work.sum_signal_types.all;
USE work.pn_types.all;

PACKAGE receiver_components IS
COMPONENT receiver IS
PORT (
reset, clock: IN STD_LOGIC;
inputs : IN sum_signal_vector (2 downto 0); -- kenh truyen chung co 4 mau
-- tuong ung voi 4 bit duoc phat
outputs : OUT despread_user_vector(3 downto 0);
-- (i)(j) i la so user, j la so
-- bit cua user do
ready : OUT STD_LOGIC;
float_alu_a : OUT float;
float_alu_b : OUT float;
float_alu_c : IN float;
float_alu_mode : INOUT float_alu_mode; -- che do cua alu
float_alu_ready : IN STD_LOGIC; -- alu da san sang hoat dong
awgn_ready: IN STD_LOGIC -- receiver chay sau awgn
Trang 177
);
END COMPONENT receiver;
END PACKAGE receiver_components;

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.float_types.all;
USE work.despread_user_types.all;
USE work.sum_signal_types.all;
USE work.pn_types.all;
USE work.float_constants.all;

ENTITY receiver IS
PORT (
reset, clock: IN STD_LOGIC; -- tong inputs(0) la cac bit0 cua ca 4 user
inputs : IN sum_signal_vector (2 downto 0); -- sum_signal_vector(i)(j) i so bit cua mot
-- user phat di,(vi da tinh tong cac user 4
--thanh 1), j(float) so bit trong mot pn,
outputs : OUT despread_user_vector(3 downto 0);
-- (i)(j) i la user j(float) so bi 1 user phat di
ready : OUT STD_LOGIC;
float_alu_a : OUT float;
float_alu_b : OUT float;
float_alu_c : IN float;
float_alu_mode : INOUT float_alu_mode;
float_alu_ready : IN STD_LOGIC ;
awgn_ready: IN STD_LOGIC -- receiver chay sau awgn
);
END ENTITY receiver;

ARCHITECTURE receiver OF receiver IS
type states is
( init,
despread_spectrum_mul,
despread_spectrum_mul_complete,
despread_spectrum_add,
despread_spectrum_add_complete,
despread_spectrum_complete,
view_bit_user_complete,
view_user_complete,
normally_after_matched_filter_div,
normally_after_matched_filter_div_complete,
normally_after_matched_filter_bit_complete,
normally_after_matched_filter_user_complete,
idle );
signal state : states := init;
-- user data after spreading
Trang 178
signal de_user: despread_user_vector(3 downto 0):= (others => (float_zero, float_zero,
float_zero)); -- tuong ung voi 4 user, moi user co 4 float
--tuong ung voi 4 bit phat di cua user do
signal i,j,k : integer range 0 to 20;
signal float_temp: float := float_zero;
-- pseudo noise code
-- constant pn0: pn := "1101 0111 1000 100";
-- constant pn1: pn := "1011 0110 1101 101";
-- constant pn2: pn := "0011 1101 0110 010";
-- constant pn3: pn := "1001 1110 0111 100";
constant pn :pn_vector(3downto0) :=("100111100111100","001111010110010",
"101101101101101"","110101111000100");
BEGIN
outputs <= de_user; -- luon gan ngo ra
fsm : PROCESS(clock, reset) IS
BEGIN
IF (reset = '1') THEN
ready <= '0';
state <= init;
de_user <= (others => (float_zero, float_zero, float_zero));
ELSIF (clock = '1' AND clock'event) THEN
IF (float_alu_mode /= idle) THEN -- cho cho troi khi alu roi
float_alu_mode <= idle ;
ELSIF (float_alu_ready = '0' or awgn_ready = '0') THEN -- receiver chay sau transmitter
ELSE
CASE state IS
WHEN init =>
ready <= '0'; -- chu hoan thanh cong viec
state <= despread_spectrum_mul;
de_user <= (others => (float_zero, float_zero, float_zero));
i <= 0;
j <= 0;
k <= 0;
--- giai trai pho tinh tuong quan trong 1 pn
WHEN despread_spectrum_mul =>
-- pn(0)* inputs(0) sau do tinh tong vay la da duoc float sau bo loc thich hop
if pn(i)(j) ='1' then -- i la user, j la bit trong ma pn
float_alu_a <= float_2582; -- 1/sqrt(15)
else
float_alu_a <= float_n2582; -- -1/sqrt(15)
end if;
float_alu_b <= inputs(k)(j); -- k nhom pn, j (float) so bit trong pn
float_alu_mode <= mul;
state <= despread_spectrum_mul_complete;
WHEN despread_spectrum_mul_complete =>
float_temp <= float_alu_c;
state <= despread_spectrum_add ;
WHEN despread_spectrum_add => -- tinh tong cua mot mau pn (gom 15 so float)
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float_alu_a <= float_temp; -- ban dau user0 va bit thu 0 cua no, 1
--k = tong cua 15 j
float_alu_b <= de_user(i)(k); -- user thu i va bit thu k cua user do, cong don
--theo chuky trai pho hay do loi
float_alu_mode <= add ;
state <= despread_spectrum_add_complete;
WHEN despread_spectrum_add_complete =>
de_user(i)(k) <= float_alu_c;
state <= despread_spectrum_complete ;
WHEN despread_spectrum_complete =>
if j = 15 - 1 then -- j la so bit trong mot pn
j <= 0;
state <= view_bit_user_complete; -- xem coi da het 4 bit cua mot user chua
else
j <= j+1; -- tang len nhan bit tiep theo trong pn0
state <= despread_spectrum_mul;
end if;
WHEN view_bit_user_complete =>
if k= 3-1 then -- k la so bit cua mot user(hay so nhom pn)
k <= 0;
state <= view_user_complete;
else
k <= k+1;
state <= despread_spectrum_mul;
end if;
WHEN view_user_complete =>
if i= 4-1 then -- neu i = 4 la so user
i <= 0;
state <= normally_after_matched_filter_div ; -- khi thoat i,j,k deu bang 0 het
else
i <= i + 1;
state <= despread_spectrum_mul;
end if;
-- i,j,k da reset
WHEN normally_after_matched_filter_div =>
float_alu_a <= de_user(i)(k); -- ban dau user0 va bit thu 0 cua no,
--1 k = tong cua 15 j
float_alu_b <= float_1p8667; -- user thu i va bit thu k cua user do
float_alu_mode <= div; -- chuan hoa
state <= normally_after_matched_filter_div_complete;
WHEN normally_after_matched_filter_div_complete =>
de_user(i)(k) <= float_alu_c;
state <= normally_after_matched_filter_bit_complete; -- het so bit cua 1 user chua
WHEN normally_after_matched_filter_bit_complete =>
if k= 3-1 then
k <= 0;
state <= normally_after_matched_filter_user_complete;
-- chuyen qua xet het so user chua
Trang 180
else
k <= k + 1;
state <= normally_after_matched_filter_div;
end if;
WHEN normally_after_matched_filter_user_complete =>
if i= 4-1 then -- tang so user quay lai cho toi khi het 4 user
i <= 0;
state <= idle; -- hoan thanh xong ch
else
i <= i + 1;
state <= normally_after_matched_filter_div;
end if;
WHEN idle =>
ready <= '1'; -- da sang sang tuc la da tinh toan xong
state <= idle; -- nhay tai cho
WHEN others =>
state <= init;
END CASE;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE receiver;
Khi SIGN
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.float_types.all;
USE work.float_constants.all;
USE work.float_components.all;
USE work.despread_user_types.all;
USE work.data_types.all;

PACKAGE sign_components IS
COMPONENT sign IS
PORT (
reset, clock: IN STD_LOGIC ;
inputs : IN despread_user_vector(3 downto 0);
-- kenh truyen chung co 3 mau tuong ung voi 3 bit duoc phat
outputs : OUT std_logic_vector (11 downto 0); -- 12 bit cua 4 user theo thu tu
ready : OUT STD_LOGIC ; -- thong bao minh da lam xong viec
receiver_ready : IN STD_LOGIC -- chay sau khoi receiver
);
END COMPONENT sign;
END PACKAGE sign_components;

LIBRARY ieee;
USE ieee.std_logic_1164.all;
Trang 181
USE work.float_types.all;
USE work.float_constants.all;
USE work.float_components.all;
USE work.despread_user_types.all;
USE work.data_types.all;

ENTITY sign IS
PORT (
reset, clock: IN STD_LOGIC ;
inputs : IN despread_user_vector(3 downto 0);
-- inputs(i)(j) i la user j(float) so bit 1 user phat di
outputs : OUT std_logic_vector (11 downto 0);
-- 12 bit cua 4 user theo thu tu 4*3bit phat
ready : OUT STD_LOGIC;
receiver_ready : IN STD_LOGIC -- chay sau khoi receiver
);
END ENTITY sign;

ARCHITECTURE sign OF sign IS
signal fp_cmp_enable, fp_cmp_agb : std_logic := '0';
signal fp_cmp_a, fp_cmp_b : float := float_zero;
signal i,j : integer range 0 to 10;
signal temp_outputs: data_vector(3 downto 0);
type states is
( init,
sign_cmp,
sign_cmp_wait,
sign_cmp_wait_complete,
sign_cmp_bit_complete,
sign_cmp_user_complete,
idle );
signal state : states := init;

BEGIN

fp_cmp0 : fp_cmp port map (reset, fp_cmp_enable, clock, fp_cmp_a, fp_cmp_b,
fp_cmp_agb); -- su dung bo so sanh
fsm : PROCESS(clock, reset) IS
BEGIN
IF (reset = '1') THEN
ready <= '0';
state <= init;
ELSIF (clock = '1' AND clock'event) THEN
IF ( receiver_ready = '0') THEN -- chay sau khoi receiver
ELSE
CASE state IS
WHEN init =>
ready <= '0'; -- chu hoan thanh cong viec
Trang 182
state <= sign_cmp;
i <= 0;
j <= 0;
WHEN sign_cmp =>
fp_cmp_a <= inputs(i)(j); -- de_user(i)(j) j la so bit cua mot user, i la user
fp_cmp_b <= float_zero; -- so sanh voi nguong 0
fp_cmp_enable <= '1'; -- mo lenh so sanh
state <= sign_cmp_wait;
WHEN sign_cmp_wait =>
state <= sign_cmp_wait_complete;
WHEN sign_cmp_wait_complete =>
fp_cmp_enable <= '0'; -- ngung so sanh
if (fp_cmp_agb = '1') then -- neu a > 0 thi ngo ra do la bit -1 theo quy uoc
temp_outputs(i)(j) <= '0'; -- -1 giai ma chuyen sang gia tri std luon
else
temp_outputs(i)(j) <= '1'; -- +1
end if;
state <= sign_cmp_bit_complete;
WHEN sign_cmp_bit_complete => -- het so bit chua
if j= 3-1 then
j <= 0;
state <= sign_cmp_user_complete;
else
j <= j + 1;
state <= sign_cmp;
end if;
WHEN sign_cmp_user_complete => -- het so user chua
if i= 4-1 then
i <= 0;
state <= idle;
outputs <= temp_outputs(3)(2 downto 0)&temp_outputs(2)(2 downto 0)
&temp_outputs(1)(2 downto 0)&temp_outputs(0)(2 downto 0);
-- update lai ngo ra
else
i <= i + 1;
state <= sign_cmp;
end if;
WHEN idle =>
ready <= '1'; -- da sang sang tuc la da tinh toan xong
state <= idle; -- nhay tai cho
WHEN others =>
state <= init;
END CASE;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE sign;
Trang 183

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