ldi Sequential logic: output at any time depends not

out = {fA, muxPC, 2'bxx, destMAR, noLoad, noLoad, noLoad}; only on its current input but also on the past
out = {fAplus1, muxPC, 2'bxx, destPC, noLoad, memRD, noLoad}; sequence of inputs that have been applied to it.
out = {fA, muxMDR, 2'bxx, destReg, loadCC, noLoad, noLoad};
add Combinational logic: the same input values
out = {fAplusB,muxReg,muxReg,destReg,loadCC,noLoad,noLoad}; always produce the same out value independent
out = {fAminB,muxReg,muxReg,destReg,loadCC,noLoad,noLoad}; of the history of input values.
ldr
out = {fB, 2'bxx,muxReg,destMAR,noLoad,noLoad,noLoad}; ISA: an interface/contract between programmer
out = {4'bxxxx, 2'bxx,2'bxx,destNone,noLoad,memRD,noLoad}; and hardware designers. An attribute of a system
out = {fA, muxMDR,2'bxx,destReg,loadCC,noLoad,noLoad}; as seen by the programmer.
bra
out = {fA, muxPC,2'bxx,destMAR,noLoad,noLoad,noLoad}; Prime Implicant: an implicant that cannot be
out = {4'bxxxx, 2'bxx,2'bxx,destNone,noLoad,memRD,noLoad}; covered by a more general implicant.
out = {fA, muxMDR,2'bxx,destPC,noLoad,noLoad,noLoad};
cmi Essential Implicant: are prime implicants that
out = {fA, muxPC, 2'bxx, destMAR, noLoad, noLoad, noLoad}; cover an output of the function that no
out = {fAplus1, muxPC, 2'bxx, destPC, noLoad, memRD, noLoad}; combination of other prime implicants is able to
out = {fAminB, muxReg, muxMDR, destNone, loadCC, noLoad, noLoad}; cover.
cmr
out = {fAminB,muxReg,muxReg,destNone,loadCC,noLoad,noLoad};
lshl
out = {fAshl,muxReg,2'bxx,destReg,loadCC,noLoad,noLoad};
out = {fAlshr,muxReg,2'bxx,destReg,loadCC,noLoad,noLoad};
lda
out = {fA, muxPC, 2'bxx, destMAR, noLoad, noLoad, noLoad};
out = {fAplus1, muxPC, 2'bxx, destPC, noLoad, memRD, noLoad};
out = {fA, muxMDR, 2'bxx, destMAR, noLoad, noLoad, noLoad};
out = {4'bxxxx, 2'bxx, 2'bxx, destNone, noLoad, memRD, noLoad};
out = {fA, muxMDR, 2'bxx, destReg, loadCC, noLoad, noLoad};
sta
out = {fA, muxPC, 2'bxx, destMAR, noLoad, noLoad, noLoad};
out = {fAplus1, muxPC, 2'bxx, destPC, noLoad, memRD, noLoad};
out = {fA, muxMDR, 2'bxx, destMAR, noLoad, noLoad, noLoad};
out = {fB, 2'bxx, muxReg, destMDR, noLoad, noLoad, noLoad};
out = {4'bxxxx, 2'bxx, 2'bxx, destNone, noLoad, noLoad, memWR};
str
out = {fA, muxReg,2'bxx,destMAR,noLoad,noLoad,noLoad};
out = {fB, 2'bxx,muxReg,destMDR,noLoad,noLoad,noLoad};
out = {4'bxxxx, 2'bxx,2'bxx,destNone,noLoad,noLoad,memWR};
jsr
out = {fAmin1, muxSP,2'bxx,destSP,noLoad,noLoad,noLoad};
out = {fA, muxSP,2'bxx,destMAR,noLoad,noLoad,noLoad};
out = {fAplus1, muxPC,2'bxx,destMDR,noLoad,noLoad,noLoad};
out = {fA, muxPC, 2'bxx, destMAR,noLoad,noLoad,memWR};
out = {4'bxxxx, 2'bxx,2'bxx,destNone,noLoad,memRD,noLoad};
out = {fA, muxMDR,2'bxx,destPC,noLoad,noLoad,noLoad};
ldsf
out = {fA, muxPC, 2'bxx, destMAR, noLoad, noLoad, noLoad};
out = {fAplus1, muxPC, 2'bxx, destPC, noLoad, memRD, noLoad};
out = {fAplusB, muxMDR, muxSP, destMAR, noLoad, noLoad, noLoad};
out = {4'bxxxx, 2'bxx,2'bxx,destNone, noLoad, memRD, noLoad};
out = {fA, muxMDR, 2'bxx, destReg, noLoad, noLoad, noLoad};
pop
out = {fA, muxSP, 2'bxx, destMAR, noLoad, noLoad, noLoad};
out = {fAplus1, muxSP, 2'bxx, destSP, noLoad, memRD, noLoad};
out = {fA, muxMDR, 2'bxx, destReg, noLoad, noLoad, noLoad};
push
out = {fAmin1, muxSP, 2'bxx, destMAR, noLoad, noLoad, noLoad};
out = {fA, muxReg, 2'bxx, destMDR, noLoad, noLoad, noLoad};
out = {fAmin1, muxSP, 2'bxx, destSP, noLoad, noLoad, memWR};
rtn
out = {fA, muxSP, 2'bxx, destMAR, noLoad, noLoad, noLoad};
out = {fAplus1, muxSP, 2'bxx, destSP, noLoad, memRD, noLoad};
out = {fA, muxMDR, 2'bxx, destPC, noLoad, noLoad, noLoad};
stsf
out = {fA, muxPC, 2'bxx, destMAR, noLoad, noLoad, noLoad};
out = {fAplus1, muxPC, 2'bxx, destPC, noLoad, memRD, noLoad};
out = {fAplusB, muxMDR, muxSP, destMAR, noLoad, noLoad, noLoad};
out = {fA, muxReg, 2'bxx, destMDR, noLoad, noLoad, noLoad};
out = {4'bxxxx, 2'bxx, 2'bxx, destNone, noLoad, noLoad, memWR};
addsp
out = {fA, muxPC, 2'bxx, destMAR, noLoad, noLoad, noLoad};
out = {fAplus1, muxPC, 2'bxx, destPC, noLoad, memRD, noLoad};
out = {fAplusB, muxMDR, muxSP, destSP, noLoad, noLoad, noLoad};
stsp
out = {fA, muxSP, 2'bxx, destReg, noLoad, noLoad, noLoad};
neg
out = {fAnot, muxReg, 2'bxx, destReg, noLoad, noLoad, noLoad};
out = {fAplus1, muxReg, 2'bxx, destReg, noLoad, noLoad, noLoad};
module fsm1(x, clk, rst, y, state); Mealy Machine: Output on transition
input x, clk, rst;
output reg y; Moore Machine: Output on state

// (increase bitwidth if you need more than eight states) 1947 by Nace
output reg [2:0] state; // This is to become the synchronously

// registered current state.

reg [2:0] nextState; // This is to become the combinationally

// determined next state value

// Define your states and state encodings here
// (increase bitwidth if you need more than eight states)
parameter [2:0] stateA = 3'b000,
stateB = 3'b001,
stateC = 3'b010,
stateD = 3'b011,
stateE = 3'b100;

// Next state logic is defined here. You are basically

// transcribing the .next-state. column of the state transition
// table into a Verilog case statement.
always @* begin
case (state)
stateA: begin
nextState = (x == 1) ? stateB : stateA;
end
stateE: begin
nextState = (x == 1) ? stateB : stateC;
end
default: begin
nextState = stateA;
end
endcase // case(state)
end // always @ *

// Output logic defined here. You are basically transcribing

// the output column of the state transition table into a Verilog
// case statement.
// Remember, if this is a Moore machine, this logic should only.
// depend on the current state. Otherwise, the assignment
// would also involve the input value.
always @* begin
case (state)
stateA: begin
y = 0;
end
stateE: begin
y = 1;
end
default: begin
y = 0;
end
endcase // case(state)
end // always @ *

// Synchronous state update described here.

// This doesn.t do anything interesting except to capture the new
// state value on each clock edge.
always @(posedge clk) begin
if (rst) begin
state <= stateA; // or whatever our reset state is
end else begin
state <= nextState;
end
end
endmodule // fsm1