Finite-State Machine (FSM)

Task: Implement a Mealy finite-state machine in schematic form first (without debounce circuit), then in VHDL (with debounce circuit). Verify each project on FPGA development board. Use one of the Push Buttons to generate a clock signal. Compare synthesis results of both FSM implementations (without debouncer): schematics in RTL Viewer, resource usage, maximum clock frequency, etc. What are the (dis)advantages of each design entry method?

Moore FSM Example Example finite-state machine algorithm is presented in Figure 1. It will be implemented using a Moore machine concept. FSM has three inputs marked as X1, X2, X3 and eight outputs. Output values are shown in hexadecimal format.

Externally, the FSM is defined by its primary inputs, outputs and the clock signal. The clock signal determines when the inputs are sampled and outputs get their new values. Internally, it means, that machine stores a state which is updated at each tick of the clock.

Table 1: Example FSM State Transition Table Current State X1 X2 X3 Next State Output State 0 1 0 0 0 1 0 1 State 1 State 2 State 3 State 0 State 4 State 4 State 2 State 0 X55 X3D X68 XC4 X0F

State 1 State 2 State 3 State 4

Example Moore FSM has five states, corresponding to the number of output vertices of the graph. Lets name them State 0, State 1, State 2, State 3 and State 4. It is now possible to

draw a state transition table (Table 1).

Figure 1: Example Finite-State Machine Algorithm

In order to model the states of the FSM in VHDL an enumerated type of State is created. Signals, which hold the values of the current state and the next state, are of this type. States are encoded automatically during synthesis. Type and signals are declared as follows: type State is (State_0, State_1, State_2, State_3, State_4); signal current_state, next_state: State; A FSM is characterized by two functions the next state function and the output function.

The next state function depends on current state and inputs. The output function is defined by the FSM type. For Moore machine it depends on the current state only. VHDL description of these functions is presented in Listing 1 and Listing 2. Listing 1: Next State Function of Example Moore FSM process (current_state, X1, X2, X3) begin case current_state is when State_0 => if X1 = '1' then next_state <= State_1; elsif X2 = '1' then next_state <= State_3; else next_state <= State_2; end if; when State_1 => next_state <= State_0; when State_2 => next_state <= State_4; when State_3 => next_state <= State_4; when State_4 => if X3 = '1' then next_state <= State_0; else next_state <= State_2; end if; end case; end process;

Listing 2: Output Function of Example Moore FSM process (current_state) begin case current_state is when State_0 => Outputs <= X"55"; when State_1 => Outputs <= X"3D"; when State_2 => Outputs <= X"68"; when State_3 => Outputs <= X"C4"; when State_4 => Outputs <= X"0F"; end case; end process; Next state and output functions form a combinational part of the FSM. Both functions are

same as 01010101 same as 00111101 same as 01101000 same as 11000100 same as 00001111

described using a separate process statements. Sensitivity list of each process features all signals, which serve as inputs to the combinational portion of the design represented by this process. Just like in a real combinational circuit, whenever any of these signals changes a value, the process responds by reevaluating the outputs. Thus, output values for every input combination should be defined. Note, that outputs of the example FSM are represented by an 8-bit vector.

VHDL description of the sequential logic, which stores the state of the example FSM, is presented in Listing 3. Signal current_state infers a register during synthesis, as it is assigned a value inside an edge sensitive if statement. This makes the else path excessive, as the storage element should hold the data unchanged in any other case. The state change occurs on the positive edge of the clock.

Listing 3: Sequential Logic for Storing State of the Example FSM process (clock) begin if clock'event and clock = '1' then current_state <= next_state; end if; end process; The block diagram of the resultant register is presented in Figure 2. Signal current_state can be viewed as register's internal value, which also corresponds to the register's output. Signal next_state provides input data, which is to be stored on the rising edge of the signal clock.

next_state current_state clock

current_state

The block diagram of the entire example Moore FSM is presented in Figure 3. It consists of three main blocks: Next State Function, Output Function and State Register. Each block is described with a corresponding process from Listing 1, Listing 2 and Listing 3 respectively. The cloud blocks represent combinational logic, the rectangle block sequential logic. Blocks (processes) exchange data using wires (signals) next_state and current_state.
current_state

Example Moore FSM

next_state

Next State Function

State Register

CLK Figure 3: Block Diagram of Example Moore FSM

RTL Viewer After synthesis, a RTL schematic of the design may be viewed. Highlight top-level source file in Sources for window. Unfold Synthesize process and double-click View RTL Schematic, select Start with a schematic of the top-level block and click OK. Be aware, that this schematic solution may not completely match the one specified in schematic source file due to optimization. The functionality of both should be equivalent, of course.

In case of HDL source, one can try to draw the parallel between the description and schematic output. However, the synthesized result is, as a rule, tool dependent. One and the same HDL description may be presented differently in various tools.

Push Button Debounce Circuit In order to use a Push Button to generate clock signal pulses it has to be debounced. The problem is that Push Button contains a metal spring and it actually makes contact several times before stabilizing. The high-speed logic circuits may react to the contact bounce as if

the Push Button has been pressed several times, because some pulses may have a sufficient voltage and long enough duration. Thus, for the hardware implementation to work correctly, contact bounce must be filtered.

A 4-bit shift register, which is clocked at 100Hz, can do the trick. With each clock tick it shifts in Push Button's output. When all four bits of the shift register are High, its output goes also High. This will delay the Low to High change until the contact bounce stops.

VHDL description of the 4-bit shift register, which is clocked at 100Hz, is presented in Listing 4 (combinational part) and Listing 5 (sequential part).

Listing 4: Combinational Part of the Shift Register process (Shift_RG) begin if Shift_RG (3 downto 0) = 1111 then Debounced_Push_Button <= '1'; else Debounced_Push_Button <= '0'; end if; end process; Listing 5: Sequential Part of the Shift Register process (clock_100Hz) begin if clock_100Hz'event and clock_100Hz = '1' then Shift_RG (2 downto 0) <= Shift_RG (3 downto 1); Shift_RG (3) <= Push_Button; end if; end process; Nexys-2 FPGA board features a 50MHz crystal oscillator clock source, which output can be divided to 100Hz. VHDL description of the clock divider is presented in Listing 6.

Listing 6: Clock Divider process (clock_50MHz) variable counter: integer range 0 to 249999; begin if clock_50MHz'event and clock_50MHz = '1' then if counter < 249999 then counter := counter + 1; else counter := 0; clock_100Hz <= not clock_100Hz; end if; end if; end process; As the counter is used by clock divider only, it can be implemented as a variable. Variable is local to the process, where it is declared. Unlike signals, variables are assigned value right away. However, for this example it doesn't really matter whether counter is implemented using signal or variable. Note, that the counter is declared as an integer. This way there is no need to know how wide the counter should be, as it will be determined during synthesis automatically, if the counting range is specified as well.