library ieee; use ieee.std_logic_1164.

all; entity FA is port a,b,cin : in std_logic; s, cout : out std_logic); end FA; Architecture chfa of FA is begin S <= axor b xor cin after 7 ns; cout <= (a and b) or (a and cin) or(b and cin) after 5 ns; end chfa; --library ieee; use ieee.std_logic_1164.all; use work.all; entity rca16 is port (a, b : in std_logic_vector(15 downto 0); cin : in std_logic; sum : out std_logic_vector(15 downto 0); cout : out std_logic); end rca16; Architecture archrca16 of rca16 is componet FA is port a,b,cin : in std_logic; s, cout : out std_logic); end component; signal c std_logic_vector( 14 downto 0); begin a0: FA port map (a(0), b(0), cin, sum(0), c(0)); aLast: FA port map (a(15, b(15), c(14), sum(15), cout); ss: for I in 1 to 14 generate am: FA port map (a(i), b(i), c(i-1), sum(i), c(i)); end generate ss; end archrca16; -library ieee; use ieee.std_logic_1164.all; use work.all; entity mux17 is port ( a,b : in std_logic_vector(16 downto 0); s: instd_logic; c: out std_logic_vector(16 downto 0)); end mux17; Architecture archmux of mux17 is begin with s select c <= a when '0', b when others; end archmux; -library ieee; use ieee.std_logic_1164.all; use work.all; entity mux33 is port ( a,b : in std_logic_vector(32 downto 0); s: instd_logic; c: out std_logic_vector(32 downto 0)); end mux33; Architecture archmux of mux33 is begin with s select

c <= a when '0', b when others; end archmux; -library ieee; use ieee.std_logic_1164.all; use work.all; entity csa32 is port (a,b :in std_logic_vector(31 downto 0); cin : in std_logic; s: out std_logic_vector(32 downto 0)); end csa32; architecture archcsa32 of csa32is component mux17 is port ( a,b : in std_logic_vector(16 downto 0); s: instd_logic; c: out std_logic_vector(16 downto 0)); end component; component rca16 is port (a, b : in std_logic_vector(15 downto 0); cin : in std_logic; sum : out std_logic_vector(15 downto 0); cout : out std_logic); end component; signal M1, M2 std_logic_vector(15 downto 0); signal lc std_logic; begin A1: rca16 port map(a(15 downto 0), b(15 downto 0), '0', s(15 downto 0), lc); A2: rca16 port map(a(31 downto 16), b(31 downto 16), '0', M1(31 downto 16), M1(32); A3: rca16 port map(a(31 downto 16), b(31 downto 16), '1', M2(31 downto 16), M2(32)); A4: mux17 port map( M1, M2, lc, S(32 downto 16); end archcsa32; -library ieee; use ieee.std_logic_1164.all; use work.all; entity csa64 is port (a,b :in std_logic_vector(63 downto 0); cin : in std_logic; s: out std_logic_vector(64 downto 0)); end csa64; architecture archcsa32 of csa32is component mux33 is port ( a,b : in std_logic_vector(16 downto 0); s: instd_logic; c: out std_logic_vector(16 downto 0)); end component; component csa32 is port (a,b :in std_logic_vector(31 downto 0); cin : in std_logic; s: out std_logic_vector(32 downto 0)); end component; signal M1, M2 std_logic_vector(64 downto 0); signal lc std_logic; begin A1: csa32 port map(a(31 downto 0), b(31 downto 0), '0', s(31 downto 0), lc); A2: csa32 port map(a(63 downto 32), b(63 downto 32), '0', M1(64 downto 0)); A3: csa32 port map(a(63 downto 32), b(63 downto 32), '1', M2(64 downto 0)); A4: mux33 port map( M1, M2, lc, S(64 downto 32); end archcsa32;