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Tut 6 Digital VHDL

This document contains 5 questions related to VHDL code examples. Question 1 defines a multiplexer entity and architecture using a case statement to select the output based on the select signal. Question 2 defines a full adder subsystem using a component for a full adder. Question 3 defines a priority encoder that encodes the most significant low bit of the input. Question 4 defines an entity that implements logic functions on 6 inputs to generate an 8-bit output. Question 5 defines a comparator that outputs signals to indicate if the first input is less than, equal to, or greater than the second input.

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Shobhit Garg
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49 views16 pages

Tut 6 Digital VHDL

This document contains 5 questions related to VHDL code examples. Question 1 defines a multiplexer entity and architecture using a case statement to select the output based on the select signal. Question 2 defines a full adder subsystem using a component for a full adder. Question 3 defines a priority encoder that encodes the most significant low bit of the input. Question 4 defines an entity that implements logic functions on 6 inputs to generate an 8-bit output. Question 5 defines a comparator that outputs signals to indicate if the first input is less than, equal to, or greater than the second input.

Uploaded by

Shobhit Garg
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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Tutorial 6 - VHDL

Q.1

library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity multi_plexer is port ( a, b, c, d, e, f, g, h : in std_logic; Sel : in std_logic_vector(2 downto 0); Output : out std_logic ); end entity multi_plexer; architecture Behavioral of multi_plexer is begin process (a, b, c, d, e, f, g, h, Sel) is begin case Sel is when "000" => Output <= a; when "001" => Output <= b; when "010" => Output <= c; when "011" => Output <= d; when "100" => Output <= e; when "101" => Output <= f; when "110" => Output <= g; when others => Output <= h; end case; end process;

end architecture Behavioral;

Test Bench Waveform

Lo

Logic Diagram

Test Bench Waveform

Q.2 library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.STD_LOGIC_ARITH.ALL;

entity fulladder_subt is port ( A, B :in std_logic_vector(3 downto 0); --inputs for each level M :in std_logic; --input carry is M SUM : out std_logic_vector(3 downto 0); --output sum for each level cout, V :out std_logic); --output carry end fulladder_subt; architecture struct_fulladder_subt of fulladder_subt is signal C: std_logic_vector (3 downto 0); component FULL_ADDER port ( A,B,C,M : in std_logic; S, carry : out std_logic); end component; begin FA0: FULL_ADDER Port map (A(0), B(0), M, M, SUM(0), C(0)); FA1: FULL_ADDER Port map (A(1), B(1), C(0), M, SUM(1), C(1)); FA2: FULL_ADDER Port map (A(2), B(2), C(1), M, SUM(2), C(2)); FA3: FULL_ADDER Port map (A(3), B(3), C(2), M, SUM(3), C(3)); Cout <= C(3); V <= C(3) xnor C(2); end struct_fulladder_subt;

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.STD_LOGIC_ARITH.ALL; entity FULL_ADDER is port ( A,B,C,M : in std_logic; S,Carry : out std_logic); end FULL_ADDER; architecture Behavioral of FULL_ADDER is begin S<= (A xor (B xor M) ) xor C; Carry<= (A and (B xor M) ) or ( C and (A xor (B xor M) ) ); end Behavioral;

Test Bench Waveform

Logic Diagram

Test Bench Waveform

The Full Adder Component

Full Adder Component

Logic Diagram

Q.3 library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.STD_LOGIC_ARITH.ALL;

entity Priority_encod is port ( sel : in std_logic_vector (7 downto 0); EI : in std_logic; Output : out std_logic_vector(2 downto 0); GS, EO : out std_logic); end entity Priority_encod; architecture Behavioral of Priority_encod is begin process (sel, EI)

begin EO <= '1'; if(EI = '0') then GS <= '0'; if sel(7)='0' then output <= "000"; elsif sel(6) = '0' then output <= "001"; elsif sel(5) = '0' then output <= "010"; elsif sel(4) = '0' then output <= "011"; elsif sel(3) = '0' then output <= "100"; elsif sel(2) = '0' then output <= "101"; elsif sel(1) = '0' then output <= "110"; elsif sel(0) = '0' then output <= "111"; else output <= "111"; GS <= '1'; EO <= '0'; end if; else GS <= '1'; output <= "111"; end if; end process; end architecture Behavioral;

Logic Diagram

Test Bench Waveform

Q.4
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.STD_LOGIC_ARITH.ALL;

entity Answer_4 is port (a,b,c,d,e,f:in std_logic; O: out std_logic_vector(7 DOWNTO 0)); end Answer_4; architecture Behavioral of Answer_4 is begin O(0)<=a or b or c or d; O(1)<=a or b or (not c) or d; O(2)<=a or b or c or (not d); O(3)<=a or b or (not c) or (not d); O(4)<=(not c) and (not d) and (not(e and f)); O(5)<=(c) and (not d) and (not(e and f)); O(6)<=(not c) and (d) and (not(e and f)); O(7)<=(c) and (d) and (not(e and f));

end Behavioral;

Test Bench Waveform

Q.5
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.STD_LOGIC_ARITH.ALL; entity compare_inp is port (A : in std_logic_vector(3 downto 0); B : in std_logic_vector(3 downto 0); less :out std_logic; equal : out std_logic; greater :out std_logic); end compare_inp; architecture Behavioral of compare_inp is begin process (A, B) begin if (A < B ) then less <= '1'; equal <= '0'; greater <= '0'; elsif (A < B) then less <= '0'; equal <= '0'; greater <= '1'; else less <= '0'; equal <= '1'; greater <= '0'; end if; end process; end Behavioral;

Logic Diagram

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