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Proj Rybczynski FIR Filter

This document discusses optimizations that can be made to a 3-tap FIR filter design. It describes the original 6-state FIR control, and proposes an optimized 3-state control that performs all multiplications simultaneously before adding the results. It also replaces the multiplier blocks with optimized array multipliers to further improve the design's area and timing. Tables compare the area and timing of the original, optimized control, and optimized control with array multipliers.

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Ved Pragyan
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as PPT, PDF, TXT or read online on Scribd
18 views

Proj Rybczynski FIR Filter

This document discusses optimizations that can be made to a 3-tap FIR filter design. It describes the original 6-state FIR control, and proposes an optimized 3-state control that performs all multiplications simultaneously before adding the results. It also replaces the multiplier blocks with optimized array multipliers to further improve the design's area and timing. Tables compare the area and timing of the original, optimized control, and optimized control with array multipliers.

Uploaded by

Ved Pragyan
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as PPT, PDF, TXT or read online on Scribd
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3-Tap FIR Filter Optimizations

By: Jeff Rybczynski CMPE 222

3-Tap FIR Filter Design

Monday, June 02, 2003

FIR Optimization Jeff Rybczynski

FIR Filter Control

Six States meaning 3 bit State Variable Each Multiply is in a separate state Asynchronous Reset

Monday, June 02, 2003

FIR Optimization Jeff Rybczynski

FIR Filter Data Path

3 Independent Multiply Operations 3 Independent Addition Operations Not order dependent

Monday, June 02, 2003

FIR Optimization Jeff Rybczynski

Optimized FIR Control

Take out extra calculate steps and place all the multiplies in one CALC state Add the values from the multiply step together in ADD state Place value directly into result before you raise output_ready
FIR Optimization Jeff Rybczynski 5

Monday, June 02, 2003

Changes to the Verilog Code


Original Verilog Code
3'b100 3'b110 3'b111 3'b101 3'b001 begin output_ready <= 1'b0; rin <= sample; end acc <= rin * 24'h702a78; acc <= rs0 * 24'h800000 + acc; acc <= rs1 * 24'h4fd547 + acc; begin output_ready <= 1'b1; result <= acc; rs1 <= rs0; rs0 <= rin; end default : begin acc <= 24'h000000; output_ready <= 1'b0; end : : : : :

Monday, June 02, 2003

FIR Optimization Jeff Rybczynski

Changes to the Verilog Code


Optimized Code
2'b00 : begin output_ready <= 1'b0; rin <= sample; end 2'b10 : begin temp1 <= rin * 24'h702a78; temp2 <= rs0 * 24'h800000; temp3 <= rs1 * 24'h4fd547; end 2'b11 : begin result <= temp1 + temp2 + temp3; rs1 <= rs0; rs0 <=rin; output_ready <=1b1 end 2'b01 : output_ready <= 1'b0;
Monday, June 02, 2003 FIR Optimization Jeff Rybczynski 7

Array Multiplier

Similar to how you multiply by hand Cascading Array multiplier blocks

Monday, June 02, 2003

FIR Optimization Jeff Rybczynski

Array Multiplier Block

Monday, June 02, 2003

FIR Optimization Jeff Rybczynski

Array Multiplier
A3=1 0 B0=1 1
A B CO CI S

A2=0 0 0 0
A B CO CI S

A1=1 0 0 1
A B CO CI S

A0=1 0 0 1
A B CO CI S

0 0

B1=0

0
A B CO CI S

0
A B CO CI S

0
A B CO CI S

0
A B CO CI S

0 0 B2=1 1
A B CO CI S

0
A B CO CI S

1
A B CO CI S

1
A B CO CI S

0 0 B3=1 1
A B CO CI S

0
A B CO CI S

1
A B CO CI S

1
A B CO CI S

0 0
A B CO CI S

A B CO CI S

A B CO CI S

A B CO CI S

0 1 1 1 1

Monday, June 02, 2003

FIR Optimization Jeff Rybczynski

10

Add Array Multiplier to Verilog Code

Old Code:
temp1 <= rin * 24'h702a78; temp2 <= rs0 * 24'h800000; temp3 <= rs1 * 24'h4fd547;

New Code:
array_multi a(temp1,rin, 24'h702a78); array_multi b(temp2,rs0, 24'h800000); array_multi c(temp3,rs1, 24'h4fd547);

Monday, June 02, 2003

FIR Optimization Jeff Rybczynski

11

FIR Designs
Area Time

Original FIR Design


Optimized FIR 3 Latency Optimized FIR Array Multiplier
Monday, June 02, 2003

77182.453125
76806.578125 91060.187500
FIR Optimization Jeff Rybczynski

9.77 ns
9.61 ns 9.73 ns
12

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