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Design and Implementation of USART Using VHDL

This document describes the design and implementation of a Universal Asynchronous Receiver/Transmitter (USART) using VHDL. A USART is used to send and receive small packets of serial data asynchronously or synchronously. It transmits 5-9 bits of data along with start, stop, and optional parity bits. The VHDL implementation includes schematics for the transmitter and receiver along with modules for a data register, control register, and baud rate generator. Simulation results showed the transmitter and receiver operating reliably for serial communication.

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485 views18 pages

Design and Implementation of USART Using VHDL

This document describes the design and implementation of a Universal Asynchronous Receiver/Transmitter (USART) using VHDL. A USART is used to send and receive small packets of serial data asynchronously or synchronously. It transmits 5-9 bits of data along with start, stop, and optional parity bits. The VHDL implementation includes schematics for the transmitter and receiver along with modules for a data register, control register, and baud rate generator. Simulation results showed the transmitter and receiver operating reliably for serial communication.

Uploaded by

wineyarddee
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PPT, PDF, TXT or read online on Scribd
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DESIGN AND IMPLEMENTATION OF USART USING VHDL

USART FUNCTION
Universal Synchronous Asynchronous Receiver Transmitter

used to send and receive small packets over a serial line


full or half duplex
typically asynchronously 5 9 bits of data 2 or 3 framing bits start bit 1 or 2 stop bits 0 or 1 parity bits

MAIN FUNCTIONS
Universal Synchronous Asynchronous Receiver Transmitter: can be synchronous or asynchronous can receive and transmit Full duplex asynchronous operation Most common use: RS-232 communications to a PC serial port

DATA FORMAT
Must be agreed on by sender and receiver before any exchanges can be made stop bit (1 to 0 transition)

5 9 data bits
0 or 1 parity bits (odd or even parity) 1 or 2 stop bits (logic 0)

SCHEMATIC OF TRANMITTER

SENDING DATA
Remember synchronization is on a character by character basis check status

load data register


start transmit wait for transmission complete status or for interrupt repeat

RECEIVING DATA
poll status register for data ready or wait for interrupt read data (save it)

repeat

SCHEMATIC OF RECEIVER

PROGRAMMING MODEL
Data input register Data output register

Control register
speed, data bits, parity, stop bits, start, stop

BAUD RATE GENERATOR

BAUD RATE GENERATOR


This module is designed to generate a square clock irrespective of the divisor value . In synchronous mode of communication ,this clock is transmitted along with the data.

SIMULATION RESULTS TRANSMITTER

RECEIVER
Receiver

CONCLUSION
This design uses VHDL as design language to achieve the modules of UART. The results are stable and relaible. The design has great flexibility,high integration with some reference value.

FUTURE SCOPE
We can implement this project for the designing of USARTS for system on chip devices.

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