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Modelsim Commands

The document describes the basic steps to compile and simulate a design using the command line in VHDL. It involves creating a physical library directory with vlib, mapping it with vmap, compiling the design with vcom, invoking the simulator with vsim, adding signals to the waveform view, running and restarting the simulation, and quitting the simulator.

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Sreekanth Pusapati
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30 views

Modelsim Commands

The document describes the basic steps to compile and simulate a design using the command line in VHDL. It involves creating a physical library directory with vlib, mapping it with vmap, compiling the design with vcom, invoking the simulator with vsim, adding signals to the waveform view, running and restarting the simulation, and quitting the simulator.

Uploaded by

Sreekanth Pusapati
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Command line operation

Creating a compilation library Create a physical compilation directory with vlib:


vlib ./work vmap work ./work

Create a logical name for the physical directory with vmap:

Compiling your design


vcom mux.vhd

Invoking the simulator


vsim work.T_MUX

Simulator User Unterface


view * view wave

Add signals in the waveform window add wave /t_mux/uut/* Running the simulation run 100 ns Restart the simulation restart f Quitting the simulator quit -sim

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