Compression and Decompression
Compression and Decompression
By: Bhunavya.T N.Kalyan Chakravarthy D.Sirish R.Govind Raju under the guidence of: Mr.M.RAMA KRISHNA M.Tech
Contents
Introduction Scope of the project Basic communication system Why do we use digital instead of analog Compression Compression techniques Decompression
Contents(cntd..)
Block diagram Compressor block XMatch pro algorithm Content addressable memory Decompressor block Feature scope conclusion
Introduction
With the current reliance on telecommunications, a way to shrink data and save on bandwidth is essential.
DATA compression is nearly an ubiquitous occurrence in modern computing. Data compression is one of the enabling technologies of each of the multimedia revolution.
By using the architecture of compressors, the data compression rates are significantly improved. Also inherent possible. scalability of architecture is
Compression
The compression is the process that is required either to reduce the volume of information to be transmitted text, fax and images or reduce the bandwidth that is required for its transmission speech, audio and video. The compression technique is first applied to the source information prior to its transmission.
Compression techniques
Compression algorithms can be classified in to two types, namely
Lossless Compression
Lossy Compression
Lossless compression
Lossless compression allows for the total recall of the original data set after compression. The aim is to reduce the amount of source information to be transmitted in such a way that, when the compressed information is decompressed, there is no loss of information.
Lossy compression
Lossy compression occurs when the original data set cannot be fully constructed from the compressed data set.
The aim of the Lossy compression algorithms is normally not to reproduce an exact copy of the source information after decompression but rather a version of it that is perceived by the recipient as a true copy.
Decompression
Decompression is the reverse process of compression. Reconversion of compressed data into its original (nearly original) form so that it can be heard, read, and/or seen as normal.
Block diagram
Compressor block
32BIT COMPRESSION SYSTEM
COMPRESSOR
CLK
ADD OUT
RST
CAM
COMPARATOR add out
DATA
(32 BITS)
COMPARATOR
ARRAY
MATCH HIT
START
DATA OUT (32 BIT)
Compressor block(contd..)
The block diagram gives the details about the components of a single 32 bit Compressor. There are three components namely,
COMPARATOR ARRAY CAMCOMPARATOR
Compressor block(contd..)
The COMPARATOR is used to compare two 32-bit data and to set or reset the output bit as 1 for equal and 0 for unequal. ARRAY is of length of 64X32 bit locations. This is used to store the unmatched incoming data and when a new data comes, the incoming data is compared with all the data stored in this array. The CAM COMPARATOR searches the CAM dictionary entries for a full match of the input data given.
XMatchPro algorithm
The XMatchPro algorithm uses a fixed-width dictionary of previously seen data and attempts to match the current data element with a match in the dictionary. It works by taking a 4-byte word and trying to match or partially match this word with past data. This past data is stored in a dictionary, which is constructed from a content addressable Memory.
XMatchPro algorithm(contd..)
The coding function for a match is required to code several fields as follows: A zero followed by: 1). Match location: It uses the binary code associated to the matching location. 2). Match type: Indicates which bytes of the incoming tuple have matched. 3). Characters that did not match transmitted in literal form.
Features
High-speed lossless data compressor supports compression and decompression in a single FPGA. Throughput up to 200 Mbytes/second compression or decompression with low latency clocking at 50 MHz on a APEX FPGA. Full-duplex operation enables simultaneous compression or decompression for a combined performance of 400 Mbytes/s.
Features (cntd...)
Full-duplex architecture enables self-checking test mode using CRC (Cyclic Redundancy Check) codes. 32-bit high-performance coprocessor-style interface. Fully contained 32-bit architecture does not require any external components and supports operation on blocked data.
Decompressor block
The decompressor has the following components
Array Processing Unit.
Decompressor block(contd..)
Array has the same function as that of the array unit which is used in the Compressor. It is also of the same length. Processing unit checks the incoming match hit data. if it is 0, it indicates that the data is not present in the Array, so it stores the data in the Array. if the match hit data is 1, it indicates the data is present in the Array, then it instructs to find the data from the Array with the help of the address input and sends as output to the data out.
Conclusion
The Improved Compression ratio is Compression architecture with least latency. The High speed throughput The architecture provides inherent future. achieved in increase in is achieved. scalability in
The total time required to transmit compressed data is less than that of transmitting uncompressed data. This can lead to a performance benefit, as the bandwidth of a link appears greater when transmitting compressed data and hence more data can be transmitted in a given amount of time .
Future scope
There is a potential of doubling the performance of storage / communication system by increasing the available txion bandwidth and data capacity with minimum investment. It can be applied in Computer systems, High performance storage devices.
Results compression
RTL Schematic
decompression