EE4292 Integrated Circuit Design Lab

Logic Synthesis
Hsi-Pin Ma ()
http://larc.ee.nthu.edu.tw/~hp/EE4292/ Department of Electrical Engineering National Tsing Hua University

Cell-based Design Flow

Architecture Design HDL RTL Coding Testbenches Functional Simulation Logic Synthesis Cell Library Pre-layout Simulation Automatic Placement & Routing Post-layout Verification & Simulation System-level Integration tapeout
2

Memory Module

sdf

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HDL Coding References

Michael Keating and Pierre Bricaud, Reuse Methodology Manual, Kluwer Academic Publishers, Third Ed., 2002 Guide to HDL Coding Styles for Synthesis, SOLD. Preparing Design Files for Synthesis (Chapter 3 in Design Compiler User Guide), SOLD.

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Verilog Simulation References

Verilog-XL
Verilog-XL User Guide Verilog-XL Reference

NC-Verilog
Cadence NC-Verilog Simulator Help

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Logic Synthesis

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References
Design Compiler User Guide, SOLD. Synthesis, CIC Training documents.

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Synthesis
Translate

HDL Sources

Optimize + Map

Generic Boolean (GTECH) Synthesis = Translation + Optimization + Mapping Target Technology

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Basic Synthesis Flow

Develop HDL Files Specify Libraries
set_operating_conditions set_wire_load_model set_drive set_driving_cell set_load set_fanout_load set_min_library

Library Objects
link_library target_library symbol_library synthetic_library

Read Design Define Design Environment Set Design Constraints

analyze elaborate read_file

Design Rule Constraints

Top down Bottom up

Select Compile Strategy Optimize the Design

set_max_transition set_max_fanout set_max_capacitance

Design Optimization Constraints

create_clock set_clock_latency set_propagated_clock set_clock_uncertainty set_clock_transition set_input_delay set_output_delay set_max_area

compile

check_design report_area report_constraint report_timing

Analyze and Resolve Design Problems Save the Design Database

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write

Running Design Compiler

setup file
$HOME/.synopsys_dc_setup

Start using design compiler

% dc_shell dc_shell> write -hierarchy -output my_design.db dc_shell> quit %
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% dc_shell -f synthesis.scr %

A Simple Synthesis Script

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Design Objects
Design : A circuit that performs one or more logic functions Cell : An instance of a design or library primitive within a design Reference : The name of the original design that a cell instance points to Port : The input or output of a design Pin : The input or output of a cell Net : The wire that connects ports to pins and/or pins to each other Clock : A timing reference object in DC memory which describes a waveform for timing analysis

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Design Objects
Design module TOP (A, B, C, D, CLK, OUT1); input A, B, C, D, CLK; output [1:0] OUT1; Port wire INV1, INV0, bus1, bus0; ENCODER U1(.AIN(A), ..., .Q1(bus1)); Reference Cell INV U2(.A(BUS0), .Z(INV0)), U3(.A(BUS1), .Z(INV1)); Net

Clock

Pin

REGFILE U4(.D0(INV0), .D1(INV1), .CLK(CLK)); endmodule

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find
Search current design for names of the given object type Syntax
find type [name_list] [-hierarchy] type : design, port, reference, cell, clock, pin or net name_list
List of design of library object names, use brackets ({lists}) for multiple names If no name_list is given, find lists all the names of specified object type
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find
List all ports of the current design
find (port, *);

List all the instances that start with B or D

find (cell, {B* D*})

Find the nets n2003, n2004

find (net, {n2003,n2004})

Place a dont_touch attribute on all the designs in the hierarchy

set_dont_touch find (design, * -hier)

List all the pins of the FD1 cell of the class library
find (pin, class/FD1/*)
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Design Constraints

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Setting Design Constraints

Constraints
Goals that DC uses for optimizing a design into the target library

Design rule constraints

technology-specific restrictions, eg., maximum transition, maximum fanout, maximum capacitance

Optimization constraints
design goals and requirements, eg., maximum delay, minimum delay, maximum area, maximum power
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Design Rule Constraints

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Design Rule Constraints

Cannot be violated at any cost! Use the following rule to set a more conservative constraints than the library description
set_max_transition set_max_fanout set_max_capacitance

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set_max_transition
Set a maximum transition time on ports or design (Smaller than the librarys definition)
set_max_transition 5 all_inputs() set_max_transition 3 all_outputs()

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Optimization Constraints

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Timing Paths in Design Compiler

Design time breaks designs into sets of signal paths.
Each path has a startpoint and an endpoint Startpoints : input ports, clock pins of sequential devices Endpoints : output ports, data input pins of sequential devices

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Maximum Delay Constraints

For combinational logics primarily
Select the start and end points of the timing path (unit : ns)
dc_shell> set_max_delay 5.0 -from start_clock -to comb_end

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Sequential Logics
create_clock
Define clock
dc_shell> create_clock CLK -period 20 -waveform {0 8}

set_fix_hold
Correct hold time violations
dc_shell> set_fix_hold CLK

set_dont_touch_network
Preserve clock network
dc_shell> set_dont_touch_network CLK
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Input Delay
Clock-cycle >= DFFclk-Qdelay + a + b + DFFsetup Input delay = DFFclk-Qdelay + a

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Input Delay

dc_shell> set_input_delay -clock clk -max 6.4 in1 dc_shell> set_input_delay -clock clk -min 4.4 in1

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Output Delay
Clock-cycle >= DFFclk-Qdelay + d + e + DFFsetup Output delay = e + DFFsetup

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Output Delay

dc_shell> set_output_delay -clock clk -max 5.3 in1

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Setting Area Constraints

set_max_area
Set the maximum area of the design, the area is technology dependent (equivalent gate counts/um x um/ Transistors)
/*example script for smallest design */ remove_constraint -all remove_clock -all set_max_area 0

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Compile Strategy

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Drive Characteristics

dc_shell> current_design top_level_design dc_shell> set_drive 1.5 {I1 I2} dc_shell> current_design sub_design2 dc_shell> set_driving_cell -cell IV {I3}

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Design Strategy Example

/* Constraints File for Design TOP (defaults.con) */ set_operating_conditions WCCOM set_wire_load_model 20x20 create_clock -period 25 clk set_input_delay 3 -clock clk all_inputs() -find(port, clk) set_output_delay 2 -clock clk all_outputs() set_load 1.5 all_outputs() set_driving_cell -cell IV all_inputs() set_drive 0 clk
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Top-Down Compile
/* read in the entire design */ read_file -format verilog E.v read_file -format verilog D.v read_file -format verilog C.v read_file -format verilog B.v read_file -format verilog A.v read_file -format verilog TOP.v current_design TOP link /* apply constraints and attributes */ include defaults.con /* compile the design */ compile

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Bottom-Up Compile
all_blocks = {E,D,C,B,A} /* compile each subblock independently */ foreach (block, all_blocks) { /* read in block */ block_source = block + .v read_file -format verilog block_source current_design block link /* apply global constraints and attributes */ include defaults.con /* apply constraints and attributes */ block_script = block + .con include block_script /* compile the block */ compile } /* read in the entire compiled design */ read_file -format verilog TOP.v current_design TOP link write -hierarchy -output first_pass.db /* apply top-level constraints */ include defaults.con include top_level.con /* check for violations */ report_constraint /* characterize all instances in the design */ all_instances = {U1,U2,U2/U3,U2/U4,U2/U5} characterize -constraint all_instances /* save characterize information */ foreach (block, all_blocks) { current_design block char_block_script = block + .wscr write_script > char_block_script }
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Bottom-Up Compile
/* recompile each block */ foreach (block, all_blocks) { /* clear memory */ remove_design -all /* read in previously characterized subblock */ block_source = block + .v read_file -format verilog block_source /* recompile subblock */ current_design block link /* apply global constraints and attributes */ include defaults.con /* apply characterization constraints */ char_block_script = block + .wscr include char_block_script /* apply block constraints and attributes */ block_script = block + .con include block_script /* recompile the block */ compile
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Multiple Design Instances of a Design Reference

Use set_dont_touch, ungroup, uniquify to fix it

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Multiple Design Instances of a Design Reference

uniquify
Create a unique design file for each instance (DC will run this automatically)

dc_shell> current_design top dc_shell> compile

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Multiple Design Instances of a Design Reference

set_dont_touch
Inhibit re-compile of a lower level design

dc_shell> current_design top dc_shell> characterize U2/U3 dc_shell> current_design C dc_shell> compile dc_shell> current_design top dc_shell> set_dont_touch {U2/U3 U2/U4} dc_shell> compile

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Multiple Design Instances of a Design Reference

ungroup
Does not preserve the hierarchy

dc_shell> current_design B dc_shell> ungroup {U3 U4} dc_shell> current_design top dc_shell> compile

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Pre-layout Verilog Timing Simulation

In dc synthesis script, add the following after compile
write_timing -format sdf -output design.sdf

In Verilog testbench, add the following

$sdf_annotate(design.sdf, TOP_MODULE_NAME); Remember also to add `timescale

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