Scribd
Upload
32 views4 pages

Lab Report: COURSE: Digital Design Lab Section: B

This lab report describes digital logic circuits implemented in code. It includes codes for a half-adder, full-adder, and 4-bit full-adder. For the half-adder, it uses an XOR gate for the sum and AND gate for the carry. The full-adder code uses two half-adders and an OR gate. Finally, the 4-bit full-adder code chains together four full-adder modules to add 4-bit inputs and output the final sum and carry.

Uploaded by

Javaria Ahmad
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
32 views4 pages

Lab Report: COURSE: Digital Design Lab Section: B

This lab report describes digital logic circuits implemented in code. It includes codes for a half-adder, full-adder, and 4-bit full-adder. For the half-adder, it uses an XOR gate for the sum and AND gate for the carry. The full-adder code uses two half-adders and an OR gate. Finally, the 4-bit full-adder code chains together four full-adder modules to add 4-bit inputs and output the final sum and carry.

Uploaded by

Javaria Ahmad
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
You are on page 1/ 4

LAB REPORT

COURSE: Digital Design Lab SECTION: B


DATED: 10-02-12

SUBMITTED BY:
JAVARIA AHMAD IRAM BASHIR MARIA NAZIR BSEE01103084 BSEE01103066 BSEE01103063

Q1: Write a code for half-adder. Sol: module half(s,c,a,b); Input a,b; Ouputs,c; Xor x(s,a,b); And a1(c,a,b); Endmodule;

Q: write a code for full-adder. Sol: modulefulladder(s,c,a,b,d); Input a,b,d; Output s,c Wire w1,w2,w3; Half h1(w1,w2,a,b); Half h2(s,w3,w1,d); Or o1(c,w3,w2); Endmodule

Q3. Write a code for 4 bit full-adder. Sol: modulefourbitfulladder(s1,s2,s3,s4,c,a1,a2,a3,a4,b1,b2,b3,b4,cin) Input a1,a2,a3,a4,b1,b2,b3,b4; Output s1,s2,s3,s4,c; Wire w1,w2,w3; fulladder f1(w1,s1,a1,b1,cin); fulladder f1(w2,s2,a2,b2,w1); fulladder f1(w3,a3,b3,s3,w2); fulladder f1(c,s4,w3,a4,b4); endmodule;

You might also like