Synthetizable VHDL

Jan Koenek r
[email protected]

Outline
Introduction to synthesis Synthesis levels VHDL templates and implementation Synthesis issues Conclusion

VHDL
VHDL - Very high speed integrated circuit Hardware Description Language. Designed for simulation discrete time simulation based on processes Now is also used for synthesis

Design ow

Synthesis
Synthesis is a general term that describes the process of transformation of the model of a design, usually described in a hardware description language (HDL), from one level of behavioral abstraction to a lower, more detailed behavioral level. These transformations try to improve upon a set of objective metrics (e.g., area, speed, power dissipation) of a design, while satisfying a set of constraints (e.g., I/O rates, MIPS, sample period) imposed on it.

Levels of Synthesis
Behavioral Synthesis - synthesis of abstract behavior or control-ow behavior from a high level algorithm description RTL Synthesis - synthesis of register-transfer structure from abstract, control-ow, or register-transfer behavior Logic Synthesis - synthesis of gate-level logic (an implementation) from register-transfer structure or Boolean equations

Levels of Synthesis

Behavioral level

RTL level

Logic level

Behavioral level
The input to a behavioral synthesis system describes the dataow, input/output constraints, memory accesses, and user dened constraints (sample period, latency). The output of the behavioral synthesis system provides the datapath, registers, memories, I/O structures, and a state machine-based controller that satises the same test bench as the input.

Behavioral level specication

Behavioral level example

RTL level synthesis

Input to the RTL synthesis environment includes the number of data path components (adders, multipliers,), the mapping of operations to data path components, and a controller (nite state machine) that contains the detailed schedule (related to clock edge) of computational, I/O, and memory operations. Output of the RTL synthesis provides logic level implementations that can be evaluated through the optimization of the data path, memory, and controller components, individually or in a unied manner, through mapping to gate-level component libraries.

RTL level specication

RTL level example

Development diagram

Practical templates
combinational circuits and logic multiplexer and demultiplexer counter, comparators, etc. register and sequential circuits synchronious and asynchronious registers shift registers State machines and controllers

Decoder or Multiplexer
using case statement.
process (sel, a, b, c, d) begin case sel is when "00" => mux_out when "01" => mux_out when "10" => mux_out when "11" => mux_out when others => null; end case; end process;

<= <= <= <=

a; b; c; d;

when statement
mx_out <= a when "00" else b when "01" else c when "10" else d;

Counter
up and down counter.
process (clk, reset) begin if reset=1 then count <= "0000"; elsif clk=1 and clkevent then if ce=1 then if load=1 then count <= din; else if dir=1 then count <= count + 1; else count <= count 1; end if; end if; end if; end if; end process;

Register
with asynchronious reset
process (clk, reset) begin if reset=1 then asynchronous reset dout <= 0; elsif (clkevent and clk=1) then dout <= din; end if; end process;

with synchronious reset

process (clk) begin if clkevent and clk=1 then if reset=1 then dout <= 0; else dout <= din; end if; end if; end process;

Shift register
VirtexII component instantion
component SRLC16E generic ( INIT : bit_vector := X"0000" ); port ( D : in std_logic; CE : in std_logic; CLK : in std_logic; A0 : in std_logic; A1 : in std_logic; A2 : in std_logic; A3 : in std_logic; Q : out std_logic; Q15 : out std_logic ); end component;

Finite state machine

A state machine has three basic parts Next State Logic Output Logic Memory
Mealy machine model
output combinatonal logic next state combinational logic

Moore machine model

output combinatonal logic next state combinational logic

memory

memory

Finite state machine (cont.)

Use enumerated type to encode state variables
signal present_state, next_state : state_type; type state_type is (idle,init,test,add,shift);

User can choose state encoding type in synthesis tool Sequential One Hot Gray Others enum_encoding attribute can be used to specify encoding directly

Finite state machine (example)

process (clk, reset) begin if reset=1 then cur_state <= fst_state; elsif (clkevent and clk=1) then cur_state <= next_state; end if; end process; o_logic : process (cur_state, inputs) begin out_sig <= 1; case cur_state is when fst_state => out_sig <= 0; when s_something => out_sig <= 1;
ns_logic : process (cur_state, inputs) begin next_state <= fst_state; case cur_state is when fst_state => next_state <= s_something; when s_something =>

when others null; end case; end process o_logic;

=>

next_state <= fst_state; when others null; end case; end process ns_logic; =>

curent state logic

output logic

next state logic

Block RAM
VirtexII component instantion
component RAMB16_S36 generic ( WRITE_MODE : string := "READ_FIRST"; ); port ( DI : in (31 downto 0); DIP : in std_logic_vector (3 downto 0); ADDR : in std_logic_vector (8 downto 0); EN : in std_logic; WE : in std_logic; SSR : in std_logic; CLK : in std_logic; DO : out std_logic_vector (31 downto 0); DOP : out std_logic_vector (3 downto 0) ); end component;

Synthesis library
The standard for VHDL Register Transfer Level Synthesis is IEEE Std 1076.6-1999.
basic synthesis library use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; arithmetic operations

works with unsigned words

The purpose of the standard is to dene a syntax and semantics for VHDL RTL synthesis. It denes a subset of IEEE 1076 (VHDL) that is intended to be used in common by all RTL synthesis tools.

Data types
Signal data types std_logic std_logic_vector(*) integer Constant format Binary - "1010101100000000" Hexadecimal - X"AB00" Integer format - conv_integer(const_integer)

Operators
Logical Operators: and, or, nand, nor, xor, xnor Relational Operators: =, /=, < , <= , > , >= Shift Operators: sll , srl , sla , sra , rol , ror Adding Operators: + , - , & Sign Operators: + , Multiplying Operators: * , / , mod , rem Miscellaneous Operators: ** , abs , not

Design issues
Inferring latches Incomplete sensitivity list Loop and Generate statements Seqvential assignment Technology consideration

Inferring latches
Code and circuit example
correct source

process (sel, a, b, c) begin case sel is when "00" => mux_out <= a; when "01" => mux_out <= b; when "10" => mux_out <= c; end case; end process;

process (sel, a, b, c) begin mx_out <= a; case sel is when "00" => mux_out <= a; when "01" => mux_out <= b; when "10" => mux_out <= c; end case; end process;

uncavered values

=>

latch generation

Incomplete sesitivity list

Missing signal at sensitivity list different behavior in function and time simulation. it is difcult to nd this error
a, b, c, d signals missing
process (sel) begin case sel is when "00" => mux_out when "01" => mux_out when "10" => mux_out when "11" => mux_out when others => null; end case; end process;

<= <= <= <=

a; b; c; d;

Loop and Generate statement

Loops and Genarate - this syntax construction can be used only for constant integer generation or loops.
dis_mem : for i in 0 to DATA_WIDTH1 generate INST_RAM16X1D : RAM16X1D port map ( D => data_in(i), WE => write_en, WCLK => clk, A0 => addr_a(0), A1 => addr_a(1), A2 => addr_a(2), A3 => addr_a(3), DPRA0 => addr_b(0), DPRA1 => addr_b(1), DPRA2 => addr_b(2), DPRA3 => addr_b(3), SPO => data_out_a(i), DPO => data_out_b(i) );f end generate;

Seqvential assignment
Order of signal assignments does not affect synthesis and simulation as long as the sensitivity list is complete. However, if using signals and variables the order may affect simulation and synthesis

Sig_s <= not Test1_v; Test1_v := Test2_v and B and C; Test2_v := D and E;

only affects simulation (not synthesis) Swapping these statements

Var1_v := B and C; Var1_v := A and B; output <= Var1_v;

Swapping these staetemnts affects synthesis and simulation

Technology consideration
The developer of a synthesizable behavioral VHDL description MUST consider the implementation technology when writing the code Some FPGA families do not have internal tri-state devices - behavioral descriptions that are based on internal tri-state busses will fail in the technology mapping phase Many PLDs have ip ops only on the I/O pins - state machines with too many I/O ports and state variables simply wont t

Design improvements
Basic issues logic delay wire delay Solution - using paralel technics Paralel blocks Pipeline

Paralel blocks
Basic paralel technic Easy for implementation Increasing throuput
PE Input data PE Output data

Pipeline
Basic paralel technic Paralel computing - similar computation time Can eliminate wire delay Higher freqvency can be reach
Reg Reg Reg

Conclusion
Model translation from higher to lower level Synthesis levels - use only RTL and Logic levels Use only predened templates Issues - inferring latches, incomplete sensitivity list, etc Design speed-up - pipeline and other paralel technics