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This document provides VHDL code for a 4:1 demultiplexer circuit using case statements. The code defines a demux1_4 entity with 4 output lines and a 2-bit select input line to demultiplex a single input bit. The case statement selects which output line equals the input bit based on the value of the select lines. A testbench is also provided to test the circuit by applying different input patterns and verifying the output.

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Mekonnen Getnet
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70 views2 pages

Simple 1

This document provides VHDL code for a 4:1 demultiplexer circuit using case statements. The code defines a demux1_4 entity with 4 output lines and a 2-bit select input line to demultiplex a single input bit. The case statement selects which output line equals the input bit based on the value of the select lines. A testbench is also provided to test the circuit by applying different input patterns and verifying the output.

Uploaded by

Mekonnen Getnet
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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Simple 1 : 4 Demultiplexer using case statements

Here is the code for 4 :1 DEMUX using case statements.The module has 4 single bit output lines and one 2 bit select input.The input line is defined as a single bit line.

library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity demux1_4 is port ( out0 : out std_logic; --output bit out1 : out std_logic; --output bit out2 : out std_logic; --output bit out3 : out std_logic; --output bit sel : in std_logic_vector(1 downto 0); bitin : in std_logic --input bit ); end demux1_4; architecture Behavioral of demux1_4 is begin process(bitin,sel) begin case sel is when "00" => out0 <= bitin; out1 <= '0'; out2 <= '0'; out3 <='0'; when "01" => out1 <= bitin; out0 <= '0'; out2 <= '0'; out3 <='0'; when "10" => out2 <= bitin; out0 <= '0'; out1 <= '0'; out3 <='0'; when others => out3 <= bitin; out0 <= '0'; out1 <= '0'; out2 <='0'; end case; end process; end Behavioral;
The testbench code used for testing the code is given below:

LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY testbench IS END testbench; ARCHITECTURE behavior OF testbench IS SIGNAL out0,out1,out2,out3,bitin : std_logic:='0'; SIGNAL sel : std_logic_vector(1 downto 0):="00"; BEGIN UUT : entity work.demux1_4 port map(out0,out1,out2,out3,sel,bitin); tb : PROCESS BEGIN bitin <= '1'; sel <="00"; wait for 2 ns; sel <="01"; wait for 2 ns; sel <="10"; wait for 2 ns; sel <="11"; wait for 2 ns; --more input combinations can be given here. END PROCESS tb; END;
The code was synthesized using XILINX ISE XST . The RTL schematic of the design is shown below:

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