8085 Programming
8085 Programming
CONTENTS
1. 8085 PROGRAMING
i) ii) iii) iv) v) vi) vii) viii) ix) x) xi) xii) 8-Bit Addition 8-Bit Subtraction 8-Bit Division Logical Operation Smallest Data Largest Data Ascending Order Descending Order Look Up Table Factorial Square Root Average
2. 8086 PROGRAMING
8-Bit Addition ii) 8-Bit Subtraction iii) 8-Bit Division iv) Logical Operation v) Smallest Data vi) Largest Data vii) Ascending Order viii) Descending Order
i) 3.
8086 PROGRAMING
8-Bit Addition 8-Bit Subtraction iii) 8-Bit Division iv) Logical Operation v) Smallest Data vi) Largest Data vii) Ascending Order viii) Descending Order
i) ii)
DEPT OF ECE
8085 PROGRAMMING
1. PROGRAMS BASED ON ARITHMETIC AND LOGIC INSTRUCTIONS
DEPT OF ECE 2
i)
OPCODES 3A 50 41 47 3A 51 41 90 32 52 41 76
HLT
76 OUTPUT: (4152) = 0E
DEPT OF ECE
4101 4102 4103 4104 4105 4106 4107 4108 4109 410A 410B 410C 410D 410E 410F 4110 4111 4112 4113 4114 4115 4116
00 42 0E 00 AF 46 23 56 82 D2 0E 41 0C 05 C2 09 41 23 77 23 71 76
REPT:
C B REPT
H M,A H M,C
OPCODES 3A 01 42 47 3A 00 42 0E 00 B8 DA
LABEL
AGAIN:
CMP JC
410B 410C 410D 410E 410F 4110 4111 4112 4113 4114 4115 4116 4117 4118 4119
12 41 90 0C C3 09 41 32 03 42 79 32 02 42 76 HLT (4200) = 40H MOV STA A,C 4202 STORE: STA 4203 SUB INR JMP B C AGAIN
OPCODES 3A 50 41 47 3A 51 41 4F A0 32 52 41 79
MOV
A,C
5
410D 410E 410F 4110 4111 4112 4113 4114 4115 4116 4117 4118 4119 411A 411B
B0 32 53 41 79 A8 32 54 41 79 2F 32 55 41 76
ORA STA
B 4153
A,C B 4154
A,C A 4155
2)
LOOP:
A,M B LOOP
DEPT OF ECE
(4305)= 12
RESULT:
MEMORY ADDRESS 4100 4101 4102 4103 4104 4105 4106 4107 4108 4109 410A 410B 410C 410D 410E 410F 4110 4111 4112 4113 4114 INPUT:
LOOP:
A,M B LOOP
STA
4300
HLT
(4305)=12
7
DEPT OF ECE
RESULT:
(4300)= FF
OPCODES 3A 00 42 47 05 21 00 42 4E 0D 23 7E 23 BE D2 16 41 56 77 2B 72 23 0D C2 0B 41 05 C2 05 41 76
LABEL
MNEMONICS LDA MOV DCR LXI MOV DCR INX MOV INX CMP JNC
LOOP2:
LOOP1:
DCR JNZ
B LOOP2
HLT
8
(4205)= 34 (4205)=04
OUTPUT:(4201)=FE (4202)=CD
OPCODES 3A 00 42 47 05 21 00 42 4E 0D 23 7E 23 BE DA 16 41 56 77 2B 72 23 0D C2 0B 41 05 C2 05
LABEL
MNEMONICS LDA MOV DCR LXI MOV DCR INX MOV INX CMP JC
LOOP2:
LOOP1:
DCR JNZ
B LOOP2
411D 411E
41 76 HLT
(4205)= 34 (4205)=FE
OUTPUT:(4201)=04 (4202)=23
OPCODES 3A 00 42 47 E6
LABEL
4105 4106 4107 4108 4109 410A 410B 410C 410D 410E 410F 4110 4111 4112 4113 4114 4115 4116 4117 4118 4119 411A 411B 411C 411D 411E 411F 4120 4121 4122 4123 INPUT: (4200)=04
0F CD 1A 41 32 01 42 78 E6 F0 07 07 07 07 CD 1A 41 32 02 42 76 FE 0A DA 1F 41 C6 07 C6 30 C9 SKIP: SUB1:
CALL STA
SUB1 4201
A,B F0
SUB1
STA
4202
07 30
iii)
HEX TO BCD
11
DEPT OF ECE
MEMORY ADDRESS 4100 4101 4102 4103 4104 4105 4106 4107 4108 4109 410A 410B 410C 410D 410E 410F 4110 4111 4112 4113 4114 4115 4116 4117 4118 4119 INPUT: (4150)=FF
OPCODES 21 50 41 16 00 AF 4E C6 01 27 D2 0E 41 14 0D C2 07 41 32 51 41 7A 32 52 41 76
LABEL
LOOP2:
D C LOOP2
STA
4151
MOV STA
A,D 4152
iv)
BCD TO HEX
MEMORY ADDRESS 4100 4101 4102 OPCODES 21 50 41 MNEMONICS LXI OPERANDS H,4150
DEPT OF ECE
12
4103 4104 4105 4106 4107 4108 4109 410A 410B 410C 410D INPUT: (4150) = 02 MSD (4151) = 09 LSD
7E 87 47 87 87 80 23 86 23 77 76
MOV ADD MOV ADD ADD ADD INX ADD INX MOV HLT
RESULT: (4152) = 1D H = 29 D
OPCODES 21 25 41 3A 50 41 FE 0A DA 11 41 3E FF 32 51 41 76 3D 4F 06 00 09 7E 32 51
LABLE
MNEMONICS LXI LDA CPI JC MVI STA HLT DCR MOV MVI DAD MOV STA
AFTER:
4119 411A LOOK UP TABLE (4125)=01 (4126)=04 (4127)=09 INPUT: (4150) = 05 INPUT: (4150) = 11
41 76
HLT
OPCODES 31 00 42 3A 00 43 FE 02 DA 1A 41 16 00 5F 3D 4F CD 21 41 EB 22 00 44 C3 1D 41 21 01
LABLE
MNEMONICS LXI LDA CPI JC MVI MOV DCR MOV CALL XCHG SHLD JMP
LAST:
LXI
411C 411D 411E 411F 4120 4121 4122 4123 4124 4125 4126 4127 4128 4129 412A 412B 412C 412D 412E 412F INPUT: (4300) = 04
00 22 01 44 76 21 00 00 41 19 05 C2 25 41 EB 0D C4 10 41 C9
END:
SHLD HLT LXI MOV DAD DCR JNZ XCHG DCR CNZ RET
4401
FACTO:
BACK:
C FACTO
OPCODES 3A 00 42 47 0E 02 CD 1F 41 5A 78 4A CD 1F 41 7A 83 0E 02
LABLE
OPERANDS 4200H B,A C,02H DIV E,D A,B C,D DIV A,D E C,02H
REP:
15
4113 4114 4115 4116 4117 4118 4119 411A 411B 411C 411D 411E 411F 4120 4121 4122 4123 4124 4125 4126 4127 INPUT: (4200) = 04
CD 1F 41 7B BA C2 09 41 32 01 42 76 16 00 91 14 B9 D2 21 41 C9
CALL MOV CMP JNZ STA HLT MVI SUB INR CMP JNC RET
DIV: NEXT:
D,00H C D C NEXT
RESULT: (4201) = 02
MEMORY ADDRESS 4100 4101 4102 4103 4104 4105 4106 4107 4108 4109 410A 410B 410C 410D 410E
DEPT OF ECE
OPCODES 21 00 42 4E 41 AF 23 56 82 23 0D C2 07 41 0E
LABLE
MNEMONICS LXI MOV MOV XRA INX MOV ADD INX DCR JNZ MVI
RPT:
410F 4110 4111 4112 4113 4114 4115 4116 4117 4118 4119 411A 411B 411C 411D
00 B8 DA 19 41 90 0C C3 10 41 79 32 00 43 76
INPUT: (4200) = 04 --- COUNT (4201) = 01 (4202) = 02 (4203) = 03 (4204) = 05 RESULT: (4300) = 02
8086 PROGRAMMING
8086 PROGRAMMING
1. ADDITION OF TWO 16-BIT NUMBERS
DEPT OF ECE
17
MEMORY ADDRESS 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 100A 100B 100C
OPCODES 8B 06 00 11 03 06 02 11 89 06 00 12 F4
MNEMONICS MOV
OPERANDS AX,[1100]
ADD
AX,[1102]
MOV
[1200],AX
HLT
RESULT:
DEPT OF ECE
18
MEMORY ADDRESS 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 100A 100B 100C
OPCODES 8B 06 00 11 2B 06 02 11 89 06 00 12 F4
MNEMONICS MOV
OPERANDS AX,[1100]
SUB
AX,[1102]
MOV
[1200],AX
HLT
DEPT OF ECE
19
RESULT:
OPCODES 8B 06 00 11 8B 1E 02 11 F7 E3 89 16 00 12 89 06 02 12 F4
MNEMONICS
OPERANDS
MOV AX , [1100]
MOV BX , [1102]
MUL BX
MOV [1200] , DX
MOV [1202] , AX
1011 1012
20
HLT
RESULT: [1202]
4. 32-BIT DIVISION
DEPT OF ECE
21
OPCODES 8B 16 00 11 8B 06 02 11 8B 0E 04 11 F7 F1 89 06 00 12 89 16 02 12 F4
MNEMONICS
OPERANDS
DATA:
1002 1003 1004 1005 1006 1007 1008 1009 100A 100B 100C 100D 100E 100F 1010 1011 1012 1013 1014 1015 1016
DIV CX
MOV [1200] , AX
MOV [1202] , DX
HLT
RESULT:QUOTIENT: REMAINDER:
22
5. LOGICAL OPERATIONS
DEPT OF ECE
23
MEMORY ADDRESS 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 100A 100B 100C 100D 100E 100F 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 101A 101B 101C
DEPT OF ECE
OPCODES C6 C4 FF C6 C0 F2 20 C4 88 26 00 15 08 C4 88 26 01 15 30 C4 88 26 02 15 F6 D4 88 26 03 15 F4
MNEMONICS
OPERANDS
MOV AH,0FF
MOV AL,0F2
AND AH,AL
MOV [1500],AH
OR AH,AL
MOV [1501],AH
XOR AH,AL
MOV [1502],AH
NOT AH
MOV [1503],AH
101D 101E
24
HLT
[1501] = F2
[1502] = 00
DEPT OF ECE
25
MEMORY ADDRESS 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 100A 100B 100C 100D 100E 100F 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 101A 101B 101C
DEPT OF ECE 101D
OPCODES C7 C6 00 11 8A 0C FE C9 C7 C6 00 11 8A 2C FE CD 46 8A 04 46 3A 04 72 05 86 04 86 44 FF FE CD
LABEL
MNEMONICS
OPERANDS
MOV SI,1100
MOV CL,[SI]
DEC CL
REPEAT:
MOV SI,1100H
MOV CH,[SI]
DEC CH
CMP AL,[SI]
JC AHEAD
XCHG AL,[SI]
XCHG AL,[SI-1]
AHEAD:
DEC CH
26
101E
DEPT OF ECE
27
MEMORY ADDRESS 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 100A 100B 100C 100D 100E 100F 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 101A 101B 101C
DEPT OF ECE 101D
OPCODES C7 C6 00 11 8A 0C FE C9 C7 C6 00 11 8A 2C FE CD 46 8A 04 46 3A 04 73 05 86 04 86 44 FF FE CD
LABEL
MNEMONICS
OPERANDS
MOV SI,1100
MOV CL,[SI]
DEC CL
REPEAT:
MOV SI,1100H
MOV CH,[SI]
DEC CH
CMP AL,[SI]
JNC AHEAD
XCHG AL,[SI]
XCHG AL,[SI-1]
AHEAD:
DEC CH
28
101E
DEPT OF ECE
29
MEMORY ADDRESS 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 100A 100B 100C 100D 100E 100F 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 101A 101B 101C
DEPT OF ECE 101D
OPCODES C7 C6 00 11 C7 C7 00 12 8A 0C 46 8A 04 FE C9 46 8A 1C 38 D8 72 02 88 D8 FE C9 75 F3 88 05 F4
LABEL
MNEMONICS
OPERANDS
MOV SI,1100
MOV DI,1200
MOV CL,SI
DEC CL
AGAIN:
CMP AL,BL
JC AHEAD
MOV AL,BL
AHEAD:
DEC CL
JNZ AGAIN
MOV [DI],AL
30
101E
HLT
8. LARGEST DATA
DEPT OF ECE
31
MEMORY ADDRESS 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 100A 100B 100C 100D 100E 100F 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 101A 101B 101C
DEPT OF ECE 101D
OPCODES C7 C6 00 11 C7 C7 00 12 8A 0C 46 8A 04 FE C9 46 8A 1C 38 D8 73 02 88 D8 FE C9 75 F3 88 05 F4
LABEL
MNEMONICS
OPERANDS
MOV SI,1100
MOV DI,1200
MOV CL,SI
DEC CL
AGAIN:
CMP AL,BL
JNC AHEAD
MOV AL,BL
AHEAD:
DEC CL
JNZ AGAIN
MOV [DI],AL
32
101E
HLT
INTERFACING PROGRAMS 1. AIM: TO INITIALIZE PORT A AS INPUT PORT AND PORT B AS OUTPUT PORT IN MODE 0 MEMORY ADDRESS 4100 4101 4102 4103 4104 4105 4106 4107 4108 4109 OPCODES 3E 90 D3 C6 DB C0 32 00 45 76 MNEMONICS MVI OUT IN STA HLT OPERANDS A,90 0C6H 0C0H 4500H
CONTROL WORD
DEPT OF ECE
33
PROCEDURE: 1. Enter the program starting from user RAM address 4100h. 2. Set a known data at the SPDT switches. 3. Execute the program 4. The data as set by the SPDT switch settings is input into the accumulator and is stored at location 4500. 5. The data output at the 4500 is same as the SPDT switch settings
2. AIM: TO INITILIZE 8253 AND 8251 AND TO CHECK THE TRANSMISSION
1.The program first initializes 8253 to give an output clock frequency of 150 khz at channel 0 which will give a 9600 baud rate of 8251. 2. Output of channel 0 is connected to transmitter clock and receiver clock of 8251. 3. Connect RTS with CTS and TXD with RXD, by setting the jumpers accordingly. Now execute the program. I/O DECODING 8251 is selected with address
Since the address line A1 is connected to control/data input (C/D) of 8251, the control register of 8251 is selected when
The I/O address for control register, Channel 0, Channel 1 and Channel 2 are A7 1 1 1 1 A6 1 1 1 1 A5 0 0 0 0 A4 0 0 0 0 A3 1 1 1 1 A2 1 0 0 1 A1 1 0 1 0 A0 0 0 0 0 HEX CE C8 CA CC
OPCODES 3E 36 D3 CE
35
4104 4105 4106 4107 4108 4109 410A 410B 410C 410D 410E 410F 4110 4111 4112 4113 4114 4115 4116 4117 4118
3E 0A D3 C8 3E 00 D3 C8 3E 4E D3 C2 3E 37 D3 C2 3E 41 D3 C0 CF
MVI OUT MVI OUT MVI OUT MVI OUT MVI OUT RST
A,0AH 0C8H A,00 0C8H A,4E 0C2H A,37H 0C2H A,41 0C0H 1
3. AIM: ROLLING DISPLAY (DISPLAY MESSAGE IS HELP US) MEMORY ADDRESS 4100 4101 4102 4103 4104 4105 4106 4107 4108 4109 410A 410B 410C 410D 410E 410F 4110 4111 4112 4113 4114
DEPT OF ECE
OPCODES 21 2C 41 16 0F 3E 10 D3 C2 3E CC D3 C2 3E 90 D3 C2 76 D3 C0 CD
LABEL START:
OPERANDS H,POINTER D,0FH A,10H CNT A,0CCH CNT A,90H CNT A,M DAT DELAY
36
LOOP:
4115 4116 4117 4118 4119 411A 411B 411C 411D 411E 411F 4120 4121 4122 4123 4124 4125 4126 4127 4128 4129 412A 412B 412C 412D 412E 412F 4130 4131 4132 4133 4134 4135 4136 4137 4138 4139 413A 413B LOOK-UP TABEL: [412C] = FF [4130] = FF [4134] = 98 [4138] = FE
DEPT OF ECE
1F 41 23 15 C2 11 41 C3 00 41 06 A0 0E FF 0D C2 23 41 05 C2 21 41 C9 FF FF FF FF FF FF FF FF 88 68 7C C8 1C 29 FF FF
INX DCR JNZ JMP DELAY: LOP1: LOP2: MVI MVI DCR JNZ DCR JNZ RET
FF FF 68 1C
FF FF 7C 29
FF FF C8 FF
37
SEGMENT DEFINITION:
CORRESPONDENCE BETWEEN THE DATA BUS AND OUTPT PORT BITS OF 8279 AND SEGMENT RELATIONSHIP. DATA BUS 8279 OUTPUT SEGMENTS D7 A3 d D6 A2 c D5 A1 b D4 A0 a D3 B3 dp D2 B2 g D1 B1 f D0 B0 e
D0 bit of the byte send to the display RAM corresponds to B0 and D7 of the byte sent to the display RAM corresponds A3. In order to light up a segment the corresponding bit of data written into the display RAM should be a 0.
4. ANALOG TO DIGITAL CONVERTION PROCEDURE: 1.Place jumper J2 in C position 2.Place jumper J5 in A position 3.Enter and execute the program 4.Vary th analog input(using trimpot) and verify the digital data displayed with that data stored in memory
MEMORY ADDRESS 4100 4101 4102 4103 4104 4105 4106 4107
DEPT OF ECE
OPCODES 3E 10 D3 C8 3E 18 D3 C8
LABEL
4108 4109 410A 410B 410C 410D 410E 410F 4110 4111 4112 4113 4114 4115 4116 4117 4118 4119 411A 411B 411C 411D 411E 411F 4120 4121
3E 01 D3 D0 AF AF AF 3E 00 D3 D0 DB D8 E6 01 FE 01 C2 13 41 DB C0 32 50 41 76
MVI OUT XRA XRA XRA MVI OUT LOOP: IN ANI CPI JNZ IN STA HLT
Theory: A 3 to 8 decoded 74LS138(U2) is employed to generate I/O decoding logic.Pin1,Pin2 and Pin3 of 74LS138(U2) is employed to generate I/O decoding logic.Pin1, Pin2 and Pin3 of 74LS138 are connected to address lines A3,A4 and A5 respectively.IOR and IOW signals are NANDed together and the NAND gate output is connected to Pin6 of 74LS138. Similarly the Address lines A6 and A7 are NAND gate output lied to Pin5 of the 3 to 8 decoder.Pin4 is grounded. The I/O address for the latch 74LS174 which latches the data bus to ADD A,ADD B, ADD C and ALE 1 and ALE 2 is
The buffer 74LS244 transfers the converted data outputs to data bus is selected when
DEPT OF ECE 39
The flip flop 74LS74 which transfers the D0 line status to the SOC pin ADC 0809 is selected
The EOC output ADC1 and ADC2 is transferred to D0 line by means of two tristate buffers. The EOC1 is selected when
OPCODES 3E 00 D3 C0 3C
C2 02 41 C3 00 41
JNZ JMP
L1 START
THEORY: DAC 0800 is a monolithic, high speed ,current output Digital to Analog converter. I/O DECODING: The ICs 74LS138 and 74LS00 form the address decoding logic in this interface board. The address lines A3,A4 and A5 are tied to pin1,pin2 and pin3 of 74ls138 respectively. The address lines A6 and A7 are NANDed together and the NAND gate output is conncted to pin 5 of 74LS138.Similarly IOW and IOR signals are NANDed and the NAND gate output is connected to pin 6 of 74LS1328.Pin 4 is grounded.
6. To run the stepper motor in both forward and reverse direction with delay
MEMORY ADDRESS 4100 4101 4102 4103 4104 4105 4106 4107 4108 4109 410A 410B 410C 410D 410E 410F 4110
DEPT OF ECE
OPCODES 21 1A 41 06 04 7E D3 C0 11 03 03 00 1B 7B B2 C2 0B
LABEL START:
REPT:
DELAY:
D A,E D DELAY
41
4111 4112 4113 4114 4115 4116 4117 4118 4119 411A 411B 411C 411D
41 23 05 C2 05 41 C3 00 41 09 06 06 0A
H B REPT START 0A
PROCEDURE: 1. Enter the program starting from location 4100. 2. Execute the program 3. Stepper motor runs in forward direction 4.speed can be varied by varying the count at DE pair 4. To run the stepper motor in anticlockwise direction the sequence should be given is 0Ah,06H,05H,09H Theory: A motor in which the rotor is able to assume only discrete stationary angular position is a stepper motor. The rotary motion occurs in a stepwise manner from one equilibrium position to the next. As shown in the figure below the four pole structure is continuous with the stator frame and the magnetic field passes through the cylindrical stator annular ring. The rotor magnetic system has two end faces. The left face is permanently magnetized as south pole and the right face as north pole. The south pole structure and north pole structure possess similar pole faces. The north pole structure is twisted with respect to the south pole structure so that south pole comes precisely between two north poles. The north pole structures offset with respect to the south pole structure by one pole pitch. The step size is
Where Ns is the No. of stator poles Nr is the No. of pairs of rotor poles
DEPT OF ECE
42
FIGURE: Stepper Motor Cross-sectional View Table: Wave switching scheme ANTICLOCKWISE A1 A2 A3 1 0 0 0 0 0 0 1 0 0 0 1 CLOCKWISE A1 A2 A3 1 0 0 0 0 1 0 1 0 0 0 0
STEP 1 2 3 4
A4 0 1 0 0
STEP 1 2 3 4
A4 0 0 0 1
8051 PROGRAMMING
1.To perform addition of two 8-bit data using 8051 MEMORY ADDRESS 4100 4101 4102 4103 4104 4105 4106 4107 4108 4109 RESULT:
DEPT OF ECE 43
OPCODES 74 20 24 10 90 45 00 F0 80 FE
LABEL
HERE:
2. TO PERFORM SUBTRACTION OF TWO 8 BIT DATA USING 8051 MEMORY ADDRESS 4100 4101 4102 4103 4104 4105 4106 4107 4108 4109 OPCODES 74 20 94 10 90 45 00 F0 80 FE LABEL MNEMONICS MOV SUBB MOV MOVX SJMP OPERANDS A,#DATA1 A,#DATA2 DPTR,#4500 @DPTR,A HERE
HERE:
RESULT: INPUT: DATA1=20 DATA2=10 OUTPUT: [4500]=10 3. To obtain product of two 8-bit number using 8051 MEMORY ADDRESS 4100 4101 4102 4103 4104 4105 4106 4107 4108 4109 410A 410B 410C 410D 410E 410F OPCODES LABEL 74 0A 75 F0 88 A4 90 45 00 F0 A3 E5 F0 F0 80 FE HERE: MNEMONICS MOV MOV MUL MOV MOVX INC MOV MOVX SJMP OPERANDS A,#DATA1 B,#DATA2 AB DPTR,#4500 @DPTR,A DPTR A,B @DPTR,A HERE
DEPT OF ECE
44
INPUT: DATA1:0A DATA2:88 OUTPUT: [4500] = 50 (LSB) [4501] = 05 (MSB) 4. 8 BIT DIVISION USING 8051 MEMORY ADDRESS 4100 4101 4102 4103 4104 4105 4106 4107 4108 4109 410A 410B 410C 410D 410E 410F OPCODES LABEL 74 65 75 F0 08 84 90 45 00 F0 A3 E5 F0 F0 80 FE HERE: MOVX SJMP @DPTR,A HERE MNEMONICS MOV MOV DIV MOV MOVX INC MOV OPERANDS A,#DATA1 B,#DATA2 AB DPTR,#4500 @DPTR,A DPTR A,B
DATA: DATA1 = 65-DIVIDEND DATA2 = 08-DIVISOR RESULT: [ 4500 ] = 0C QUOTIENT [ 4501 ] =05 REMAINDER
OPCODES LABEL 90 45 00 E0 75
4105 4106 4107 4108 4109 410A 410B 410C 410D 410E 410F 4110 4111 4112 4113 4114 4115 4116 4117 4118 4119
F0 64 84 90 45 01 F0 E5 F0 75 F0 0A 84 A3 F0 A3 E5 F0 F0 80 FE HLT:
DIV MOV
AB DPTR,#4501
DATA: [4500] = FF RESULT: [4501] = 02 [4502] = 05 [4503] = 05 2.2. DECIMAL TO HEX CONVERSION USING 8051 MEMORY ADDRESS 4100 4101 4102 4103 4104 4105 4106 4107 4108 4109 410A
DEPT OF ECE
OPCODES LABEL 90 42 00 E0 75 F0 0A A4 F5 F0 A3
AB B,A DPTR
46
E0 25 F0 A3 F0 80 FE HLT:
DATA: [4200] = 03 [4201] = 06 RESULT: [4202] = 24 3.1 LARGEST DATA USING 8051 OPCODES LABEL 90 42 00 E0 F5 40 7D 03 A3 E0 B5 40 08 A3 DD F9 E5 40 F0 80 FE 40 F6
47
MEMORY ADDRESS 4100 4101 4102 4103 4104 4105 4106 4107 4108 4109 410A 410B 410C 410D 410E 410F 4110 4111 4112 4113 4114 4115 4116
DEPT OF ECE
LOOP3:
LOOP2:
HLT: LOOP1:
SJMP JC
F5 40 80 F2
MOV SJMP
40H,A LOOP2
DATA: [4200] = 05 [4201] = 06 [4203] = 01 RESULT: [4204] = 0F 3.2 SMALLEST DATA USING 8051 OPCODES LABEL 90 42 00 E0 F5 40 7D 03 A3 E0 B5 40 08 A3 DD F9 E5 40 F0 80 FE 50 F6 F5 40 80 SJMP MOV LOOP1: JNC HLT: MOVX SJMP MOV LOOP2: INC DJNZ
[4202] = 0F
MEMORY ADDRESS 4100 4101 4102 4103 4104 4105 4106 4107 4108 4109 410A 410B 410C 410D 410E 410F 4110 4111 4112 4113 4114 4115 4116 4117 4118 4119
DEPT OF ECE
LOOP3:
411A
F2 [4202] = 0F
ASCENDING ORDER USING 8051 MEMORY ADDRESS 4100 4101 4102 4103 4104 4105 4106 4107 4108 4109 410A 410B 410C 410D 410E 410F 4110 4111 4112 4113 4114 4115 4116 4117 4118 4119 411A 411B 411C OPCODES LABEL 7B 04 7C 04 90 45 00 AD 82 AE 83 E0 F5 F0 A3 E0 F8 C3 95 F0 50 13 C0 82 C0 83 8D 82 8E MOV DPH,R6
49
REPT1:
R5,DPL R6,DPH A,@DPTR B,A DPTR A,@DPTR R0,A C A,B CHKNXT DPL DPH DPL,R5
REPT:
EXCH:
DEPT OF ECE
411D 411E 411F 4120 4121 4122 4123 4124 4125 4126 4127 4128 4129 412A 412B 412C 412D 412E 412F 4130 4131 4132 4133 4134 4135 4136 4137
83 E8 F0 D0 83 D0 82 E5 F0 F0 88 F0 DB E3 1C EC FB 0C 8D 82 8E 83 A3 DC D1 80 FE [4501] [4504] [4501] [4504] = = = = 1C 76 2A F9 [4502] = F9 [4502] =76 HLT: SJMP HLT INC DJNZ DPTR R4,REPT1 MOV DPH,R6 DEC MOV MOV INC MOV R4 A,R4 R3,A R4 DPL,R5 CHKNXT: DJNZ R3,REPT MOVX MOV @DPTR,A B,R0 MOV A,B POP DPL MOV MOVX POP A,R0 @DPTR,A DPH
4.2
DEPT OF ECE
MEMORY ADDRESS
OPCODES LABEL
MNEMONICS
OPERANDS
DEPT OF ECE
51
4100 4101 4102 4103 4104 4105 4106 4107 4108 4109 410A 410B 410C 410D 410E 410F 4110 4111 4112 4113 4114 4115 4116 4117 4118 4119 411A 411B 411C 411D 411E 411F 4120 4121 4122 4123 4124
DEPT OF ECE
7B 04 7C 04 90 45 00 AD 82 AE 83 E0 F5 F0 A3 E0 F8 C3 95 F0 50 13 C0 82 C0 83 8D 82 8E 83 E8 F0 D0 83 D0 82 E5
REPT1:
R5,DPL R6,DPH A,@DPTR B,A DPTR A,@DPTR R0,A C A,B CHKNXT DPL DPH DPL,R5 DPH,R6 A,R0 @DPTR,A DPH DPL A,B
52
REPT:
EXCH:
4125 4126 4127 4128 4129 412A 412B 412C 412D 412E 412F 4130 4131 4132 4133 4134 4135 4136 4137
F0 F0 88 F0 DB E3 1C EC FB 0C 8D 82 8E 83 A3 DC D1 80 FE = 1C = 76 =88 = 1C [4502] = F9 [4502] =76 HLT: SJMP HLT INC DJNZ DPTR R4,REPT1 MOV DPH,R6 DEC MOV MOV INC MOV R4 A,R4 R3,A R4 DPL,R5 CHKNXT: DJNZ R3,REPT MOVX MOV @DPTR,A B,R0
DATA: [4500] = 2A [4501] [ 4503] = 88 [4504] RESULT: [4500] =F9 [4501] [ 4503] =2A[4504]
5.1 AVERAGE OF N NUMBERS USING 8051 MEMORY ADDRESS 4100 4101 4102 4103 4104 4105 4106 4107 4108
DEPT OF ECE
OPCODES LABEL 90 42 00 E0 F8 FA 75 F0 00
53
4109 410A 410B 410C 410D 410E 410F 4110 4111 4112 4113 4114 4115 4116 4117 4118 4119 411A 411B 411C
A3 E0 25 F0 F5 F0 A3 D8 F8 E5 F0 8A F0 84 90 45 00 F0 80 FE
ADD:
INC MOVX ADD MOV INC DJNZ MOV MOV DIV MOV
@DPTR,A HLT
[4204] = 03
8085 OPCODES
HEX CE 8F 88 89 8A 8B MNEMONIC ACI ADC ADC ADC ADC ADC 8-BIT A B C D E HEX BC BD BE D4 C4 F4 MNEMONIC CMP CMP CMP CNC CNZ CP H L M 16-BIT 16-BIT 16-BIT HEX 2C 34 . 03 13 23 33 MNEMONIC INR INR INX INX INX INX L M B D H SP 54
DEPT OF ECE
8C 8D 8E 87 80 81 82 83 84 85 86 C6 A7 A0 A1 A2 A3 A4 A5 A6 E6 CD DC FC 2F 3F BF B8 B9 BA
ADC ADC ADC ADD ADD ADD ADD ADD ADD ADD ADD ADI ANA ANA ANA ANA ANA ANA ANA ANA ANI CALL CC CM CMA CMC CMP CMP CMP CMP
EC FE E4 CC 27 . 09 19 29 39 3D . 05 0D 15 1D 25 2D 35 0B 1B 2B 3B F3 FB 76 DB 3C
CPE CPI CPO CZ DAA DAD DAD DAD DAD DCR DCR DCR DCR DCR DCR DCR DCR DCX DCX DCX DCX DI EI HLT IN INR INR INR INR INR
DA FA C3 D2 C2 F2 EA E2 CA 3A 0A 1A 2A . 01 11 21 31 7F 78 79 7A 7B 7C 7D
JC JM JMP JNC JNZ JP JPE JPO JZ LD A LD AX LD AX LHL D LXI LXI LXI LXI MO V MO V MO V MO V MO V MO V MO V MO V MO V MO V MO V MO V MO V
16-BIT 16-BIT 16-BIT 16-BIT 16-BIT 16-BIT 16-BIT 16-BIT 16-BIT 16-BIT B D 16-BIT B,16BIT D,16BIT H,16BIT SP,16BIT A,A A,B A,C A,D A,E A,H A,L A,M B,A B,B B,C B,D B,E 55
8-BIT A B C D E
7E 47 40 41 42 43
A B C D
. 04 0C 14 1C
DEPT OF ECE
BB
CMP
24
INR
44
MO V
B,H
HEX 45 46 4F 48 49 4A 4B 4C 4D 4E 57 50 51 52 53 54 55 56 5F 58 59 5A 5B 5C 5D 5E 67 60 61 62 63 64 65 66
MNEMONIC
HEX 6A 6B 6C 6D 6E 77 70 71 72 73 74 75 3E . 06 0E 16 1E 26 2E 36 . 00 B7 B0 B1 B2 B3 B4 B5 B6 F6 D3 E9 C1 D1
MNEMONIC
HEX D5 E5 F5 17 1F D8 C9 20 . 07 F8 D0 C0 F0 E8 E0 0F C7 CF D7 DF E7 EF F7 FF C8 9F 98 99 9A 9B 9C 9D
MNEMONIC PUS H PUS H PUS H RAL RAR RC RET RIM RLC RM RNC RNZ RP RPE RPO RRC RST RST RST RST RST RST RST RST RZ SBB SBB SBB SBB SBB SBB SBB SBB SBI
MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV
B,L B,M C,A C,B C,C C,D C,E C,H C,L C,M D,A D,B D,C D,D D,E D,H D,L D,M E,A E,B E,C E,D E,E E,H E,L E,M H,A H,B H,C H,D H,E H,H H,L H,M
MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MVI MVI MVI MVI MVI MVI MVI MVI NOP ORA ORA ORA ORA ORA ORA ORA ORA ORI OUT PCH L POP POP
L,D L,E L,H L,L L,M M,A M,B M,C M,D M,E M,H M,L A,8-BIT B,8-BIT C,8-BIT D,8BIT E,8-BIT H,8BIT L,8-BIT M,8BIT A B C D E H L M 8-BIT 8-BIT
D H PSW
0 1 2 3 4 5 6 7 A B C D E H L M 8-BIT 56
B D
9E DE
DEPT OF ECE
6F 68 69
E1 F1 C5
H PSW B
22 30 F9
16-BIT
HEX 32 . 02 12 37 97 90 91 92 93 94 95 96 D6 EB AF A8 A9 AA AB AC AD AE EE E3
MNEMONIC STA STAX STAX STC SUB SUB SUB SUB SUB SUB SUB SUB SUI XCH G XRA XRA XRA XRA XRA XRA XRA XRA XRI XTHL 16-BIT B D A B C D E H L M 8-BIT
A B C D E H L M 8-BIT
DEPT OF ECE
57
8051 OPCODES
HEX CODE 11 31 51 71 91 B1 D1 F1 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 34 35 36 37 38 39 3A
NUMBE R OF BYTES 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 2 2 1 1 1 1 1
MNEMO NIC ACALL ACALL ACALL ACALL ACALL ACALL ACALL ACALL ADD ADD ADD ADD ADD ADD ADD ADD ADD ADD ADD ADD ADDC ADDC ADDC ADDC ADDC ADDC ADDC
OPERANDS code addr code addr code addr code addr code addr code addr code addr code addr A,#DATA A,data addr a,@R0 A,@R1 A,R0 A,R1 A,R2 A,R3 A,R4 A,R5 A,R6 A,R7 A,#Data A,data addr A,@R0 A,@R1 A,R0 A,R1 A,R2
HEX COD E 3C 3D 3E 3F . 01 21 41 61 81 A1 C1 E1 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 82
NUMBE R OF BYTES 1 1 1 1 2 2 2 2 2 2 2 2 2 3 2 2 1 1 1 1 1 1 1 1 1 1 2
MNEMO NIC ADDC ADDC ADDC ADDC AJMP AJMP AJMP AJMP AJMP AJMP AJMP AJMP ANL ANL ANL ANL ANL ANL ANL ANL ANL ANL ANL ANL ANL ANL ANL
OPERANDS A,R4 A,R5 A,R6 A,R7 code addr code addr code addr code addr code addr code addr code addr code addr data addr,A data addr,# data A,# data A,data addr A,@R0 A,@R1 A,R0 A,R1 A,R2 A,R3 A,R4 A,R5 A,R6 A,R7 C,bit addr
DEPT OF ECE
58
HEX COD E
NUMB ER OF BYTES
MNEM ONIC
OPERANDS
HEX CODE
NUMBE R OF BYTES
MNEMO NIC
OPERANDS
B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF C2 C3 E4 B2 B3 F4 D4 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 84 D5
3 3 3 3 3 3 3 3 3 3 3 3 2 1 1 2 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 3
CJNE CJNE CJNE CJNE CJNE CJNE CJNE CJNE CJNE CJNE CJNE CJNE CLR CLR CLR CPL CPL CPL DA DEC DEC DEC DEC DEC DEC DEC DEC DEC DEC DEC DEC DIV DJNZ
A,# data,Code addr A, data addr, Code addr . @R0,# data,code addr . @R1,# data,code addr R0, # data, code addr R1, # data, code addr R2, # data, code addr R3, # data, code addr R4, # data, code addr R5, # data, code addr R6, # data, code addr R7, # data, code addr bit addr C A bit addr C A A A data addr . @R0 . @R1 R0 R1 R2 R3 R4 R5 R6 R7 AB data addr, code addr
DA DB DC DD DE DF . 04 . 05 . 06 . 07 . 08 . 09 0A 0B 0C 0D 0E 0F A3 20 10 40 73 30 50 70 60 12 . 02 74 75 76 77
2 2 2 2 2 2 1 2 1 1 1 1 1 1 1 1 1 1 1 3 3 2 1 3 2 2 2 3 3 2 3 2 2
DJNZ DJNZ DJNZ DJNZ DJNZ DJNZ INC INC INC INC INC INC INC INC INC INC INC INC INC JB JBC JC JMP JNB JNC JNZ JZ LCALL LJMP MOV MOV MOV MOV
R2,code addr R3,code addr R4,code addr R5,code addr R6,code addr R7,code addr A data addr . @R0 . @R1 R0 R1 R2 R3 R4 R5 R6 R7 DPTR bit addr,code addr bit addr,code addr code addr . @A + DPTR bit addr,code addr code addr code addr code addr code addr code addr A,#data data addr,# data . @R0,# data . @R1,# data
DEPT OF ECE
59
HEX COD E
7A 7B 7C 7D 7E 7F 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 92 A2 E5 E6 E7 E8 E9 EA EB EC ED EE EF F5 F6 F7
NUMBE R OF BYTES
2 2 2 2 2 2 3 2 2 2 2 2 2 2 2 2 2 3 2 2 2 1 1 1 1 1 1 1 1 1 1 2 1 1
MNEM ONIC
MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV
OPERANDS
R2,# data R3,# data R4,# data R5,# data R6,# data R7,# data data addr,data addr data addr,@R0 data addr,@R1 data addr,R0 data addr,R1 data addr,R2 data addr,R3 data addr,R4 data addr,R5 data addr,R6 data addr,R7 DPTR,#data bit addr,C C,bit addr A,data addr A,@R0 A,@R1 A,R0 A,R1 A,R2 A,R3 A,R4 A,R5 A,R6 A,R7 data addr,A . @R0,A . @R1,A
HEX COD E
F9 FA FB FC FD FE FF A6 A7 A8 A9 AA AB AC AD AE AF 83 93 E0 E2 E3 F0 F2 F3 A4 . 00 42 43 44 45 46 47 48
NUMBE R OF BYTES
1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 2 3 2 2 1 1 1
MNEM ONIC
MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOVC MOVC MOVX MOVX MOVX MOVX MOVX MOVX MUL NOP ORL ORL ORL ORL ORL ORL ORL
OPERANDS
R1,A R2,A R3,A R4,A R5,A R6,A R7,A . @R0,data addr . @R1,data addr R0, data addr R1,data addr R2,data addr R3,data addr R4,data addr R5,data addr R6,data addr R7,data addr A,@A + PC A,@A+DPTR A,@DPTR A,@R0 A,@R1 . @DPTR,A . @R0,A . @R1,A AB data addr,A data addr,#data A,#data A,Data addr A,@R0 A,@R1 A,R0
DEPT OF ECE
60
HEX COD E
4A 4B 4C 4D 4E 4F 72 A0 D0 C0 22 32 23 33 . 03 13 D2 D3 80 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F C4 C5 C6 C7
NUMBE R OF BYTES
1 1 1 1 1 1 2 2 2 2 1 1 1 1 1 1 2 1 2 2 2 1 1 1 1 1 1 1 1 1 1 1 2 1 1
MNEM ONIC
ORL ORL ORL ORL ORL ORL ORL ORL POP PUSH RET RETI RL RLC RR RRC SETB SETB SJMP SUBB SUBB SUBB SUBB SUBB SUBB SUBB SUBB SUBB SUBB SUBB SUBB SWAP XCH XCH XCH A A A A
OPERANDS
A,R2 A,R3 A,R4 A,R5 A,R6 A,R7 C,bit addr C,/bit addr data addr data addr
HEX COD E
C8 C9 CA CB CC CD CE CF D6 D7 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F A5
NUMBE R OF BYTES
1 1 1 1 1 1 1 1 1 1 2 3 2 2 1 1 1 1 1 1 1 1 1 1
MNEMO NIC
XCH XCH XCH XCH XCH XCH XCH XCH XCHD XCHD XRL XRL XRL XRL XRL XRL XRL XRL XRL XRL XRL XRL XRL XRL
OPERANDS
A,R0 A,R1 A,R2 A,R3 A,R4 A,R5 A,R6 A,R7 A,@R0 A,@R1 data addr,A data addr,# data A,# data A,data addr A,@R0 A,@R1 A,R0 A,R1 A,R2 A,R3 A,R4 A,R5 A,R6 A,R7
bit addr C code addr A,# data A,data addr A,@R0 A,@R1 A,R0 A,R1 A,R2 A,R3 A,R4 A,R5 A,R6 A,R7 A A,data addr A,@R0 A,@R1
RESERVED
DEPT OF ECE
61
DEPT OF ECE
62