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Logic Synthesis With Synopsys Design Compiler: Formal Hardware Verification (COEN7501) (COEN7501) Summer 2010

This document provides an overview of using Synopsys Design Compiler for logic synthesis. It discusses setting up a design environment, analyzing the HDL description, applying area, power, and timing constraints, performing logic synthesis and optimization, and viewing the synthesis report. The goal is to transform the HDL description into an optimized gate-level netlist while meeting constraints.

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0% found this document useful (0 votes)
68 views10 pages

Logic Synthesis With Synopsys Design Compiler: Formal Hardware Verification (COEN7501) (COEN7501) Summer 2010

This document provides an overview of using Synopsys Design Compiler for logic synthesis. It discusses setting up a design environment, analyzing the HDL description, applying area, power, and timing constraints, performing logic synthesis and optimization, and viewing the synthesis report. The goal is to transform the HDL description into an optimized gate-level netlist while meeting constraints.

Uploaded by

starwar127
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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LogicSynthesiswithSynopsys DesignCompiler

FormalHardwareVerification (COEN7501) Summer2010

Synthesis=Faithfultransformationfromonedescriptiontoanother
RTL Gatelevel

HDL Description Translation Intermediate Intermediate Representation

Area,Speed, Power Constraints

Technology Library (Cells)

OptimizationandMapping Optimization and Mapping OptimizedGateLevelNetlist

Setup
Makenewdirectory:mkdir synopsys CopyHDLandsetupfiles:useUNIXcopycommand Sourcetheenvironmentfile:source/CMC/ENVIRONMENT/synopsys.env

HomeDirectory

Synopsys

HDLfiles

WORK

.synopsys_dc.setup y py_ p

design_analyzer &

Schematicand Sy bo e s SymbolViews Moveupand Downthe hierarchy

fm_shell fscriptfile

SymbolicView

AreaandPowerConstraints
Maximumarea Dynamicandleakagepower

Attributes

Optimizationconstraints

Designconstraints

OperatingConditions
Commercial Industrial Military

TimingConstraints
RiseandFallDelaytimes Rise and Fall Delay times

Attributes

Optimizationconstraints

Timingconstraints

LogicSynthesisandOptimization

Tools

Designoptimizations

SynthesisReport

Analysis

Report

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