Logic Synthesis With Synopsys Design Compiler: Formal Hardware Verification (COEN7501) (COEN7501) Summer 2010
Logic Synthesis With Synopsys Design Compiler: Formal Hardware Verification (COEN7501) (COEN7501) Summer 2010
Synthesis=Faithfultransformationfromonedescriptiontoanother
RTL Gatelevel
Setup
Makenewdirectory:mkdir synopsys CopyHDLandsetupfiles:useUNIXcopycommand Sourcetheenvironmentfile:source/CMC/ENVIRONMENT/synopsys.env
HomeDirectory
Synopsys
HDLfiles
WORK
.synopsys_dc.setup y py_ p
design_analyzer &
fm_shell fscriptfile
SymbolicView
AreaandPowerConstraints
Maximumarea Dynamicandleakagepower
Attributes
Optimizationconstraints
Designconstraints
OperatingConditions
Commercial Industrial Military
TimingConstraints
RiseandFallDelaytimes Rise and Fall Delay times
Attributes
Optimizationconstraints
Timingconstraints
LogicSynthesisandOptimization
Tools
Designoptimizations
SynthesisReport
Analysis
Report