Chapter 12 Algorithmic State Machine ___________________________________________

12.0 Introduction
In Chapter 10, we introduced two models of synchronous sequential network, which are Mealy and Moore machines. In this chapter, we would like to introduce another approach of designing synchronous sequential network using flowchart, which is similar to those used in computer programming. This is called algorithmic state machine ASM. Designing using ASM allows handling of more complex system than state diagram shown in earlier chapter.

12.1 Algorithmic State Machine

An approach of digital design is to partition the system into a controller and a controlled architecture also called data processor, which is shown in Fig. 12.1.

Figure 12.1: Partition of digital system

Data processor is a hardware required for data manipulation that may consist of adder, subtractor, shift register, and etc and output the results. In addition to this function, the data processor also provides status of the data manipulation to the controller. The controller, which is also termed as ASM, provides sequence of command to data processor. It is called ASM because it consists of well defined finite number of step to the solution of a process. The external input is used to provide the task required to be carried out by the controller. The input data is used in the manipulation.
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The model of algorithmic state machine ASM is shown in Fig. 12.2. The machine is viewed as the combination of Mealy and Moore machines.

Figure 12.2: Model of Algorithmic State Machine

Next state and memory blocks are similar for both Mealy and Moore machines. Conditional output function block is similar to that of a Mealy machine, whilst state output function block is similar to that of a Moore machine.

12.2 Algorithmic State Machine Chart

The algorithmic state machine SM chart can be divided into three blocks namely the state box, the decision box, and the conditional output box. They are shown in Fig. 12.3.

Figure 12.3: The alogoritmic state machine blocks

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The state box contains an output list, state name, and optional state code. The decision box is a usual diamond shaped symbol with true and false evaluate to decide the branches. The conditional output box contains conditional output list. The conditional outputs depend on both the state of system and the inputs. Lets consider an ASM chart shown in Fig. 12.4 and use it to explain the flow of the sequence.

Figure 12.4: An ASM chart showing the state box, conditional box, and decision box

When state S1 entered, output Y1 and Y2 become 1. If inputs X1 and X2 are both equal to 0, Y3 and Y4 are also 1, and at the end of state time the machine goes to the next state via exit path 1. If inputs X1 = 0 and X2 = 1, Y3 and Y4 are 1, the exit to next state is via path 2. On the other hand, if X1 = 1 and X3 = 0, the output Y5 is 1 and exit to the next state will occur via exit path 3. If X1 = 1 and X3 = 1, the exit to the next state will occur via path 4.
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12.3 Conversion of State Diagram to Algorithmic State Machine Chart

Lets consider the state diagram of a SR flip-flop and see how it is being converted into an ASM chart. From the excitation equation of an SR flip-flop, which is Qn+1 = S + Qn R , the state diagram of a SR flip-flop is derived and shown in Fig. 12.5.

Figure 12.5: State diagram of a SR flip-flop

The simplified form with Boolean expressions is shown in Fig. 12.6.

Figure 12.6: The simplified form of state diagram for SR flip-flop

Based on the state diagram shown in Fig. 12.5, the ASM chart of the SR flipflop is shown in Fig. 12.7. The initial state of the flip-flop is Q = 0, when the decision S R is true, the flip-flop will change state to Q = 1. When it is not true, which shall mean S R = S+ R, it would hold its state at Q = 0. When the decision R is true, the flip-flop will hold its state at Q = 1. When the decision R is not true, which is R is true, the flip-flop will change state to Q = 0.
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Figure 12.7: The ASM chart of SR flip-flop

Lets consider an example of sequential network shown in Fig. 12.8. This sequential network contains both Mealy and Moore outputs. The Mealy output is depending on the present state and input state X. Thus, output Y1 and Y2 should be conditional outputs and they are to be resided in the conditional box. Output Ya, Yb, and Yc are Moore outputs. They do not depend on the state of input X. Thus they should reside in the state box. Input X can be either 0 or 1. Thus, it should be resided in decision box.

Figure 12.8: A state diagram

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The ASM chart of the state diagram shall then be as shown in Fig. 12.9.

Figure 12.9: ASM chart of state diagram shown in Fig. 12.8

After entering to state S0, the output Ya becomes 1. State S0 will change to state S1 only when condition of input X = 1 and output Yb will become 1. If X = 0 then the state remains unchange and output becomes 0. State S1 will change to state S2 only when condition of input X = 1 and output Yc becomes 1. If X = 0 then state S1 will transition back to state S0. Thus, one can see that output Yc is always 1. If X = 1 and Y2 = 1 then the state S2 remains unchanged. If X = 0 and output Y1 = 1, then state changes to S0.
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12.4 Design the Circuit with ASM Chart

The Boolean expression of the outputs shall be determined from the type, the state conditions, and input conditions that used to obtain them. The next state equation for the flip-flop Q shall be obtained from the following procedure. Identify all the states in which Q = 1. For each of these states, find all the link paths that lead into the state. For each of these link paths, find a term that is 1 when the path is followed. That is for a link path from Si to Sj, the term will be 1 if the machine is in state Si and the conditions for exiting to Sj are satisfied. The Boolean expression for next state flip-flop output Q+ is formed by ORing together the states found in above step. We shall use the ASM chart shown in Fig. 12.8 to derive the Boolean expressions for the outputs and next state equations this sequential network. The assignment of the state shall be S0 = A B = 00, S1 = A B = 01, and S2 = A B = 11. Note that A is the MSB, whilst B is LSB. Since the Moore output Ya and Yb are only present state dependent, therefore, the output Ya = A B , Yb = A B and Yc = A B . The Boolean expressions for Mealy output shall be Y1 = A B X and Y2 = A BX . Following the procedure listed above link path 1, 2 and 3 are identified for determining the next state equation for the flip-flop. Lets begin with LSB bit B. Path 1 has B transition from 0 to 1. Thus, the Boolean expression for this transition is A B X . For path 2, B is transition from 1 to 1. Thus, the Boolean expression for this path is A B X . For path 3, B is also transition from 1 to 1. Thus, its Boolean expression is A B X . ORing these Bollean expressions shall form the next state B+ equation for the LSB of the flip-flop. Thus, the next state equation for LSB B is B+ = A BX +A BX +A BX .

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For Path 1, A is transition from 0 to 0, which does not lead to Q = 1. Thus, it is not necessary to obtain the Boolean expression for this path. For path 2, A is transition from 0 to 1. Its Boolean expression shall be A B X . For path 3, A is transition from 1 to 1. Its Boolean expression is A B X . ORing all these Boolean expressions shall form the next state A+ equation for the MSB A of flip-flop. The next state equation for A shall be A+ = A BX +A BX . Now that we have obtained all the necessary Boolean expressions and next state equations. A state table can then be obtained. Deciding the flip-flop type to be used, obtaining next input of flip-flop, using optimization technique to reduce the state, and finally draw the circuit diagram. The design using D flip-flop is shown in Fig. 12.10. Student is encouraged to list the state table from the state equations.

Figure 12.10: The design of the system from ASM chart shown in Fig. 12.9

Lets consider another example of design using ASM chart. A start signal S starts the system by clearing a 4-bit binary counter A (A3, A2, A1, and A0) and flip-flop F. With the next clock pulse the counter is
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incremented. The counter continues to be incremented until the operation stop. The counter bit A3 and A2 are used to control the sequence. If A2 = 0 flip-flop E is cleared and continues counting. If A2 = 1 flip-flop E is set. If A3 = 0 the count continues. If A3 = 1 flip-flop F is set on next clock pulse and the system stop counting. Based on the design statement, the ASM chart for system is shown in Fig. 12.11.

Figure 12.11: ASM chart of the design example

Based on the ASM chart, the flip-flop F and binary counter are reset by Boolean expression B C S , whereby B is the MSB and C is LSB of state. Flip E is set by Boolean expression B C A 2 and reset by Boolean expression B C A 2 .
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Flip-flop F is set by Boolean expression BC. The binary counter is incremented by Boolean expression B C . If JK flip-flops are used as the flip-flop E and F, then the J input of flipflop E is JE = B C A 2 . The K input of flip-flop E is KE = B C A 2 . The J input of flip-flop F is JF =BC. The K input of flip-flop F is KF = B C S . The block diagram of the design is shown in Fig. 12.12.

Figure 12.12: Block diagram of the system design for ASM shown in Fig. 12.11

The sequence circuit is designed based on the procedure listed at the beginning of this section. The next state equation for bit B is B+ = B C A 2 A 3 , which is shown by the red path in Fig. 12.13. There are four paths shown in blue in Fig. 12.13 for the next state equation of bit C. Thus, the next state equation for bit C is C+ = B C S + B C A 2 A 3 + B C A2 A3 + B C A2 . Based on the above results, the next-state and output state table is shown in Fig. 12.14.
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Figure 12.13: The next state paths of ASM shown in Fig. 12.11

Present State S0 S0 S1 S1 S1 S2 X

Present State B C 0 0 0 0 0 1 0 1 0 1 1 1 1 0

Input S 0 1 X X X X X A2 X X 0 1 1 X X A3 X X X 0 1 X X

Next State B+ C+ 0 0 0 1 0 1 0 1 1 1 0 0 X X

Ouput JE 0 0 0 1 1 0 X KE JF KF 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 1 0 X X X

Figure 12.14: The next-state and output state table

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If the sequencer circuit is designed using D-flip flop then the input DC of flipflop C shall be DC = B C S + B C A 2 A 3 + B C A 2 A 3 + B C A 2 = B C S + B C and for input DB of flip-flop B shall be DB = B C A 2 A 3 . The state 10 is a dont care state, the state table of output S0, S1 and S2 are shown in Fig. 12.15. Input B 0 0 1 1 C 0 1 0 1 S0 1 0 X 0 Output S1 0 1 X 0

S2 0 0 X 1

Figure 12.15: State table of output S0, S1, and S2

Based on the state table shown in Fig. 12.15, the Boolean expressions for S0, S1, and S2 are respectively equal to S0 = C , S1 = B C , and S2 = B. The design of the sequencer circuit shall then be as shown in Fig. 12.16.

Figure 12.16: The circuit design of sequencer circuit

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Replacing the sequencer circuit shown in Fig. 12.12 with the circuit shown in Fig. 12.16 would complete the design of the system as specified by the ASM chart shown in Fig 12.11.

Tutorials
12.1. Draw an ASM chart for a JK flip-flop. 12.2. Use the ASM chart to derive the Boolean expression for output Y1.

12.3. Draw the ASM chart based on this state diagram and implement this machine using D flip-flop.

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12.4. Convert the ASM chart shown below into state diagram

12.5. Using the ASM chart shown in Fig. 12.9 to design the circuit using D flip-flop. 12.6. Derive the Boolean expressions of the output and next state equations for the machine with ASM chart shown below. Also draw the state table and design for the machine if D flip-flop is chosen for the design.

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12.7. Using the ASM chart shown in Fig. 12.11, draw the state diagram of sequencer.

References
1. Charles H. Roth, Jr., Fundamentals of Logic Design, Third Edition West Publishing Company 1985. 2. Randy H. Katz, Contemporary Logic Design, The Benjamin/Cumming Publishing Company Inc. 1994. 3. Alan B. Marcovitz, Introduction to Logic Design, McGraw- Hill 2002.

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