Verilog HDL

Verilog is a concurrent programming language unlike C, which is sequential in nature. initial block - executes once at time 0. If there is more then one block, each execute concurrently always block executes continuously Modeling Levels Switch-Level, Gate-Level, Dataflow, Behavioral Assignments Blocking assignment: = executed in order they appear in a block Nonblocking assignment: <= allow scheduling of assignments without blocking execution of statements that follow in a sequential block Continuous assignment assign A = B; connects nets permanently. Example 1: #10 A = 1b1; counter = 0; Example 2: A <= #10 1b1; counter <= 0;

//executed at 10 (after A assignment)

// executed at time 0 (before A assignment)

Sequential Black begin-end Parallel Blocks fork-join Module definition: module <module_name> (<module_terminal_list>); <module_terminal_definitions> <functionality_of_module> endmodule // semicolon required!!!

// no semicolon!!!

Gate-Level Modeling
Example 1: Full Adder
module FullAdder(X, Y, Cin, Cout, Sum); input X, Y, Cin; // input terminal definitions output Cout, Sum; // output terminal definitions wire w1, w2, w3, w4; xor #(10) (w1, X, Y); xor #(10) xor2(Sum, w1, Cin); and and and #(10) (w2, X, Y); #(10) (w3, X, Cin); #(10) (w4, Y, Cin); // internal net declarations // delay time of 10 units // with instance name

or #(10, 8)(Cout, w2, w3, w4); endmodule

// 3 input or (rise time of 10, fall // time of 8)

Example 2: 4-bit Full Adder

module Adder4(A, B, Cin, S, Cout); input[3:0] A, B; input Cin; output[3:0] S; output Cout; wire c1, c2, c3; // 4 instantiated 1-bit Full Adders FullAdder fa0(A[0], B[0], Cin, C1, sum[0]); FullAdder fa1(A[1], B[1], C1, C2, sum[1]); FullAdder fa2(A[2], B[2], C2, C3, sum[2]); FullAdder fa3(A[3], B[3], C3, Cout, sum[3]); endmodule

Example 3: Stimulus Module for 4-bit Full Adder

module stimulus; // declare variables reg[3:0] A, B; reg C_IN; wire [3:0] SUM; wire C_OUT; //Instantiate 4-bit Full Adder Adder4 FA1(A, B, C_IN, SUM, C_OUT); initial begin $monitor($time, A=%b B=%b Cin=%b, C_OUT); end // stimulate inputs initial begin A = 4d0; B = 4d0, C_IN = 1b0; #10 A = 4d2; B=4d2; #10 A = 4d5; B=4d8; #10 C_IN = 1b1 end endmodule

-> Sum = %b Cout=%b\n, A, B, C_IN, SUM,

// // // // //

sequential block begins 0 + 0 + 0 2 + 2 + 0 5 + 8 + 0 5 + 8 + 1

Dataflow Modeling
Example 4: 4-to-1 Multiplexer
module mux4_to_1(in, out, sel); input [3:0] in; output out; input [1:0]sel;

// continuous assignment with delay assign #10 out = (~sel[1] & ~sel[0] (~sel[1] & sel[0] ( sel[1] & ~sel[0] ( sel[1] & sel[0] endmodule

& & & &

in[0]) | in[1]) | in[2]) | in[3]);

Example 5: 4-bit Full Adder with dataflow operators

module Adder4(A, B, Cin, S, Cout); input[3:0] A, B; input Cin; output[3:0] S; output Cout; assign {Cout, S} = A + B + Cin; endmodule // concatenation

Behavioral Modeling
All behavioral statements must be in initial or always blocks Example 6: Clock Generator
module ClkGen; reg clk; initial clk = 1b0; always #10 clk = ~clk; initial #1000 $finish; endmodule //or $stop to end simulation

Example 7: Behavioral 4-to-1 Multiplexer

module mux4_to_1(in, out, sel); input [3:0] in; output out; input [1:0]sel; reg out; always @(sel or begin case(sel) 2b00: out = 2b01: out = 2b10: out = 2b11: out = default: out endcase end endmodule in) in[0]; in[1]; in[2]; in[3]; = 1bx;

Example 8: D-Type Latch

module Latch(D, C, Q) input D, C; output Q; reg Q; // output must preserve values initial Q = 1b0; always @(C or D) begin if(C == 1'b1) #10 Q = D; end endmodule

Example 9: D-type Flip-Flop (with clear and set inputs)

module DFF(D, C, Q, QN, CLRN, SETN) input D, C, CLRN, SETN; output Q, QN; reg Q, QN; // output must preserve values initial begin Q = 1b0; QN = 1b1; end always @(negedge CLRN or negedge SETN or posedge C) begin if(CLRN == 1b0) begin #10 Q = 1b0; QN = 1b1; end else if(SETN == 1b0) begin #10 Q = 1b1; QN = 1b0; end else begin #10 Q = D; QN = ~D; end end endmodule

Example 10: Ripple-Carry Counter (with active high reset) 4-bit Ripple-carry counter. Instantiates 4 negative edge triggered T-flipflops from D-flipflop
module RCC(Q, CLK, RESET); output [3:0]Q; input CLK, RESET;

TFF tff0(Q[0], TFF tff1(Q[1], TFF tff2(Q[2], TFF tff3(Q[3], endmodule

CLK, Q[0], Q[1], Q[2],

!RESET); !RESET); !RESET); !RESET);

module TFF(Q, CLK, RESET); output Q; input CLK, RESET; wire D, QN; DFF dff(D, !CLK, Q, QN, RESET, 1b1); assign D = QN; endmodule

Example 11: 7-segment LCD Display Driver (for non-multiplexed LCDs)

define define define define define define define define define define define DSP0 7b1111110; DSP1 7b0110000; DSP2 7b1101101; DSP3 7b1111001; DSP4 7b0110011; DSP5 7b1011011; DSP6 7b1011111; DSP7 7b1110010; DSP8 7b1111111; DSP9 7b1111011; BLANK 7b0000000;

module LCD_DRV(DATA, CLK, SEGMENTS, COM); input [3:0] DATA; // BCD input input CLK; // 60-100Hz clock input output [6:0] SEGMENTS; // LCD A-G segment lines output COM; // LCD COM line always @(DATA or CLK) begin assign COM = CLK; case (DATA) 4b0000: if(CLK == 1b0) SEGMENTS = DSP0; else SEGMENTS = DSP0 ^ 4b0001: if(CLK == 1b0) SEGMENTS = DSP1; else SEGMENTS = DSP1 ^ 4b0010: if(CLK == 1b0) SEGMENTS = DSP2; else SEGMENTS = DSP2 ^ 4b0011: if(CLK == 1b0) SEGMENTS = DSP3; else SEGMENTS = DSP3 ^ 4b0100: if(CLK == 1b0) SEGMENTS = DSP4; else SEGMENTS = DSP4 ^ 4b0101: if(CLK == 1b0) SEGMENTS = DSP5; else SEGMENTS = DSP5 ^ 4b0110: if(CLK == 1b0)

7b1111111;

7b1111111;

7b1111111;

7b1111111;

7b1111111;

7b1111111;

4b0111:

4b1000:

4b1001:

default:

endcase end endmodule

SEGMENTS = DSP6; else SEGMENTS = DSP6 ^ 7b1111111; if(CLK == 1b0) SEGMENTS = DSP7; else SEGMENTS = DSP7 ^ 7b1111111; if(CLK == 1b0) SEGMENTS = DSP8; else SEGMENTS = DSP8 ^ 7b1111111; if(CLK == 1b0) SEGMENTS = DSP9; else SEGMENTS = DSP9 ^ 7b1111111; if(CLK == 1b0) SEGMENTS = BLANK; else SEGMENTS = BLANK ^ 7b1111111;

Example 12: State Machine Two roads intersect: the highway and the country road. On the highway the green light is always on unless the sensor on the country road detects a car. The green light on the country road stays on until all cars leave that road. Model the traffic lights there. Set 3 clock cycle delay for yellow to red signal change and 2 for red to green for both directions. S0 Highway = Green, Country = Red S1 Highway = Yellow, Country = Red S2 Highway = Red, Country = Red S3 Highway = Red, Country = Green S4 Highway = Red, Country = Yellow
define RED 2d0 define YELLOW 2d1 define GREEN 2d2 define define define define define S0 S1 S2 S3 S4 3d0 3d1 3d2 3d3 3d4

// delays in clock cycles define Y2RDELAY 3 define R2GDELAY 2 module sig_control(highway_signal, country_signal, sensor, clock) output [1:0] highway_signal, country_signal; reg [1:0] highway_signal, country_signal; input sensor, clock; reg[2:0] state, nextstate; initial begin state = S0; nextstate = S0; highway_signal = GREEN; country_signal = RED;

end always @(posedge clock) state = nextstate; always @(state) begin case (state) S0: begin highway_signal country_signal end S1: begin highway_signal country_signal end S2: begin highway_signal country_signal end S3: begin highway_signal country_signal end S4: begin highway_signal country_signal end endcase end

= GREEN; = RED; = YELLOW; = RED; = RED; = RED; = RED; = GREEN; = RED; = YELLOW;

always @(state or sensor) begin case(state) S0: if(sensor) nextstate = S1; else nextstate = S0; S1: begin repeat(Y2RDELAY) @(posedge clock) nextstate = S2; end S2: begin repeat(R2GDELAY) @(posedge clock) nextstate = S3; end S3: if(sensor) nextstate = S3; else nextstate = S4; S4: begin repeat(Y2RDELAY) @(posedge clock) nextstate = S0; end default: nextstate = S0; endcase end endmodule

Example 13: Left/Right Shifter Using Verilog Functions

module shifter; define LEFT_SHIFT 1b0; define RIGHT_SHIFT 1b1; reg [31:0] addr, left_addr, right_addr; reg control; always @(addr)

begin left_addr = shift(addr, LEFT_SHIFT); right_addr = shift(addr, RIGHT_SHIFT); end // Define the shift function. The output is a 32-bit value function [31:0] shift; input [31:0] address; input control; begin shift = (control == LEFT_SHIFT) ? (address << 1) : (address >> 1); end endfunction endmodule

Example 14: Bitwise Operator Using Verilog Tasks

module operation; parameter delay = 10; reg[15:0] A, B; reg[15:0] AB_AND, AB_OR, AB_XOR; always @(A or B) begin bitwise_oper(AB_AND, AB_OR, AB_XOR, A, B); end taks bitwise_oper; output [15:0] ab_and, ab_or, ab_xor; input [15:0] a, b begin #delay ab_and = a & b; ab_or = a | b; ab_xor = a ^ b; end endtask endmodule

Switch-Level Modeling
Example 15: 2-to-1 Multiplexer
module mux(out, in, sel); output out; input[1:0]in; input sel; wire sel_b; //declare power and ground supply1 pwr; supply2 gnd; // implement the NOT gate pmos(sel_b, pwr, sel); nmos(sel_b, gnd, sel); // implement 2 pass gate switch gates cmos(out, in[0], sel_b, sel); cmos(out, in[1], sel, sel_b); endmodule