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Dec 07

This document outlines the topics and questions for a revised 3 hour course with a total of 100 marks. It includes questions on binary, octal and hexadecimal conversion; Boolean algebra minimization; logic gates; K-maps; Quine-McCluskey method; multiplexers; full adders; counters; shift registers; programmable devices; CMOS logic; and basic digital concepts like fanout, noise margin, Gray code, and T/D flip-flops. Students must attempt one compulsory question and four out of the remaining six questions.

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39 views1 page

Dec 07

This document outlines the topics and questions for a revised 3 hour course with a total of 100 marks. It includes questions on binary, octal and hexadecimal conversion; Boolean algebra minimization; logic gates; K-maps; Quine-McCluskey method; multiplexers; full adders; counters; shift registers; programmable devices; CMOS logic; and basic digital concepts like fanout, noise margin, Gray code, and T/D flip-flops. Students must attempt one compulsory question and four out of the remaining six questions.

Uploaded by

abhitillu
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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: ) Question 1 is compulsory. No. I t A t t e m pa n yf o u r q u e s t i o no u t o f r e m a i n i ns i x q u e s t i o n s . t s g r) Figuresto the right indicate marks. full Convert following number intoBinary, Octaland Hexadecimal number system: (38.26)10. Minimize following Boolean expression usingBoolean laws :

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A B C+ A B e + A B C + A B C + A B C
Pe rfo rm l l o w i n g p e rations fo o : - (101 00)2 ( i ) ( 11 0 0 1 ) z 1 1 ( i i ) ( 1 0 1 O O ) e ( 11 0 0 1 ) 2 1 1 Re a l i seA N D , OR , N OT,XOR logic using NAND gates only. Mi n i mi ze l l o w i n g xp ression fo e using K*map BC + AB + ABC + ABCD + ABCD +ABCD. M i n i mi ze l l o w i n g xp r essing fo e using Quine McOluskey ethod : m f ( A ,B , C , D ) = I m ( 0 , 2 , 9 , G , 7 , B , 1 0 , 1 2 , 1 3 ) .
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Re a l i sefo l l o w i n gl o g i c using 8 : 1 m ultiplexer : f ( A , B , C , D ) = I m ( 2 , 4 , 6 , 7 , g , 1 0 , 11, 1 2 , 1 5 ) De si g na fu l l a d d e r u si ng K map and r ealiseit using suitablegates.

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D e si g na 4 b i t a syn ch ronous counterusing J- K flip- flop. aw the wavefor m s . Dr 8 D e si g na syn ch ro n o u d ecadecounterusingJ- K flip- flop. s Explainits wo r k i ngw i th 12 neat waveforms. W h a t a re se q u e n ti aci rcuits? How do they differfr om com binational i r c ui ts? l c Ho w a re co u n te rs a ssified W hat ar e salientfeatur es each type of c ounter? cl ? of W h a t a re sh i ft re g i ste rs How ar e they classified Explainwor kingof any one ? ? type of shift register. 5 5 10

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Whatare programmable devices How are they classified Explain logic ? ? with 1 0 an example process realisation anycombinational the of of circuit thesedevices. in Discuss salient features, advantages limitations CMOSlogicfamily. and of 10 : e s h o r tn o t e s n : o a) Fanout of digital lC p) Noise argin M : Graycodeand its applications : T and D typeflip-flop. 20

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