y x m0 m1 0 0 xy

y 1 xy

m2 (a)

m3

xy (b)

xy

Fig. 3-1 Two-variable Map

2002 Prentice Hall, Inc. M. Morris Mano DIGITAL DESIGN, 3e.

y x 0 0

y 1 x 0

y 0

y 1 1

1 (a)

1 xy

x 1

1 (b) x

1 y

Fig. 3-2 Representation of Functions in the Map

2002 Prentice Hall, Inc. M. Morris Mano DIGITAL DESIGN, 3e.

xz x m0 m4 m1 m5 m3 m7 m2 m6 00 0 xyz 01 xyz 11 x yz

y 10 x yz

xy z

xy z

xyz

xyz

z (a) Fig. 3-3 Three-variable Map (b)

2002 Prentice Hall, Inc. M. Morris Mano DIGITAL DESIGN, 3e.

x 0 x 1

yz 00

y 01 11 1 10 1

1 z

Fig. 3-4 Map for Example 3-1; F(x, y, z) = (2, 3, 4, 5) = x y

xy

2002 Prentice Hall, Inc. M. Morris Mano DIGITAL DESIGN, 3e.

x 0 x 1

yz 00

y 01 11 1 10

1 z

Fig. 3-5 Map for Example 3-2; F(x, y, z)

(3, 4, 6, 7)

yz

xz

2002 Prentice Hall, Inc. M. Morris Mano DIGITAL DESIGN, 3e.

x 0 x 1

yz 00 1

y 01 11 10 1

1 z

Fig. 3-6 Map for Example 3-3; F(x, y, z)

(0, 2, 4, 5, 6)

xy

2002 Prentice Hall, Inc. M. Morris Mano DIGITAL DESIGN, 3e.

BC A 00 0 A 1

B 01 1 11 1 10 1

C Fig. 3-7 Map for Example 3-4; A C AB AB C BC C AB

2002 Prentice Hall, Inc. M. Morris Mano DIGITAL DESIGN, 3e.

wx

yz 00

y 01 11 10

00 w x y z w x y z w x yz w x yz m0 m4 m 12 m8 m1 m5 m 13 m9 (a) Fig. 3-8 Four-variable Map m3 m7 m 15 m 11 m2 01 w xy z m6 11 wxy z m 14 m 10 z (b) w 10 wx y z wx y z wx yz wx yz wxy z wxyz wxyz w xy z w xyz w xyz x

2002 Prentice Hall, Inc. M. Morris Mano DIGITAL DESIGN, 3e.

wx 00 01

yz 00 1 1 1 1

y 01 1 1 1 1 z 11 10 1 1 x

11 w 10

Fig. 3-9 Map for Example 3-5; F(w, x, y, z) (0, 1, 2, 4, 5, 6, 8, 9, 12, 13, 14)

wz

xz

2002 Prentice Hall, Inc. M. Morris Mano DIGITAL DESIGN, 3e.

AB 00 01

CD 00 1

C 01 1 11 10 1 1 B

11 A 10 1 1 D Fig.3-10 Map for Example 3-6; A B C B CD AB C BD BC A CD A BCD 1

2002 Prentice Hall, Inc. M. Morris Mano DIGITAL DESIGN, 3e.

AB 00 01

CD 00 1

C 01 11 10 1 1 1 1 B 1 A 1 AB 00 01

CD 00 1

C 01 11 1 1 1 1 B 1 1 1 10 1

11 A 10 1

11 10 1

D (a) Essential prime implicants BD and B D

D (b) Prime implicants CD, B C AD, and AB

Fig. 3-11 Simplification Using Prime Implicants

2002 Prentice Hall, Inc. M. Morris Mano DIGITAL DESIGN, 3e.

A DE 00 0 4 12 8

0 D DE 00 16 20 28 24

1 D

BC 00 01 11 B 10

01 1 5 13 9 E

11 3 7 15 11

10 2 6 C 14 B 10

BC 00 01 11 10

01 17 21 29 25 E

11 19 23 31 27

10 18 22 C 30 26

Fig. 3-12 Five-variable Map

2002 Prentice Hall, Inc. M. Morris Mano DIGITAL DESIGN, 3e.

A DE 00 1 1 1

0 D DE 00

1 D

BC 00 01 11 B 10

01

11

10 1 1 C

BC 00 01 11 B 10

01

11

10

1 1 1 E BD E ACE

1 C 1

1 E

Fig. 3-13 Map for Example 3-7; F = A B E

2002 Prentice Hall, Inc. M. Morris Mano DIGITAL DESIGN, 3e.

AB 00 01

CD 00 1 0 0 1

C 01 1 1 0 1 D 11 0 0 0 0 10 1 0 B 0 1

11 A 10

Fig. 3-14 Map for Example 3-8; F (A ,B ,C ,D) (0, 1, 2, 5, 8, 9, 10) B D + B C + A C D = (A + B )(C + D )(B + D)

2002 Prentice Hall, Inc. M. Morris Mano DIGITAL DESIGN, 3e.

B D

A B

C D

A D (a) F BD BC ACD

D (b) F (A B ) (C D ) (B D)

Fig. 3-15 Gate Implementation of the Function of Example 3-8

2002 Prentice Hall, Inc. M. Morris Mano DIGITAL DESIGN, 3e.

x 0 x 1

yz 00 0 1

y 01 1 0 z 11 1 0 10 0 1

Fig. 3-16 Map for the Function of Table 3-2

2002 Prentice Hall, Inc. M. Morris Mano DIGITAL DESIGN, 3e.

wx 00 01

yz 00 X 0 0 0

y 01 1 X 0 0 z (a) F yz wx 11 1 1 1 1 10 X 0 x 0 w 0 wx 00 01

yz 00 X 0 0 0

y 01 1 X 0 0 z (a) F yz wz 11 1 1 1 1 10 X 0 x 0 0

11 w 10

11 10

Fig. 3-17 Example with dont-care Conditions

2002 Prentice Hall, Inc. M. Morris Mano DIGITAL DESIGN, 3e.

Inverter x x AND y

xy

x OR y Fig. 3-18 Logic Operations with NAND Gates (x y ) x y

2002 Prentice Hall, Inc. M. Morris Mano DIGITAL DESIGN, 3e.

x y z (a) ANDinvert

(xyz)

x y z

(xyz)

(b) InvertOR

Fig. 3-19 Two Graphic Symbols for NAND Gate

2002 Prentice Hall, Inc. M. Morris Mano DIGITAL DESIGN, 3e.

A B F C D (a) A B

A B F C D (b)

F C D (c) Fig. 3-20 Three Ways to Implement F AB CD

2002 Prentice Hall, Inc. M. Morris Mano DIGITAL DESIGN, 3e.

x 0 x 1

yz 00

y 01 1 11 1 1 z (a) 10 1 F xy xy z

x y x y z (b) F

x y x y z (c) Fig. 3-21 Solution to Example 3-10 F

2002 Prentice Hall, Inc. M. Morris Mano DIGITAL DESIGN, 3e.

C D B A B C (a) AND-OR gates F

C D B A B C (a) NAND gates Fig. 3-22 Implementing F 2002 Prentice Hall, Inc. M. Morris Mano DIGITAL DESIGN, 3e. A(CD B) BC F

A B A B C D (a) AND-OR gates F

A B A B C D (b) NAND gates 2002 Prentice Hall, Inc. M. Morris Mano DIGITAL DESIGN, 3e. Fig. 3-23 Implementing F (AB A B)(C D ) F

Inverter x x y

OR

x AND y Fig. 3-24 Logic Operations with NOR Gates (x y) xy

2002 Prentice Hall, Inc. M. Morris Mano DIGITAL DESIGN, 3e.

x y z

(x

z)

x y z

xyz

(x

z)

(a) ORinvert

(a) InvertAND

Fig. 3-25 Two Graphic Symbols for NOR Gate

2002 Prentice Hall, Inc. M. Morris Mano DIGITAL DESIGN, 3e.

A B C D E Fig. 3-26 Implementing F (A B)(C D)E

2002 Prentice Hall, Inc. M. Morris Mano DIGITAL DESIGN, 3e.

A B A B C D Fig. 3-27 Implementing F (AB A B)(C D ) with NOR Gates F

2002 Prentice Hall, Inc. M. Morris Mano DIGITAL DESIGN, 3e.

A B F C D (a) Wired-AND in open-collector TTL NAND gates. (AND-OR-INVERT) (AB CD)

A B F C D (b) Wired-OR in ECL gates (OR-AND-INVERT) Fig. 3-28 Wired Logic [(A B) (C D)]

2002 Prentice Hall, Inc. M. Morris Mano DIGITAL DESIGN, 3e.

A B C D

A B C F D

E (a) AND-NOR A B C D

E (b) AND-NOR

E (c) NAND-AND Fig. 3-29 AND-OR-INVERT Circuits; F (AB CD E)

2002 Prentice Hall, Inc. M. Morris Mano DIGITAL DESIGN, 3e.

A B

A B

C D F

C D F

E (a) OR-NAND A B

E (b) OR-NAND

C D F

E (c) NOR-OR 2002 Prentice Hall, Inc. M. Morris Mano DIGITAL DESIGN, 3e. Fig. 3-30 OR-AND-INVERT Circuits; F [(A B)(C D)E]

yz x 00 0 1 x 1 0

y 01 0 0 11 0 0 0 1 10 F F xyz xyz x y xy z

z (a) Map simplification in sum of products. x y x y z AND-NOR (b) F x y z x y z OR-NAND 2002 Prentice Hall, Inc. M. Morris Mano DIGITAL DESIGN, 3e. (c) F [(x y z) (x y F (x y xy x y z x y z NOR-OR z)] F x y x y z NAND-AND z) F

Fig. 3-31 Other Two-level Implementations

xy

y (a) With AND-OR-NOT gates

xy

y (b) With NAND gates Fig. 3-32 Exclusive-OR Implementations 2002 Prentice Hall, Inc. M. Morris Mano DIGITAL DESIGN, 3e.

A 0 A 1

BC 00

B 01 1 11 10 1 1 C (a) Odd function F ABC A A 0 1

BC 00 1

B 01 11 1 1 C 1 10

(a) Even function F (A  B  C)

Fig. 3-33 Map for a Three-variable Exclusive-OR Function

2002 Prentice Hall, Inc. M. Morris Mano DIGITAL DESIGN, 3e.

A B C

A B C

(a) 3-input odd function

(b) 3-input even function

Fig. 3-34 Logic Diagram of Odd and Even Functions

2002 Prentice Hall, Inc. M. Morris Mano DIGITAL DESIGN, 3e.

AB 00 01

CD 00

C 01 1 11 10 1 1 B 1 1 A 1 D AB 00 01

CD 00 1

C 01 11 1 1 1 B 1 1 D 1 10

11 A 10 1

11 10

(a) Odd function F ABCD

(b) Even function F (A  B  C  D)

Fig. 3-35 Map for a Four-variable Exclusive-OR Function

2002 Prentice Hall, Inc. M. Morris Mano DIGITAL DESIGN, 3e.

x x y z P y C z P

(a) 3-bit even parity generator

(a) 4-bit even parity checker

Fig. 3-36 Logic Diagram of a Parity Generator and Checker

2002 Prentice Hall, Inc. M. Morris Mano DIGITAL DESIGN, 3e.

A B

g1

e g3 x

g2 Fig. 3-37 Circuit to Demonstrate HDL

2002 Prentice Hall, Inc. M. Morris Mano DIGITAL DESIGN, 3e.

0ns stimcrct.A stimcrct.B stimcrct.C stimcrct.x stimcrct.y

20ns

40ns

60ns

80ns

100ns

120ns

140ns

160ns

180ns

Fig. 3-38 Simulation Output of HDL Example 3-3

2002 Prentice Hall, Inc. M. Morris Mano DIGITAL DESIGN, 3e.