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Computer Concepts

Simultaneous multithreading allows multiple threads to issue instructions each cycle enabling multithreaded applications to execute threads in parallel on a single multi-core processor instead of processing threads sequentially. Superscalar describes a microprocessor design that allows more than one instruction to be executed per clock cycle by determining if instructions can be executed independently or must be executed in sequence. Macro-op fusion increases processor performance and reduces power usage by combining common instruction pairs into a single instruction.

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48 views

Computer Concepts

Simultaneous multithreading allows multiple threads to issue instructions each cycle enabling multithreaded applications to execute threads in parallel on a single multi-core processor instead of processing threads sequentially. Superscalar describes a microprocessor design that allows more than one instruction to be executed per clock cycle by determining if instructions can be executed independently or must be executed in sequence. Macro-op fusion increases processor performance and reduces power usage by combining common instruction pairs into a single instruction.

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hwa890
Copyright
© Attribution Non-Commercial (BY-NC)
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Download as DOC, PDF, TXT or read online on Scribd
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COMPUTER DEFINITIONS Simultaneous Multithreading

Last modified: Tuesday, October 16, 2007

Abbreviated as SMT, simultaneous multithreading is a processor design technology that allows multiple threads to issue instructions each cycle. Simultaneous multithreading enables multithreaded applications to execute threads in parallel on a single multi-core processor instead of processing threads in a linear fashion.

Superscalar
A design that enables a central processing unit to send several instructions to different execution units simultaneously, allowing it to execute several instructions in each clock cycle. Superscalar describes a microprocessor design that makes it possible for more than one instruction at a time to be executed during a single clock cycle . In a superscalar design, the processor or the instruction compiler is able to determine whether an instruction can be carried out independently of other sequential instructions, or whether it has a dependency on another instruction and must be executed in sequence with it. The processor then uses multiple execution units to simultaneously carry out two or more independent instructions at a time. Macro-Op Fusion With the Core microarchitecture the new chips will also be able to combine separate large instructions that usually appear in pairs into a single instruction. This is known as macro-ops fusion. This increases performance, but also reduces the amount of power used by the chip. PCI-E Lanes Each lane of a PCI Express connection contains two pairs of wires -- one to send and one to receive. Packets of data move across the lane at a rate of one bit per cycle. A x1 connection, the smallest PCIe connection, has one lane made up of four wires. It carries one bit per cycle in each direction. A x2 link contains eight wires and transmits two bits at once, a x4 link transmits four bits, and so on. Other configurations are x12, x16 and x32.

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