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Fundamentals of HDL

The document outlines a course on fundamentals of hardware description languages (HDL). The course covers 8 units over 52 hours including introductions to HDL, data flow and behavioral descriptions, structural descriptions, procedures and functions, mixed type and language descriptions, and synthesis basics. The course aims to provide common fundamentals of HDL that are applicable to various domains including electronics, telecommunications, information technology, business management, and machine learning.

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3K views1 page

Fundamentals of HDL

The document outlines a course on fundamentals of hardware description languages (HDL). The course covers 8 units over 52 hours including introductions to HDL, data flow and behavioral descriptions, structural descriptions, procedures and functions, mixed type and language descriptions, and synthesis basics. The course aims to provide common fundamentals of HDL that are applicable to various domains including electronics, telecommunications, information technology, business management, and machine learning.

Uploaded by

DINESH
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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FUNDAMENTALS OF HDL

(Common to EC/TC/IT/BM/ML) Sub Code : 10EC45 Hrs/ Week : 04 Total Hrs. : 52 IA Marks : 25 Exam Hours : 03 Exam Marks : 100

UNIT 1: Introduction: Why HDL? , A Brief History of HDL, Structure of HDL Module, Operators, Data types, Types of Descriptions, simulation and synthesis, Brief comparison of VHDL and Verilog 7 Hrs UNIT 2: Data Flow Descriptions: Highlights of Data-Flow Descriptions, Structure of DataFlow Description, Data Type Vectors. 6 Hrs UNIT 3: Behavioral Descriptions: Behavioral Description highlights, structure of HDL behavioral Description, The VHDL variable Assignment Statement, sequential statements. 6 Hrs UNIT 4: Structural Descriptions: Highlights of structural Description, Organization of the structural Descriptions, Binding, state Machines, Generate, Generic, and Parameter statements. 7 Hrs UNIT 5: Procedures, Tasks, and Functions: Highlights of Procedures, tasks, and Functions, Procedures and tasks, Functions. Advanced HDL Descriptions: File Processing, Examples of File Processing 7 Hrs UNIT 6: Mixed Type Descriptions: Why Mixed-Type Description? VHDL User-Defined Types, VHDL Packages, Mixed-Type Description examples 6 Hrs UNIT 7: Mixed Language Descriptions: Highlights of Mixed-Language Description, How to invoke One language from the Other, Mixed-language Description Examples, Limitations of Mixed-Language description. 7 Hrs UNIT 8: Synthesis Basics: Highlights of Synthesis, Synthesis information from Entity and Module, Mapping Process and Always in the Hardware Domain. 6 Hrs
TEXT BOOKS: 1. HDL Programming (VHDL and Verilog)-Nazeih M.Botros-John Weily India Pvt. Ltd. 2008. REFERENCE BOOKS: 1 Fundamentals of HDL Cyril P.R. Pearson/Sanguin 2010. 2 VHDL -Douglas perry-Tata McGraw-Hill 3 A Verilog HDL Primer-J.Bhaskar BS Publications 4 Circuit Design with VHDL-Volnei A.Pedroni-PHI

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