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Stick Diagrams and Layouts

The document describes various memory cell layouts including: 1) A 6T-SRAM layout with transistors arranged in two cross-coupled inverters. 2) A 3T-DRAM layout with a transistor and two pass gates connected to a bitline and wordline. 3) Read-only memory cells including a diode-based ROM, and MOS-based ROM, OR ROM, and NOR ROM configurations using transistors, wordlines, and bitlines. 4) Layouts of MOS NOR ROM, NAND ROM, and NOR2 and NAND2 gate cells with dimensions and layers used for programming.

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Ashish Verma
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582 views19 pages

Stick Diagrams and Layouts

The document describes various memory cell layouts including: 1) A 6T-SRAM layout with transistors arranged in two cross-coupled inverters. 2) A 3T-DRAM layout with a transistor and two pass gates connected to a bitline and wordline. 3) Read-only memory cells including a diode-based ROM, and MOS-based ROM, OR ROM, and NOR ROM configurations using transistors, wordlines, and bitlines. 4) Layouts of MOS NOR ROM, NAND ROM, and NOR2 and NAND2 gate cells with dimensions and layers used for programming.

Uploaded by

Ashish Verma
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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6T-SRAM Layout

VDD
M2 M4

Q
M1 M3

GND
M5 M6

WL

BL

BL

3T-DRAM Layout
BL2 BL1 GND RWL
M3 M2

WWL
M1

Read-Only Memory Cells


BL VDD WL WL BL WL BL

BL WL WL

BL WL

BL

GND Diode ROM MOS ROM 1 MOS ROM 2

MOS OR ROM
BL [0] BL [1] BL [2] BL [3]

WL [0]
V DD WL [1]

WL [2]
V DD WL [3]

V bias Pull-down loads

MOS NOR ROM


V DD Pull-up devices

WL [0]
GND WL [1]

WL [2] GND WL [3]

BL [0]

BL [1]

BL [2]

BL [3]

MOS NOR ROM Layout


Cell (9.5l x 7l)

Programmming using the Active Layer Only

Polysilicon Metal1 Diffusion Metal1 on Diffusion

MOS NOR ROM Layout


Cell (11l x 7l)

Programmming using the Contact Layer Only

Polysilicon Metal1 Diffusion Metal1 on Diffusion

MOS NAND ROM


V DD Pull-up devices BL [0] WL [0] BL [1] BL [2] BL [3]

WL [1]

WL [2]

WL [3]

All word lines high by default with exception of selected row

MOS NAND ROM Layout


Cell (8l x 7l)

Programmming using the Metal-1 Layer Only


No contact to VDD or GND necessary; drastically reduced cell size Loss in performance compared to NOR ROM

Polysilicon Diffusion Metal1 on Diffusion

NAND ROM Layout


Cell (5l x 6l)

Programmming using Implants Only

Polysilicon Threshold-altering implant Metal1 on Diffusion

CMOS NOR2 GATE LAYOUT

CMOS NAND2 GATE LAYOUT

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