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VLSI Design

1. The document is an exam for a VLSI Design course covering topics like CMOS device characteristics, logic gates, multiplexers, PLA, FPGA and VHDL modeling. 2. It contains two sections - Part A with 10 short answer questions worth 2 marks each and Part B with 5 long answer questions worth 16 marks each. 3. The questions cover concepts like enhancement and depletion NMOS, CMOS inverter design, dynamic CMOS circuits, charge sharing problems, counter design using PLA, FPGA architecture and VHDL modeling of sequential circuits.

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59 views1 page

VLSI Design

1. The document is an exam for a VLSI Design course covering topics like CMOS device characteristics, logic gates, multiplexers, PLA, FPGA and VHDL modeling. 2. It contains two sections - Part A with 10 short answer questions worth 2 marks each and Part B with 5 long answer questions worth 16 marks each. 3. The questions cover concepts like enhancement and depletion NMOS, CMOS inverter design, dynamic CMOS circuits, charge sharing problems, counter design using PLA, FPGA architecture and VHDL modeling of sequential circuits.

Uploaded by

Surendar Avi
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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VELAMMAL ENGINEERING COLLEGE, CHENNAI 66.

. EXAM CELL INTERNAL ODD SEMESTER 2011 2012 MODEL EXAM Sub/Sub Code: VLSI DESIGN/ EI2403 Max. Marks: 100Marks Sem/Branch: VII / EIE Date / Time: / 3Hours PART A (10 x 2 = 20 Marks)

1. What is the basic difference between enhancement and depletion NMOS? 2. What is the use of bulk effect capacitance? 3. Write the drain to source current equation for the NMOS working in saturation and active region. 4. Draw the stick diagram for two input NAND gate. 5. Differentiate static and dynamic CMOS circuits. 6. What are NAND-NAND, NOR NOR and AOI circuits? 7. List the methods of programming PAL. 8. Implement a half adder using PLA. 9. Define test bench program. 10. Write a VHDL code for 2:1 multiplexer using case statement. PART B (80 Marks) 11. (a) Explain the different aspects of CMOS device characteristics. (16) (OR) (b) Explain the principles of CMOS device fabrication in P-well method (16) 12. (a) Derive the pull up to pull down ratio required for an NMOS inverter driven by another NMOS inverter. (16) (OR) (b) (i) Draw and explain the stick and layout diagrams of a two input CMOS NOR gate. (8) (ii) Give a brief account of BiCMOS and steering logic. (8) 13. (a) (i) Write a brief note on dynamic CMOS technology. (8) (ii) Draw and explain with necessary stick diagram the design of a four way NMOS multiplexer. (8) (OR) (b) (i) Draw and explain the operation of a 4 x 4 barrel shifter. (8) (ii) Discuss the charge sharing problem occurred in a dynamic CMOS circuit and the methods to avoid it. (8) 14. (a) (i) Design a counter which counts the sequence 0,2,4,6,8,10,12,14,0.. in a PLA(8) (ii) Draw an NMOS based PLA arrangement and explain in detail. (8) (OR) (b) Explain the salient features of a FPGA? Explain in detail the architectural aspects, interconnect, logic and I/O details with suitable diagrams. (16) 15. (a) (i) Write a VHDL description of a test bench for a D Flip flop. (8) (ii) Explain the modeling of a sequential circuit using VHDL. (8) (OR) (b) (i) Explain the syntax details of a VHDL subprogram. Write a VHDL subprogram to perform binary to integer conversion. (8) (ii) Explain the application of packages in VHDL with a suitable example. (8)

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