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VHDL Örnekler2

This document contains examples of VHDL code for shift register, RAM, and ROM modules. The shift register code shifts the values in a 4-bit signal either from an input or by rotating the bits on each clock cycle. The RAM code defines a generic 4x4 RAM using an array of internal signals. The ROM code defines a 32x8 ROM with predefined constant values stored at each address. Examples of VHDL code for common digital components like registers, memory, and ROM are provided to demonstrate their implementation in VHDL.

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Ömer Küllaç
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© Attribution Non-Commercial (BY-NC)
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Download as PPT, PDF, TXT or read online on Scribd
24 views

VHDL Örnekler2

This document contains examples of VHDL code for shift register, RAM, and ROM modules. The shift register code shifts the values in a 4-bit signal either from an input or by rotating the bits on each clock cycle. The RAM code defines a generic 4x4 RAM using an array of internal signals. The ROM code defines a 32x8 ROM with predefined constant values stored at each address. Examples of VHDL code for common digital components like registers, memory, and ROM are provided to demonstrate their implementation in VHDL.

Uploaded by

Ömer Küllaç
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as PPT, PDF, TXT or read online on Scribd
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VHDL-rnekler

Shift Register
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Shift_register_VHDL is
port( Clock: in std_logic;
L,w: in std_logic;
Output: out std_logic_vector(3 downto 0);
Input: in std_logic_vector( 3 downto 0));
end Shift_register_VHDL;
architecture Behavioral of Shift_register_VHDL is
signal temp: std_logic_vector(3 downto 0);
begin
process
begin
wait until Clock'event and Clock='1';
if L='1' then
temp <= Input;
else
for i in 0 to 2 loop
temp(i) <= temp(i+1);
end loop;
temp(3) <= w;
end if;
end process;
Output <= temp;
end Behavioral;

RAM
--------------------------------------------------------------- a simple 4*4 RAM module (ESD book Chapter 5)
-- by Weijun Zhang
--- KEYWORD: array, concurrent processes, generic, conv_integer
-------------------------------------------------------------library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-------------------------------------------------------------entity SRAM is
generic(
port(

width:
depth:
addr:

integer:=4;
integer:=4;
integer:=2);
Clock:
in std_logic;
Enable:
in std_logic;
Read:
in std_logic;
Write:
in std_logic;
Read_Addr: in std_logic_vector(addr-1 downto 0);
Write_Addr: in std_logic_vector(addr-1 downto 0);
Data_in:
in std_logic_vector(width-1 downto 0);
Data_out: out std_logic_vector(width-1 downto 0)

);
end SRAM;
-------------------------------------------------------------architecture behav of SRAM is
-- use array to define the bunch of internal temparary signals
type ram_type is array (0 to depth-1) of
std_logic_vector(width-1 downto 0);
signal tmp_ram: ram_type;
begin
-- Read Functional Section

ROM
--------------------------------------------------------------- 32*8 ROM module (ESD Book Chapter 5)
-- by Weijun Zhang, 04/2001
--- ROM model has predefined content for read only purpose
-------------------------------------------------------------library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity ROM is
port( Clock : in std_logic;
Reset
: in std_logic;
Enable
: in std_logic;
Read
: in std_logic;
Address
: in std_logic_vector(4 downto 0);
Data_out: out std_logic_vector(7 downto 0)
);
end ROM;
-------------------------------------------------------------architecture Behav of ROM is
type ROM_Array is array (0 to 31)
of std_logic_vector(7 downto 0);
constant Content: ROM_Array := (
0 => "00000001",
1 => "00000010",
2 => "00000011",
3 => "00000100",
4 => "00000101",
5 => "00000110",
6 => "00000111",
7 => "00001000",
8 => "00001001",
9 => "00001010",
10 => "00001011",
11 => "00001100",

-- Suppose ROM has


-- prestored value
-- like this table
----------

Kaynaklar

http://en.wikibooks.org/wiki/VHDL_for_FPGA_
http://esd.cs.ucr.edu/labs/tutorial/

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