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Assignment 4

This document outlines an assignment for a VLSI design course. Students are asked to use L-Edit to layout two stick diagrams showing transistor arrangements, minimizing the area between transistors. They must determine the minimum area for each layout. Students also must draw Elmore Delay models for the n-type sections of each layout. The assignment is due on Saturday April 9th, 2005 at the beginning of lecture.

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54 views1 page

Assignment 4

This document outlines an assignment for a VLSI design course. Students are asked to use L-Edit to layout two stick diagrams showing transistor arrangements, minimizing the area between transistors. They must determine the minimum area for each layout. Students also must draw Elmore Delay models for the n-type sections of each layout. The assignment is due on Saturday April 9th, 2005 at the beginning of lecture.

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api-3864016
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Assignment 4

Fall 2004 / 2005


Part 1:
In the lab, use L-Edit to produce design rule correct layout for each of the following two stick
diagrams. Determine the minimum area needed to produce each of the two layouts.

Make sure that the area between adjacent transistors is the minimum possible.

VDD

B C A B C A D

OUT

B C A B D A C

GND

VDD

B C A B C A D

OUT

B C A B C A D

GND

Part 2:
Draw the Elmore Delay model for the n-type section of each of the two layouts.

Make sure your solution is neatly prepared and easy to follow and read.

Due date: Saturday April 9th, 2005 at the beginning of the lecture.

VLSI Design Dr. Bassel Soudan 1

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