Scribd
Upload
44 views1 page

Assignment 3

The assignment has 3 parts: 1) Complete an S-Edit tutorial and obtain a printout. 2) Use S-Edit to draw and connect a full adder circuit using inverter, transmission gate, and MUX modules. Obtain printouts of each module and the final circuit. 3) Draw the best layout for a CMOS complex gate showing logic graphs and Euler path selection. The completed assignment is due on March 16, 2005.

Uploaded by

api-3864016
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
44 views1 page

Assignment 3

The assignment has 3 parts: 1) Complete an S-Edit tutorial and obtain a printout. 2) Use S-Edit to draw and connect a full adder circuit using inverter, transmission gate, and MUX modules. Obtain printouts of each module and the final circuit. 3) Draw the best layout for a CMOS complex gate showing logic graphs and Euler path selection. The completed assignment is due on March 16, 2005.

Uploaded by

api-3864016
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 1

Assignment 3

Fall 2004 / 2005


Part 1:
Go to the lab. Personally perform the S-Edit tutorial that was covered in the presentation by Mr.
Yaser and Mrs. Eman.
Before leaving, make sure to show the lab assistant your completed work.
Obtain a print out and submit it with your homework.

Part 2:
In the lab, use S-Edit to draw and connect the full adder circuit shown below.
Hint: Create an inverter module, a transmission gate module and a 2X1 MUX module. Then build
the circuit using these modules.

SUM

CARRY

Obtain a print out of each module and the final circuit and submit it with your homework.

Part 3:
Using the technique shown in the class, draw the best possible layout for the following CMOS
complex gate. Show all steps including the formation of the logic graphs and Euler Path selection.

F = ( A • ( B + C + D)) + ( E • F • G )

Make sure your solution is neatly prepared and easy to follow and read.

Due date: Wednesday March 16th, 2005 at the beginning of the lecture.

VLSI Design Dr. Bassel Soudan 1

You might also like