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Assignment 1

This document outlines 3 assignments for a Fall 2004/2005 VLSI design course. The first assignment asks students to draw the voltage transfer curve and determine critical voltages and noise margins for a CMOS inverter. The second asks students to draw the transistor-level schematic for a logic function using simple gates and calculate the number of transistors. The third is similar but requires using a single complex gate. Students are asked to submit their solutions neatly by the beginning of lecture on March 2nd, 2005.

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45 views1 page

Assignment 1

This document outlines 3 assignments for a Fall 2004/2005 VLSI design course. The first assignment asks students to draw the voltage transfer curve and determine critical voltages and noise margins for a CMOS inverter. The second asks students to draw the transistor-level schematic for a logic function using simple gates and calculate the number of transistors. The third is similar but requires using a single complex gate. Students are asked to submit their solutions neatly by the beginning of lecture on March 2nd, 2005.

Uploaded by

api-3864016
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Assignment 1

Fall 2004 / 2005

1. Draw the Voltage Transfer Curve (VTC) and determine the critical voltages and noise
margins for a symmetric CMOS inverter with the following characteristics:

WN = 1 µm, Lmin = 1 µm, COX = 2.3 fF/µm2, k’N = 75 µA / V2


k’P = 30 µA / V2, VDD = 5 V, VTN = |VTP| = 0.7 V

2. Draw the schematic (transistor level design) for the following function using simple gates.
You may re-write the function to use basic NOT, NAND and NOR gates if you need.

F = ABC + DE + G

Calculate the total number of transistors needed.


Determine the worst-case number of transistors that separate an input from the output F.

3. Draw the schematic (transistor level design) for the following function using a single
complex gate.

F = ABC + DE + G

Calculate the total number of transistors needed.


Determine the worst-case number of transistors that separate an input from the output F.

Make sure your solution is neatly prepared and easy to follow and read.

Due date: Wednesday March 2nd, 2005 at the beginning of the lecture.

VLSI Design Dr. Bassel Soudan 1

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