Overview

Lecture 11: Sequential Circuits

Last lecture: Boolean logic and combinational circuits. Basic abstraction = controlled switch. In principle, can build TOY computer with a combinational circuit. 255 ! 16 = 4,080 inputs " 24080 rows in truth table! no simple pattern each circuit element used at most once
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This lecture: reuse circuit elements by storing bits in "memory." Next lecture: glue components together to make TOY computer.
ALU
combinational

Memory
state

COS126: General Computer Sci ence

http://w w w .cs.Pri nceton.EDU/~cos126

Sequential vs. Combinational Circuits

Flip-Flop
Flip-flop. A small and useful sequential circuit. Abstraction that "remembers" one bit. Basis of important computer components: memory counter
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Combinational circuits. Output determined solely by inputs. Can draw solely with left-to-right signal paths.
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We will consider several flavors. Sequential circuits. Output determined by inputs AND previous outputs. Feedback loop.
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SR Flip-Flop
What is the value of Q if: S = 1 and R = 0 ? " Q is surely 1
!

SR Flip-Flop
What is the value of Q if: S = 1 and R = 0 ? " Q is surely 1. S = 0 and R = 1 ? " Q is surely 0
! !

SR Flip-Flop
What is the value of Q if: S = 1 and R = 0 ? " Q is surely 1. S = 0 and R = 1 ? " Q is surely 0. S = 0 and R = 0 ? " Q is possibly 0
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SR Flip-Flop
What is the value of Q if: S = 1 and R = 0 ? " Q is surely 1. S = 0 and R = 1 ? " Q is surely 0. S = 0 and R = 0 ? " Q is possibly 0 . . . or possibly 1 !
! ! !

0 0

1 1

SR Flip-Flop
What is the value of Q if: S = 1 and R = 0 ? " Q is surely 1. S = 0 and R = 1 ? " Q is surely 0. S = 0 and R = 0 ? " Q is possibly 0 . . . or possibly 1.
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SR Flip-Flop
SR Flip-Flop. S = 1, R = 0 (set) S = 0, R = 1 (reset) S=R=0 S=R=1
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" " " "

Flips "bit" on. Flops "bit" off. Status quo. Not allowed.

old Q

SR flip flop

S R R

While S = R = 0 , Q remembers what it was the last time S or R was 1.

Interface Implementation

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Truth Table and Timing Diagram

Truth table. Values vary over time. S(t), R(t), Q(t) denote value at time t.
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Clock
Clock. Fundamental abstraction. regular on-off pulse External analog device. Synchronizes operations of different circuit elements. 1 GHz clock means 1 billion pulses per second.
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SR Flip Flop Truth Table S(t) 0 0 0 0 1 1 1 1 R(t) Q(t) 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Q(t+#) 0 1 0 0 1 1

Sample timing diagram for SR flip-flop.

#
Q R S

#
1 0 1 0 1 0
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cycle time

Clock

time

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How much does it Hert?

Frequency is inverse of cycle time. Expressed in hertz. Frequency of 1 Hz means that there is 1 cycle per second. Hence: 1 kilohertz (kHz) means 1000 cycles/sec. 1 megahertz (MHz) means 1 million cycles/sec. 1 gigahertz (GHz) means 1 billion cycles/sec. 1 terahertz (THz) means 1 trillion cycles/sec.
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Clocked SR Flip-Flop
Clocked SR Flip-Flop. Same as SR flip-flop except S and R only active when clock is 1.
!

S Cl R

SR flip flop

S Q R
Implementation

Clocked SR flip flop

Cl R

By the way, no such thing as 1 hert ! Q Cl R S

Interface

Heinrich Rudolf Hertz (1857-1894)

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Clocked D Flip-Flop
Clocked D Flip-Flop. Output follows D input while clock is 1. Output is remembered while clock is 0.
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Fetch-Execute Cycle
Fetch-execute cycle for TOY. Need 1-bit counter.
!

D Cl

Clocked SR flip flop

Clocked D flip flop

1-bit counter

Clock

Cl R
Implementation

D Cl

Cl

Execute Fetch

Interface

Fetch Q Cl D
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Execute Clock

1-Bit Counter
1-bit counter. Circuit that oscillates between 1 and 0.
!

1-Bit Counter
1-bit counter. Circuit that oscillates between 1 and 0.
!

1 0

Clocked D flip flop

Clocked D flip flop

1-bit counter

1
Q

Clocked D flip flop

0 X 1

Clocked D flip flop

1-bit counter

D Cl

Q1

D Cl

Q2
Slave

Cl Interface

Master

0 X 1

Q1

D Cl

Q2
Slave

Q Cl Interface

Cl
Master

1 X 0

Q2 Q1 Cl
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Q2 Q1 Cl
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1-Bit Counter
1-bit counter. Circuit that oscillates between 1 and 0.
!

1-Bit Counter
1-bit counter. Circuit that oscillates between 1 and 0.
!

1 X 0 0

Clocked D flip flop

D Cl

Q1

1 1 0 X

Clocked D flip flop

0 X 1

1-bit counter

D Cl

Q2
Slave

Q Cl Interface

0 0 X 1

Clocked D flip flop

D Cl

Q1

0 1 X 1 X 0

Clocked D flip flop

1-bit counter

D Cl

Q2
Slave

1
Cl

1 X

Master

Master

Interface

Q2 Q1 Cl
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Q2 Q1 Cl
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1-Bit Counter
1-bit counter. Circuit that oscillates between 1 and 0.
!

1-Bit Counter
1-bit counter. Circuit that oscillates between 1 and 0.
!

1 0 X 1 X 0

Clocked D flip flop

Clocked D flip flop

D Cl

Q1

D Cl

Q2
Slave

0 1 X

1-bit counter

Q Cl Interface

Clocked D flip flop

Clocked D flip flop

1-bit counter

D Cl

Q1

D Cl

Q2
Slave

Q Cl Interface

Master

1 0 X

Master

Q2 Q1 Cl
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Q2 Q1 Cl
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Memory Overview
Computers and TOY have many types of memory. Program counter. Registers. Main memory.
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Bus
16-bit bus. Bundle of 16 wires. Memory transfer, register transfer.
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16

We implement each bit of memory with a clocked D flip-flop. Need mechanism to organize and manipulate GROUPS of related bits. TOY has 16-bit words. Memory hierarchy makes architecture manageable.
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8-bit bus. Bundle of 8 wires. TOY memory address.

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4-bit bus. Bundle of 4 wires. TOY register address.

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Stand-Alone Register
k-bit register. Stores k bits. Register contents always available on output. If write enable is asserted, k input bits get copied into register. x0
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Register File Interface

n-by-k register file. Bank of n registers; each stores k bits. Read and write information to one of n registers. log2 n address inputs specifies which one Addressed bits always appear on output. If write enable and clock are asserted, k input bits are copied into addressed register.
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Ex: Program Counter, 16 TOY registers, 256 TOY memory locations.

D Q Cl D Q Cl

y0 y1

x1

16 write data

reg

16 read data

x15
Write

D Q Cl

y15

Examples. TOY registers: n = 16, k = 16. TOY main memory: n = 256, k = 16. Real computer: n = 256 million, k = 32. 1 GB memory (1 Byte = 8 bits)
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write data 16 Reg W addr 8

read data 16

write enable

16-bit Register Interface

16-bit Register Implementation

256 x 16 Register File Interface

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Register File Implementation

n = 8 for main memory

n-Bit Decoder
n-bit decoder. n address inputs, 2n data outputs. Addressed output bit is 1; others are 0.
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Implementation example: TOY main memory. Use 256 16-bit registers. Multiplexer and decoder are combinational circuits.
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x0 x1 x2

reg 0 0 reg 1 1 8-bit Decoder 16

0 000 1 Mux 16 read data 001 010 011 101 110 8 111

x0 x1 x2 x3 x4 x5 x6 x7 s2 s1 s0

x3 x4 x5 x6 x7

reg 255 255 select 8 addr 16 write data Cl W

255

sel

ect

3-Bit Decoder 100

select s2 s1 s0

addr
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3-Bit Decoder Interface

3-Bit Decoder Implementation

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n-Bit Decoder
n = 8 for main memory n = 8 for main memory

2n-to-1 Multiplexer
0 0 0

n-bit decoder. n address inputs, 2n data outputs. Addressed output bit is 1; others are 0.
! !

2n-to-1 multiplexer. n select inputs, 2n data inputs, 1 output. Copies "selected" data input bit to output.
! !

x0 x1 x2 x3

000 001 010 011 101 110 111

0 0 0 0 0 0 1 0 1 1 0

0 0 0 1 0

x0 x1 x2 x3 x4 x5 x6 x7

000 001 010 011 100 101 110 111

x4 x5 8 to 1 MUX ct le se
s0 s2s1

3-Bit Decoder 100

x6 x7

select 1 1 0

s2 s1 s0 8-to-1 Mux Implementation

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3-Bit Decoder Interface

3-Bit Decoder Implementation

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8-to-1 Mux Interface

2n-to-1 Multiplexer
n = 8 for main memory

2n-to-1 Multiplexer, Width = k

n = 8, k = 16 for main memory

2n-to-1 multiplexer. n select inputs, 2n data inputs, 1 output. Copies "selected" data input bit to output.
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0 0 0 1

2n-to-1 multiplexer, width = k. Select from one of 2n k-bit buses. Copies k "selected" data bits to output. Layering k 2n-to-1 multiplexers.
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0 0 0 1 0 1 1 1

000 001 010 011 100 101 110 111

0 1 8 to 1 MUX ct le se 01 1 1 1 1

1 4

x3 x2 x1 x0 x 4-wide 2-to-1 MUX x 4 y3 y2 y1 y0

0 2-to-1 MUX 0
z3 z2 z1 z0

4 copies of same bit Implementation for 2-to-1 MUX, width = 4

1 Interface for 2-to-1 MUX, width = 4

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8-to-1 Mux Interface

8-to-1 Mux Implementation

Register File Implementation

Implementation example: TOY main memory. Use 256 16-bit registers. Multiplexer and decoder are combinational circuits.
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Summary
Sequential circuits add "state" to digital hardware. Flip-flop. Represents 1 bit. TOY register. 16 D flip-flops. TOY main memory. 256 registers.
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reg 0 0 reg 1 1 8-bit Decoder 16

1 Mux 16 read data

Actual technologies for register file and memory are different. Register files are relatively small and very fast. expensive per bit Memories are relatively large and pretty fast. amazingly cheap per bit
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ect

reg 255 255 select 8 addr 16 write data Cl W

Next time: we build a complete TOY computer.

8

255

sel
addr
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Announcments
Not-exactly Midterm Exam Wed March 23, 7:30 PM, right here Closed book, but You can bring one cheatsheet one side of one (8.5 by 11) sheet, handwritten by you P.S. No calculators, laptops, Palm Pilots, fancy cellphones, etc. Covers entire first half of course (lectures, readings, precepts, assignments)
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Helpful review session Tuesday March 22, 7:30 PM, COS 105 Not a canned presentation Driven by your questions
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