MANCHEstER

1824
The University of Manchester

The Thumb instruction set

t Outline: r the Thumb programmers model r Thumb instructions r Thumb implementation r Thumb applications

 hands-on: writing Thumb assembly programs

2005 PEVEIT Unit ARM System Design

Thumb instruction set v5 1

MANCHEstER
1824
The University of Manchester

The Thumb instruction set

t Outline: the Thumb programmers model r Thumb instructions r Thumb implementation r Thumb applications

 hands-on: writing Thumb assembly programs

2005 PEVEIT Unit ARM System Design

Thumb instruction set v5 2

MANCHEstER
1824
The University of Manchester

What is Thumb?

t Thumb is: r a compressed, 16-bit representation of a subset of the ARM instruction set
primarily to increase code density also increases performance in some cases

t It is not a complete architecture r all Thumb-aware cores also support the ARM instruction set
therefore the Thumb architecture need only support common functions

2005 PEVEIT Unit ARM System Design

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MANCHEstER
1824
The University of Manchester

The Thumb bit

unused 7 6 5 4 0 I F T mode

31 30 29 28 27 NZCV

t The T bit in the CPSR controls the interpretation of

the instruction stream

r switch from ARM to Thumb (and back) by executing BX instruction r exceptions also cause switch to ARM code
return symmetrically to ARM or Thumb code

r Note: do not change the T bit with MSR!

2005 PEVEIT Unit ARM System Design

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MANCHEstER
1824
The University of Manchester

The Thumb programmers model

r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 SP (r13) LR (r14) PC (r15) CPSR shaded registers have restricted access Lo registers

Hi registers

2005 PEVEIT Unit ARM System Design

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MANCHEstER
1824
The University of Manchester

The Thumb programmers model

t Thumb register use: r r0 - r7 are general purpose registers r r13 is used implicitly as a stack pointer
in ARM code this is a software convention

r r14 is used as the link register

implicitly, as in the ARM instruction set

r a few instructions can access r8 - r15 r the CPSR ags are set by data processing instructions & control conditional branches

2005 PEVEIT Unit ARM System Design

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MANCHEstER
1824
The University of Manchester

The Thumb programmers model

t Thumb-ARM similarities: r load-store architecture

with data processing, data transfer and control ow instructions

r support for 8-bit byte, 16-bit half-word and 32-bit data types
half-words are aligned on 2-byte boundaries words are aligned on 4-byte boundaries

r 32-bit unsegmented memory

2005 PEVEIT Unit ARM System Design

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MANCHEstER
1824
The University of Manchester

The Thumb programmers model

t Thumb-ARM differences: r most Thumb instructions are unconditional

all ARM instructions are conditional

r most Thumb instructions use a 2-address format

most ARM instructions use a 3-address format

r Thumb instruction formats are less regular

a result of the denser encoding

r Thumb has explicit shift opcodes

ARM implements shifts as operand modiers

2005 PEVEIT Unit ARM System Design

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MANCHEstER
1824
The University of Manchester

The Thumb instruction set

t Outline: r the Thumb programmers model Thumb instructions r Thumb implementation r Thumb applications

 hands-on: writing Thumb assembly programs

2005 PEVEIT Unit ARM System Design

Thumb instruction set v5 9

MANCHEstER
1824
The University of Manchester

Thumb branch instructions

(1) B<cond> <label>

8 7 15 12 11 0 1 1 0 1 cond 8-bit offset 15 12 11 11100 15 12 11 10 1 1 1 1H 0 11-bit offset 0 11-bit offset 3 2 0 000

(2) B <label>

(3) BL <label>

15 12 11 7 6 5 0 1 0 0 0 1 1 1 0H

(4) BX Rm

2005 PEVEIT Unit ARM System Design

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MANCHEstER
1824
The University of Manchester

Thumb branch instructions

t These are similar to ARM instructions except: r offsets are scaled to half-word, not word r range is reduced to t into 16 bits r BL works in two stages:
H=0: LR := PC + signextend(offset << 12) H=1: PC := LR + (offset << 1) LR := oldPC + 3

r the assembler generates both halves r LR bit[0] is set to facilitate return via BX

2005 PEVEIT Unit ARM System Design

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MANCHEstER
1824
The University of Manchester

Thumb branch instructions

t Branch and eXchange (BX) r to return to ARM or Thumb caller:

BX lr ; replaces MOV pc, lr

t Subroutine calls r later ARMs support BLX instruction r to synthesize BLX or earlier ARM:
ADR r0, subr + 1 ADR lr, return BX r0 return ... ;
2005 PEVEIT Unit ARM System Design

; + 1 to enter Thumb mode ; save return address ; calls subr

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MANCHEstER
1824
The University of Manchester

Thumb software interrupts

15 8 7 0 1 1 0 1 1 1 1 1 8-bit immediate

t The Thumb SWI operates exactly like the ARM SWI r the (interpreted) immediate is just 8 bits
Thumb Angel SWI uses value 0xAB r0 call value is exactly as in ARM code

r the SWI handler is entered in ARM code

the return automatically selects ARM or Thumb

2005 PEVEIT Unit ARM System Design

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MANCHEstER
1824
The University of Manchester

Thumb data processing instructions

(1) ADD|SUB Rd,Rn,Rm

15 10 9 8 6 5 3 2 0 0 0 0 1 1 0 A Rm Rn Rd 15 10 9 8 6 5 3 2 0 0 0 0 1 1 1 A imm3 Rn Rd 15 12 11 10 8 7 0 0 1 op Rd/Rn 0 imm8 3 2 0

(2) ADD|SUB Rd,Rn,#imm3

(3) MOV|CMP|ADD|SUB Rd/Rn,#imm8

15 13 12 11 10 6 5 0 0 0 op #sh

(4) LSL|LSR|ASR Rd,Rn,#shift

2005 PEVEIT Unit ARM System Design

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MANCHEstER
1824
The University of Manchester

Thumb data processing instructions

(5) <Op> Rd/Rn,Rm/Rs

15 10 9 6 5 3 2 0 0 1 0 0 0 0 op Rm/Rs Rd/Rn 15 10 9 8 7 6 5 3 2 0 0 1 0 0 0 1 op D M Rm Rd/Rn 15 12 11 10 8 7 1 0 1 0 R Rd 15 8 7 6 10110000A r In case (6): 0 imm8 0 imm7

(6) ADD|CMP|MOV Rd/Rn,Rm

(7) ADD Rd,SP|PC,#imm8

(8) ADD|SUB SP,SP,#imm7

MOV does not affect the ags (it can be distinguished using the mnemonic CPY after v6)
2005 PEVEIT Unit ARM System Design Thumb instruction set v5 15

MANCHEstER
1824
The University of Manchester

Thumb data processing instructions

t Notes: r in Thumb code shift operations are separate from general ALU functions
in ARM code a shift can be combined with an

r ALU function in a single instruction r all data processing operations on the Lo registers set the condition codes
those on the Hi registers do not, apart from CMP which only changes the condition codes

2005 PEVEIT Unit ARM System Design

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MANCHEstER
1824
The University of Manchester

Thumb single register data transfers

(1) LDR|STR{B} Rd,[Rn,#off5]

15 13 12 11 10 6 5 3 2 0 011BL off5 Rn Rd 15 13 12 11 10 6 5 3 2 0 1000L off5 Rn Rd 12 11 9 8 6 5 3 2 0 15 0 1 0 1 op Rm Rn Rd 15 11 10 8 7 0 1 0 0 1 Rd 15 12 11 10 8 7 1 0 0 1 L Rd 0 off8 0 off8

(2) LDRH|STRH Rd,[Rn,#off5]

(3) LDR|STR{S}{H|B} Rd,[Rn,Rm]

(4) LDR Rd,[PC,#off8]

(5) LDR|STR Rd,[SP,#off8]

2005 PEVEIT Unit ARM System Design

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MANCHEstER
1824
The University of Manchester

Thumb multiple register data transfers

0 reg. list 0 reg. list
(2) POP|PUSH {<reg list>{,R}} (1) LDMIA|STMIA Rn!,

15 12 11 10 8 7 1 1 0 0 L Rn 15 10 9 8 7 1 0 1 1 1 1 LR

r These map directly onto the ARM forms:

PUSH: STMFD SP!, {<regs>{, lr}} POP: LDMFD SP!, {<regs>{, pc}}

note restrictions on available addressing modes compared with ARM code

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2005 PEVEIT Unit ARM System Design

MANCHEstER
1824
The University of Manchester

Unique Thumb mnemonics

t Most signicant differences from ARM:

PUSH POP NEG LSR ASR LSL ROR ; STMFD sp!,{&} ; LDMFD sp!,{&} ; RSB Rd, Rs, #0 ; MOV Rd, Rd, LSR <Rs | #5> ; MOV Rd, Rd, ASR <Rs | #5> ; MOV Rd, Rd, LSL <Rs | #5> ; MOV Rd, Rd, ROR Rs

2005 PEVEIT Unit ARM System Design

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MANCHEstER
1824
The University of Manchester

Newer Thumb instructions (from v5)

1 0 0

t BLX works in two stages; (rst is same as BL) 15 12 11 10 11101 10-bit offset
(1) BLX <label>

H=0: LR := PC + signextend(offset << 12) H=1: PC := (LR + (offset << 2)) AND FFFFFFFC LR := oldPC + 3 T flag := 0

r There is also a register-based BLX 15 7 6 3 2 0 0 1 0 0 0 1 1 1 1 Rm 0 0 0 t BKPT (Breakpoint)

2005 PEVEIT Unit ARM System Design Thumb instruction set v5 20

(2) BLX Rm

MANCHEstER
1824
The University of Manchester

Newer Thumb instructions (from v6)

Mnemonic allowing register moves without affecting ags

r CPY r SXTB/SXTH/UXTB/UXTH
Sign extension (no shifts)

r REV/REV16/REVSH
Byte swaps

r SETEND r CPSIE/CPSID
Interrupt enable/disables (no mode changes)

More about these in later ARM session.

2005 PEVEIT Unit ARM System Design Thumb instruction set v5 21

MANCHEstER
1824
The University of Manchester

ARM/Thumb interworking

t BX (Branch eXchange) moves to the mode specied by

the address LSB (in register)

t BLX (Branch with Link and eXchange) moves to the

other mode (common case)

r the LSB of LR retains the parent mode r BLX Rm can move to either mode (like BX) t The correct subroutine return is:
BX LR

r the routine can then be called from both ARM and Thumb code
2005 PEVEIT Unit ARM System Design Thumb instruction set v5 22

MANCHEstER
1824
The University of Manchester

ARM/Thumb interworking

t Calling procedures in other instruction set r ARM v5 or later

BLX procedure ; ARM or Thumb

r ARM v4T
from ARM ADR ADR BX return_addr ... from Thumb LDR MOV BX ...
2005 PEVEIT Unit ARM System Design

lr, return_addr ; r0, procedure + 1 ; + 1 sets T r0 ;

r0, =procedure lr, pc r0

; ; here + 4 ;
Thumb instruction set v5 23

MANCHEstER
1824
The University of Manchester

The Thumb instruction set

t Outline: r the Thumb programmers model r Thumb instructions Thumb implementation r Thumb applications

 hands-on: writing Thumb assembly programs

2005 PEVEIT Unit ARM System Design

Thumb instruction set v5 24

MANCHEstER
1824
The University of Manchester

Thumb decoding

t The original Thumb implementation translated the

opcodes into ARM opcodes.

r This means the effect of Thumb and ARM instructions are the same
Thumb is more restricted (e.g. smaller offsets/immediates) One or two new functions (e.g. BL details)

t Later implementations decode Thumb directly

2005 PEVEIT Unit ARM System Design

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MANCHEstER
1824
The University of Manchester

Thumb - ARM instruction mapping

15 12 11 10 8 7 0 0 1 op Rd/Rn 0 imm8
ADD Rd, #imm8

always condition ma jor opcode, format 3: MOV/ CMP/ADD/SUB with immediate

minor opcode denoting ADD & set CC

destination and source register

zero shift

immediate value

31 28 27 26 25 24 21 20 19 16 15 12 11 8 7 1 1 1 0 0 0 1 0 1 0 0 1 0 Rd 0 Rd 0 0 0 0

0 imm8

2005 PEVEIT Unit ARM System Design

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MANCHEstER
1824
The University of Manchester

The Thumb instruction set

t Outline: r the Thumb programmers model r Thumb instructions r Thumb implementation Thumb applications

 hands-on: writing Thumb assembly programs

2005 PEVEIT Unit ARM System Design

Thumb instruction set v5 27

MANCHEstER
1824
The University of Manchester

Thumb applications

t Thumb code properties: r 70% of the size of ARM code

30% less external memory power 40% more instructions

r With 32-bit memory:

ARM code is 40% faster than Thumb code

r With 16-bit memory:

Thumb code is 45% faster than ARM code

2005 PEVEIT Unit ARM System Design

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MANCHEstER
1824
The University of Manchester

Thumb applications

t For the best performance: r use 32-bit memory and ARM code t For best cost and power-efciency: r use 16-bit memory and Thumb code t In a typical embedded system: r use ARM code in 32-bit on-chip memory for small speedcritical routines r use Thumb code in 16-bit off-chip memory for large noncritical control routines
2005 PEVEIT Unit ARM System Design Thumb instruction set v5 29

MANCHEstER
1824
The University of Manchester

Hands-on: writing Thumb assembly programs

t Explore further the ARM software development tools r Write Thumb assembly programs r Check that they work as expected

 Follow the Hands-on instructions

2005 PEVEIT Unit ARM System Design

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