EECS150 - Digital Design Lecture 3 - Field Programmable Gate Arrays (FPGAs)

January 28, 2003 John Wawrzynek

Spring 2003

EECS150 - Lec03-FPGA

Page 1

Transistor-level Logic Circuits

Positive Level-sensitive latch

Transistor Level
clk

Positive Edge-triggered flip-flop built from two level-sensitive latches:

clk

clk

clk

Spring 2003

EECS150 - Lec03-FPGA

Page 2

Positive Edge-triggered Flip-flop

Flip-flop built from two latches: When clk low, left latch acts as feedthrough, and Q is stored value of right latch. When clk high left latch stores values and right latch acts as feedthrough.

clk

Spring 2003

EECS150 - Lec03-FPGA

Page 3

Outline
What are FPGAs? Why use FPGAs (a short history lesson). FPGA variations Internal logic blocks. Designing with FPGAs. Specifics of Xilinx Virtex-E series.

Spring 2003

EECS150 - Lec03-FPGA

Page 4

FPGA Overview
Basic idea: two-dimensional array of logic blocks and flip-flops with a means for the user to configure: 1. the interconnection between the logic blocks, 2. the function of each block.

Simplified version of FPGA internal architecture:

Spring 2003 EECS150 - Lec03-FPGA Page 5

Why FPGAs?
By the early 1980s most of the logic circuits in typical systems where absorbed by a handful of standard large scale integrated circuits (LSI).
Microprocessors, bus/IO controllers, system timers, ...

Every system still had the need for random glue logic to help connect the large ICs:
generating global control signals (for resets etc.) data formatting (serial to parallel, multiplexing, etc.)

Systems had a few LSI components and lots of small low density SSI (small scale IC) and MSI (medium scale IC) components.

Spring 2003

EECS150 - Lec03-FPGA

Page 6

Why FPGAs?
Custom ICs where sometimes designed to replace the large amount of glue logic:
reduced system complexity and manufacturing cost, improved performance. However, custom ICs are relatively very expensive to develop, and delay introduction of product to market (time to market) because of increased design time.

Note: need to worry about two kinds of costs:

1. cost of development, sometimes called non-recurring engineering (NRE) 2. cost of manufacture A tradeoff usually exists between NRE cost and manufacturing costs

total costs

A B

NRE

number of units manufactured (volume)

Spring 2003 EECS150 - Lec03-FPGA Page 7

Why FPGAs?
Therefore the custom IC approach was only viable for products with very high volume (where NRE could be amortized), and which were not time to market sensitive. FPGAs were introduced as an alternative to custom ICs for implementing glue logic:
improved density relative to discrete SSI/MSI components (within around 10x of custom ICs) with the aid of computer aided design (CAD) tools circuits could be implemented in a short amount of time (no physical layout process, no mask making, no IC manufacturing)

lowers NREs shortens TTM Because of Moores law the density (gates/area) of FPGAs continued to grow through the 80s and 90s to the point where major data processing functions can be implemented on a single FPGA.

Spring 2003

EECS150 - Lec03-FPGA

Page 8

Why FPGAs?
FPGAs continue to compete with custom ICs for special processing functions (and glue logic) but now also compete with microprocessors in dedicated and embedded applications.
Performance advantage over microprocessors because circuits can be customized for the task at hand. Microprocessors must provide special functions in software (many cycles).

Summary:

performance ASIC FPGA MICRO

NREs ASIC FPGA MICRO

Unit cost FPGA MICRO ASIC

TTM ASIC FPGA MICRO

ASIC = custom IC, MICRO = microprocessor

Spring 2003

EECS150 - Lec03-FPGA

Page 9

FPGA Variations
Families of FPGAs differ in:
physical means of implementing user programmability, arrangement of interconnection wires, and the basic functionality of the logic blocks.

Anti-fuse based (ex: Actel)

Most significant difference is in the method for providing flexible blocks and connections:

+ Non-volatile, relatively small fixed (non-reprogrammable)

Spring 2003

EECS150 - Lec03-FPGA

Page 10

User Programmability
Latch-based (Xilinx, Altera, )
latch

Latches are used to:

1. make or break cross-point connections in the interconnect 2. define the function of the logic blocks 3. set user options: within the logic blocks in the input/output blocks global reset/clock

+ reconfigurable volatile relatively large.

Configuration bit stream can be loaded under user control:

All latches are strung together in a shift chain:

Spring 2003

EECS150 - Lec03-FPGA

Page 11

Idealized FPGA Logic Block

Logic Block
INPUTS latch 1 set by configuration bit-stream

4-LUT

FF
0

OUTPUT

4-input "look up table"

4-input look up table (LUT)

implements combinational logic functions

Register
optionally stores output of LUT

Spring 2003

EECS150 - Lec03-FPGA

Page 12

4-LUT Implementation

INPUTS latch latch 16 latch 16 x 1 mux OUTPUT

n-bit LUT is implemented as a 2n x 1 memory:

inputs choose one of 2n memory locations. memory locations (latches) are normally loaded with values from users configuration bit stream. Inputs to mux control are the CLB inputs.

Result is a general purpose logic gate.

n-LUT can implement any function of n inputs!

latch

Latches programmed as part of configuration bit-stream

Spring 2003

EECS150 - Lec03-FPGA

Page 13

LUT as general logic gate

An n-lut as a direct implementation of a function truth-table. Each latch location holds the value of the function corresponding to one input combination. Example: 2-lut
INPUTS AND OR

Example: 4-lut
INPUTS

00 01 10 11

0 0 0 1

0 1 1 1

Implements any function of 2 inputs. How many of these are there? How many functions of n inputs?
Spring 2003

0000 0001 0010 0011 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111

F(0,0,0,0) F(0,0,0,1) F(0,0,1,0) F(0,0,1,1)

store in 1st latch store in 2nd latch

EECS150 - Lec03-FPGA

Page 14

FPGA Generic Design Flow

Design Entry:
Create your design files using: schematic editor or hardware description language (Verilog, VHDL)

Design implementation on FPGA:

Partition, place, and route to create bit-stream file

Design verification:
Use Simulator to check function, other software determines max clock frequency. Load onto FPGA device (cable connects PC to development board)

check operation at full speed in real environment.

Spring 2003 EECS150 - Lec03-FPGA Page 15

Example Partition, Placement, and Route

Idealized FPGA structure: Example Circuit:
collection of gates and flip-flops

Circuit combinational logic must be covered by 4-input 1-output gates. Flip-flops from circuit must map to FPGA flip-flops. (Best to preserve closeness to CL to minimize wiring.) Placement in general attempts to minimize wiring.
Spring 2003 EECS150 - Lec03-FPGA Page 16

Xilinx Virtex-E Floorplan

Spring 2003

EECS150 - Lec03-FPGA

Page 17

Virtex-E Configurable Logic Block (CLB)

2 logic slices

Spring 2003

EECS150 - Lec03-FPGA

Page 18

Details of Virtex-E Slice

Spring 2003

EECS150 - Lec03-FPGA

Page 19

Xilinx FPGAs (interconnect detail)

Spring 2003

EECS150 - Lec03-FPGA

Page 20

Virtex-E Input/Output block (IOB) detail

Spring 2003

EECS150 - Lec03-FPGA

Page 21

Virtex-E Family of Parts

Spring 2003

EECS150 - Lec03-FPGA

Page 22

Xilinx FPGAs
How they differ from idealized array:
In addition to their use as general logic gates, LUTs can alternatively be used as general purpose RAM. Each 4-lut can become a 16x1-bit RAM array. Special circuitry to speed up ripple carry in adders and counters. Therefore adders assembled by the CAD tools operate much faster than adders built from gates and luts alone. Many more wires, including tri-state capabilities.

Spring 2003

EECS150 - Lec03-FPGA

Page 23