1

Linl Maicrial

2
Lcsson-2

Operating principle and characteristics of a p-n junction
diode (L2.1)

p-n junction diode is Iormed by placing p and n type semiconductor materials in
intimate contact on an atomic scale. This may be achieved by diIIusing acceptor
impurities in to an n type silicon crystal or by the opposite sequence.

junction is characterized by the doping level (impurity atom density). In a step junction
accepter atom density has a high constant value in the p region and a very low value in
the n region. The opposite holds true Ior the donor atom density. In a graded junction
impurity density changes more gradually across the junction. Fig.1 shows a typical plot
oI impurity densities Ior both types oI junction.

Back

Back to ~reverse saturation current I
s




Fig. 1: Schematic diagram and impurity atom densities in a p-n junction (a)
Schematic diagram, (b) Impurity density in a step junction, (c) Impurity density in a
graded junction.
3
For the rest oI the discussion a step p-n junction will be assumed. In an open circuit p-n
junction majority carriers Irom either side with deIuse across the junction to the opposite
side where they are in minority. These diIIusing carriers will leave behind a region oI
ionized atoms at the immediate vicinity oI the metallurgical junction. This region oI
immobile ionized atoms is called the 'space charge region. ccumulated space charges
give rise to an electric Iield and potential barrier at the junction which opposes the
diIIusion oI carriers. Once the electric Iield and the potential barrier develop to suIIicient
level, migration oI carriers across the junction stops. t this point the p-n junction is said
to have attained 'thermal equilibrium. some what idealized plot oI the variation oI the
space charge density, the electric Iield and the electric potential along the device is shown
in Fig 2.



Fig. 2: Space charge density, electric field and electric potential inside a p-n junction
in thermal equilibrium; (a) schematic diagram; (b) space charge density; (c) electric
field; (d) electric potential.

The space charge densities in this idealized representation are assumed to be step
Iunctions oI magnitudes Na and Nd on the p are n sides respectively over the space
charge regions (-W
po
in the p side and W
no
in the n side).

Under this assumption the electric Iield strength is obtained by solving the one
dimensional Poisson`s equation.

4

)
)
po
ro
dE x -qNa
- W x 0
dx
E -w 0

)
)
po
po
-qNa x W
E x , - W x 0

)
)
no
no
dE x
qNd
0 x W
dx
E W 0

)
)
no
no
qNd x - W
E x 0 x W

From (2) Emax E(0)
a po
-qN W

From (4) Emax E(0)
d no
-qN W

Since E(x) is continuous at x0, Irom (5) and (6)
a po d no
N W N W

Now
)
)
no
po
2 2
W
a po d no
c
-W
q N W N W
- E x dx
2
o

Using (7) in (8)

) )
a po po no d no po no
c
qN W W W qN W W W

2 2
o



Substituting W
po
W
no
W
o
Zero bias space charge layer width


c c
po no
o a o d
2 2 1 1
W ; W
qW N qW N
o o


c a d
po no o
o a d
2 N N
W W W
qW N N
o

)
c a d
o
a d
2 N N
W
qN N
o

From (7) & (10)
c
max
o
2
E
W
o


In all these equations q is the charge oI an electron and is the dielectric constant oI the
semiconductor material.
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
(12)
5
When an external voltage V is applied across the p and n sides, it adds or subtracts with
the contact potential
c
o
. II the p side is made more positive with respect to the n side
(assumed positive convention oI V) it subtracts Irom
c
o . Since the potential barrier
reduces, the width oI the space charge layer and the maximum electric Iield strength at
the junction also reduce. The p-n junction is said to be Iorward biased under this
condition. Reversing the polarity oI V (i.e reverse biasing the p-n junction) has the
opposite eIIect.

pplication oI an external voltage does not qualitatively change the shapes oI the space
charge density, electric Iield or the electric potential distribution. ThereIore, all the
relationships given so Iar hold good with suitable modiIications. In particular

W(v) Width oI the space charge region with applied external voltage V


)
)
)
a d c a d
c
a d a d c
2 N N 2 N N V
- V 1-
qN N qN N

o +
= o

o
' '


o
c
v
or W(v) W 1-
+

o
' '


)
)
)
c
c c
max
o
c
V
2 1-
2 - V
Similarly E v
W v V
W 1-

+
o

o o
' '
o



)
c
Max
c
o
2
V
or E V 1-
W
o
o


alculation of Reverse Break down Voltage (L2.1.2) Back

Equation (14) indicates that the maximum Iield strength at the metallurgical junction
increases with the reverse bias voltage (V negative). t some critical value oI V -V
B

Max
E
reaches impact ionization value E
B
. t this electric Iield strength Iree electrons
gain suIIicient kinetic energy to break other electrons Iree Irom the valance bonds. This
impact ionization Iield strength (E
B
) depends on the magnitude oI the energy band gap
(between conduction and valance bands) oI the semiconductor material and has a typical
value oI 2 x 10
5
V/cm Ior silicon. II the reverse bias voltage exceeds V
B
impact
ionization will release a large number oI Iree carriers by avalanche multiplication process
and the p-n junction will undergo 'reverse break down characterized by a large reverse
current (Irom n to p side) Ilowing across the junction. Such large current quickly destroys
the junction by over heating. ThereIore, a p-n junction should never be operated at
(13)
(14)
6
reverse break down voltage. The reverse break down voltage can be calculated as
Iollows.

From (14) putting
)
Max B B B
E V E and V - V



c
B
B
c
o
2
V
E 1
W
o
o




)
2 2 2 2
o B o B
B c c B
c c
W E W E
OR V - V
4 4
o < o
o o



Substituting the expression oI W
O
Irom (11) in to the above equation

)
a d 2
B B
a d
N N
V E
2qN N

alculation of the Forward and Reverse urrent Densities
(L2. 1. 3) Back to ~equation 2.1
Back to ~forward biased p-n junction equation
pplication oI external voltage not only changes the width oI the space charge region
(also called 'depletion region) but also have very prominent eIIect on the excess
minority carrier density distribution as shown in Fig. 3.



Fig. 3: Excess minority carrier density distribution in a p-n junction (a) under
forward bias condition; (b) under reverse bias condition.
(15)
7
Iorward bias voltage lowers the potential barrier and allows a large number oI carriers
to change sides. It is known Irom the 'law oI the junction that the minority carrier
density at the edge oI the depletion region oI a Iorward biased p-n junction is given by


)
qv
KT
n no
p o p e


)
qv
KT
p po
n o n e

Where p
no
an n
po
are thermal equilibrium minority carrier densities in the p side and the n
side respectively and V is the applied voltage.

From basic semiconductor physics relationship

2 2
i i
no po
d a
n n
& n
N N
p

Where n
i
is the intrinsic carrier density in the semiconductor material.

Injected minority carriers recombine with majority carriers as they deIuse Iurther in the
electrically neutral region oI the semiconductor body. In steady state minority carrier
density is exponentially distributed in distance Irom the junction on either side. i.e.


) )
n
- x
L
p p
n x n o e
(19)

) )
p
- x
L
n n
p x p o e
(20)

where L
n
and L
p
are diIIusion lengths oI n and p type carriers in the p and then type
regions respectively.
Hatched portions oI Fig.3(a) represent stored excess minority carriers in the p and the n
type regions respectively.


)
n p po n
Q q n o - n L
| (21)

)
p n no p
Q q p o - p L
| (22)

Now in steady state Iorward bias condition excess minority carrier distributions shown in
Fig. 3 (a) remain stationary which implies that the carriers lost per unit time by
recombination must be replaced by Iorward current I
F



p
n
F
dQ
dQ
i.e. J
dt dt
(23)

From basic semiconductor physics the recombination dynamics is given by
(16)
(17)
(18)
8

p p
n n
n p
dQ Q
dQ Q
- and -
dt t dt t

Where t
n
an t
p
are carrier liIetimes oI n and p type carriers in the p and the n type
regions respectively.

Combining (23) and (24)

qv
p
p n 2
n KT
F i
p n a n d p
Q L Q
L
J q n e -1
t t N t N t
+


' ' |


Equation (25) also holds Ior reverse bias condition i.e. when v is negative. For suIIicient
reverse bias the reverse saturation current density is given by.

p 2 n
s i
a n d p
L
L
J q n
N t N t



|


qv
KT
F s
J J e -1
+

' '

Equations (26) and (27) deIine the i-v characteristics oI a junction diode under reverse
and Iorward bias conditions respectively.
(24)
(25)
(26)
(27)
9
%&RN ON Behavior of a Power Diode (L 2.2) Back

Fig. 1: Forward current and voltage waveforms of a Power Diode during Turn ON.
Several physical mechanism as explained below takes place during Turn ON of a
diode.

From time 0 to t
o
growing Iorward current charges the depletion layer capacitance Iormed
by the space charge oI the driIt region. The diode voltage increases gradually to the
Iorward bias junction voltage V
F
at which point the metallurgical junction p
+
n
-
becomes
Iorward biased. Minority carrier densities in all the sections oI the diode just reach their
respective thermal equilibrium levels at this point.
lthough the diode is Iorward biased aIter t
o
, the Iorward voltage drop across the device
keeps on increasing with the Iorward current Ior same more time. During this period the
driIt region oIIers signiIicant resistance due to insuIIicient carrier injection. Stray
inductance oI the waIer and bonding wires, coupled with the Iorward di
F
/dt, also
contributes to the increase in the Iorward voltage drop.
Finally aIter time t
o
t
1
resistance oI the driIt region starts decreasing due to conductivity
modulation. Forward current also reaches its steady state value 'I
F
and d
iF
/dt becomes
10
zero. s a result, the waveIorm oI the Iorward voltage drop turns over and starts
decreasing, reaching steady state value 'V
F
in time t
2
.
The peak voltage drop across the diode is called the Iorward recovery voltage and is a
strong Iunction oI the Iorward d
iF
/dt, The time interval t
1
is a Iunction oI the Iorward
d
iF
/dt with typical values in hundreds oI nanoseconds. However, t
2
is more or less
constant Ior a given diode with typical values less than 10 us. The time period t
1
t
2
is
oIten called the Iorward recover time (t
Ir
).
The next diagram explains the diode Turn on process.

11
Reverse Recovery characteristics of a power Diode

Back to ~Turn Off Behavior

Back to ~Diode

Fig. 1: Reverse Recovery characteristics of a power Diode.

Conceptually the Turn oII process oI a diode can be through oI as the reverse oI the Turn
on process. Excess minority carriers injected into the driIt region during Turn on have to
be removed beIore the diode can start blocking reverse voltage.
The reverse recovery current sweeps out excess carriers Irom the driIt region. t the end
oI time period t
3
minority carrier density in the p
+
and n
+
regions are already at their
thermal equilibrium level. However, there is still a large amount oI excess carriers
trapped in the driIt region which is then removed by the reverse recovery current during
time period t
4
. During this period minority carrier densities in the p
+
and n
+
regions do
not change very much. t the end oI t
4
too Iew carriers exist in the n
-
driIt region to
support the reverse recovery current demanded by the stray circuit inductance.
Recovery current starts Ialling sharply while the reverse voltage across the device
starts growing. Stay circuit inductance, coupled with large Ialling rate oI the recovery
current, can give rise to a peak reverse voltage (V
rr
) Iar in excess oI the steady state
blocking voltage (V
R
).
12
With increase in the reverse voltage across the diode, the depletion layer starts spreading
into the driIt region. Minority carrier densities quickly attain their respective reverse bias
proIile in the p
+
and n
+
regions.
Even at the end oI t
5
some trapped charges exist inside the driIt region which
disappear by the process oI recombination. ThereIore, reverse recovery charge (Q
rr
) is
always less than the total amount oI excess carriers stored in the driIt region during Turn
on. Next Iigure explains the carrier density variation with time during the Turn oII
process.

With reIerence ro Fig. 1


I rr
=
dt
diF
t4
=
dt
diF
1 8
trr
(1)

"
rr
<
2
1
t I rr rr
=
dt
diF

) 1 ( 2 8
trr
(2)

trr
=
dt di
8 "rr
F /
) 1 (
(3)


I rr
=
1
/ 2
8
dt di "rr F
(4)
Now iI the total charge stored in the driIt region is "
F
at a steady Iorward current
I F

then


I F

dt
d
"
F

:
"
F
OR F "
I
F
:
(5)

Where : is the excess carrier liIe time in the driIt region.
Now it has been argued earlier that
"
rr
_
"
F
always.
ThereIore Ior S 1 \\
dt
diF
F
rr
I
t
: 2
\ (6)

nd
dt
diF
F rr I I : 2
\ (7)

13
Equations (6) and (7) indicate that both
I rr
and
trr
increases with
I rr
. : increases
with
I F
and
dt
diF
while
trr
increases with
I F
but decreases with .
dt
diF

Power loss due to reverse recovery: With reIerence to Fig. 1. energy loss per
reverse recovery is given approximately by.

rr

J t I F rr 4
2
1

J t R
rr I
5
2
1

)
$J J
"
$J J
t I R F
rr R F
rr rr
$ $

1 1 2
1
(8)
II the switching Irequency is
1
8
then reverse recovery power loss is

1

= =
$
8 J
1 " 1

p
vr F
8 rr 8
rr
rr
(9)
14
$hottky Diodes (L 2.4) Back

Construction and Operating Principle
schottky diode is Iormed by placing a thin Iilm oI metal, usually luminum in direct
contact with a n type epitaxial layer grown on a
3

type substrate. The metal Iilm acts as

the positive electrode (anode) while the
3

substrate acts as the cathode. nother metal

contact is placed on the
3

cathode side Ior current collection. Fig. 2 shows the

schematic structure oI a schottky diode.

Fig.1: Schematic structure of a schottky diode.

The insulating
8io2
layer helps reduce the surIace electric Iield and improves reverse
characteristics.
The metal semiconductor junction on the anode side has a rectiIying property because the
electrons in the semiconductor have higher absolute potential energy compared to the
metal. So there will be a large Ilux oI electrons Ilowing Irom the semiconductor to the
metal across this interIace. Consequently the metal will become negatively charged while
the semiconductor positively charged and a depletion region similar to a p-n junction will
be Iormed at this interIace. However, the negative space charge in the metal comes Irom
Iree electrons and not Irom movement oI holes. This Ilow oI electron will continue till the
electrostatic potential associated with the space charge stops Iurther movement oI
electrons.
When a Iorward bias voltage (i.e, anode positive with respect to cathode) across this
structure, it reduces the potential barrier and makes it easier
15
Ior electrons to cross over. Biasing the metal negative with respect to the semiconductor
has the opposite eIIect. Thus, the metal semiconductor interIace exhibits a rectiIying
properly.
The same rectiIying properly is not observed at the cathode metal interIace. The cathode
has a much larger doping density. Thus the depletion region that is Iormed is very narrow
and the electric Iield very large. Under these circumstances, the electrons move very
easily across the interIace using a quantum mechanical eIIect called 'Tunneling under
the inIluence oI small applied voltage. That is why the cathode-metal interIace is an
ohmic contact and not a rectiIying contact.

Characteristics of schottky diodes


Fig. 2: i- v characteristic of a schottky diode.
Forward bias i-v characteristics oI a schottky diode is similar to that oI a p-n junction
diode. However, these diodes are designed to have lower Iorward voltage drop, the
diIIerence being 0.3-04V Ior the same Iorward current density.
In the reverse direction, a schottky diode has much larger reverse leakage current
compared to a p-n junction diode. The break down voltage is also considerably lower
(200v). Iter break down it exhibits resistance like characteristics.
Schottky diodes have much shorter switching times. Being a majority carrier device, no
stored charge needs to be removed during Turn oII. Consequently, there will be no
reverse current corresponding to removal oI minority carriers. Reverse current associated
with the growth oI the depletion layer charge in reverse bias will Ilow. But this is much
smaller compared to a p-n junction diode ( 5). Reverse recovery time (a Iew hundreds
oI nano seconds) and energy loss are also much smaller. During Turn on Iorward
recovery voltage
J 1r
is negligible due to much larger doping density and smaller width
oI the n type epitaxial layer. Voltage overshoot due to parasitic inductance may, however,
be observed at large di
F
/dt.
16
Lcsson-3

L 3.1

%ransistor current components
Back to ~equation 3.3 & 3.4

Back to Large current gain ~.



















Fig-1 shows diIIerent transistor current components. I
nE
is the electron component oI
emitter current arising due to diIIusion oI electrons into the base region Irom emitter.
Similarly I
PE
is the hole component oI the emitter current.

portion oI the electrons injected into the base recombines with majority hole carriers
there. Recombined holes are subsequently replenished by base current. This component
oI the base current is represented by (I
nE
I
nc
). I
PE
is another component oI the base
current due to hole injection Irom base to the emitter region.
I
cs
is the reverse saturation current oI the base collector junction and consists oI hole
component (I
pcs
) & electron component (I
ncs
).

From Fig 1 one can write

V
BE
V
CB
I
nE
I
pE
I
nC
Fig. 1 Transistor Current Components.
(I
nE
I
nC
)
I
cs
i
ncs
I
pcs
B (p)

E (n

)

C (n)

i
E
i
B
i
C
17

)
E nE pE
B nE nc pcs ncs pE
C nc cs
cs pcs ncs
I I I
I I - I - I - I I
I I I
I I I


Now
cs nc c nc
I I so I I <
nE cs PE nE PE
B
C nC nc nc nC nc
I I I I I
I
- 1 - -1
I I I I I I
+ +
<

' ' ' '

In order to make the dc current gain as large as possible.
B
C
I
I
should be very small.

ThereIore

nE
nE nc
nc
I
1 OR I I
I
< <

Which requires that recombination oI electrons in the base region be minimized. This is
achieved by making the base region very thin (Iraction oI a m in case oI signal
transistors) and increasing electron liIe time in the base region.

The other condition is

PE PE
nc nE
I I
0
I I
< <
This is achieved by increasing the doping level oI the emitter with respect to the base.

L 3.2
%he collector drift region and quasi saturation in a power
transistor
Back to ~drift region

Back to ~quasi saturation region

s in the case oI a power diode a lightly doped collector drift region (link to Section
2.3.1 of Module 2) is introduced in a power transistor in order to support the large base
collector reverse voltage. This driIt region has signiIicant eIIect on the output i-v
characteristics oI a power transistor as explained next.







18
























In the active region the minority carrier density proIile in the base extends up to the space
charge layer at the base driIt region interIace. s the collector current increases the
reverse voltage across this junction reduces due to increased drop in the load resistance.
ThereIore, the depletion layer width reduces and the minority carrier density proIile in the
base region approaches the junction and reaches it at the beginning oI the quasi saturation
region. In the quasi saturation region the base driIt region junction becomes Iorward
biased and hole injection Irom the base occurs in the collector driIt region. t the same
time excess electrons injected in to the base Irom the emitter side also enters the driIt
region in order to maintain space charge neutrality.

Thus, in the driIt region oI a Power transistor carrier injection and conductivity modulator
occurs just as in a power diode. The resistivity oI the driIt region and hence the collector
emitter voltage drop depends on the amount oI carrier injection into the driIt region
which in turn depends on the base current. ThereIore, base current retains some control
over the collector current in the quasi saturation region although the value oI . reduces
considerably due to eIIective increase oI the base width.

Hard saturation is obtained when the excess carrier density proIile in the driIt region
reaches heavily doped collector region interIace. The driIt region is now completely
shorted out by the excess carriers. ny Iurther increase in the base current causes Iurther
increase in the excess carrier density in the driIt region and hole injection in the collector
region. However, the excess carrier does not change the resistivity oI the driIt region
V
BB
i
B
R
B
v
CC
n

(E)
p
(B)
n
-

(DRIFT)
n

(c)





R
L
i
B
M
i
n
o
r
i
t
y

c
a
r
r
i
e
r

d
e
n
s
i
t
y
.

Increases with time
Increases with time
Increases
with time
Increases
with time
19
signiIicantly and hence V
CE
does not change very much. The base current looses control
over the collector current which is now determined entirely by the external biasing
voltage (V
cc
), load resistance (R
L
) and the resistance oI the conductivity modulated driIt
region.

L 3.3

urrent rowding and $econd Break Down in a Power
%ransistor

Emitter current crowding occurs in a Power BJT due to its constructional Ieatures as
explained below.

Back to ~current crowding

Back to ~second break down

Back to ~the second break down
























Due to the device geometry, during Iorward bias condition, there will be a lateral ohmic
voltage drop in the base region. ThereIore, the base emitter junction voltage near the
periphery oI the emitter region will be higher compared to the central region. The base
current density near the emitter periphery will be higher as a consequence (thicker blue
H
H H H
B
E
B
Current
Crowding
C
n

n

p

H
H H
B
B E
Current
Crowding
Figure 1: Emitter current crowding in a Power B11;
(a)During forward bias condition,
(b)During reverse bias condition.
H
C
n

p

n

(a) (b)
20
arrows in Fig.1(a)). This will lead to 'crowding oI emitter current near its periphery
(Thick red arrows in Fig.1(a)). Following the same logic current crowding will occur at
the central emitter region during reverse base bias condition (turn oII) as shown in
Fig.1(b).

One consequence oI emitter current crowding is lowering oI eIIective DC current gain
due to high level carrier injection in some portions oI the emitter. This reduction in dc
current gain occurs at a lower current level than iI the current density were uniIormly
spread over the entire emitter area.

However, a more serious consequence oI current crowding is the increased likelyhood oI
second break down Iailure. It has been mentioned in section 3.4 that 'second break
down Iailure oI Power BJT occurs due to Iormation oI 'current Iilaments and localized
thermal runaway. Non- uniIorm current density across the device will increase the
probability oI such thermal run away due to negative temperature coeIIicient oI resistivity
in a BJT. Non-uniIormity oI current density can be caused by emitter current crowding.
To reduce the severity oI current crowding the width oI the emitter regions in a power
BJT are made small while a large number oI such narrow 'Iinger like emitters are
spread over the entire cross section oI the device and connected in parallel.

Back
L 3.4

ollector Base Junction break down voltage (V
BO
)

When a BJT is in the blocking state the CB junction must withstand the applied voltage.
The maximum voltage a BJT can withstand diIIers considerably depending on whether it
is in open base (i
B
o) on open emitter condition (i
B
o). These two blocking voltages
are dented by V
CEO
and V
CBO
respectively with V
CEO
V
CBO
.

It should be noted that even with i
B
0 the base- emitter junction is Iorward biased due to
the reverse bias current oI the C-B junction. s a result, there is carrier injection into the
base Irom the emitter side. This excess carrier in eIIect increases the reverse saturation
current oI the CB junction in the open base conIiguration compared to the open emitter
conIiguration. ThereIore, Ior a given voltage, more number oI carriers cross the CB
junction depletion region in the open base conIiguration. Consequently, the rate oI impact
ionization increases and the break down voltage reduces.

There is a semi-empirical relationship between the parameters V
CEO
and V
CBO
given by


CBO
1 CEO
n
V
V

n 4 Ior n p n transistors.
21
L 3.5

$witching characteristics of B%J with L--R-D $nubber Back

The switching characteristics oI a BJT with snubber circuit as shown in Fig 1 (a) is
shown in Fig 1 (b)






















V
BB
I
L
R
B
i
B
V
CE
i
C

-
(a)
V
CC
D

C
S
R
S
D
S
L
S


i
D

i
LS
Q

i
RS
i
DS
i
CS
v
c
22











































V
BB








v
BB
-V
BB
i
B
v
CC
v
CE
v
C
i
cs
i
RS
i
LS
i
DS
i
D
i
C I
L
v
CM
(b)
t
d
t
Iv
t
s
t
Ii
t
t
t
t
t
23






















The main diIIerence here is that i
C
can not rise beIore V
CE
starts Ialling due to the turn on
snubber inductance L
s


Here V
CE
starts Ialling Iirst with a Iall time oI t
Iv
aIter the usual delay time t
d.
V
CE
is given
by


CE CC
V V 1-
1v
t
t
+

' '
assuming
CE sat
V 0 <
Collector current i
C
can be written
i
C
i
ls
- i
cs

Diode D
s
is in oII condition


CC CE CC CC
t t
2
ls
o o
Iv s s s Iv
V - V V V 1

L 2 L L t
t
i dt dt t
t



lso
CE C C CE C
cs s
s s
V - V dV V - V
i or C
R dt R


or )
C
s s C CE CC C CC
Iv
dV
t
R C V V V 1- , V o V
t dt
+

' '


From which V
C
can be solved.
II t
Iv
is negligible compared to R
s
C
s
time constant then
Turn on
Turn oII
FBSO
RBSO
log i
C
I
L
(c)
V
CC
V
CEO
v
c max
V
CBO
log v
CE
Fig.-1: Switching characteristics of a B1T with L-R-C-D snubber
(a) Snubber circuit, (b) Switching waveforms,
(c) Switching Trajectory
24
) )
CC
C Iv CC cs Iv
s
V
V t V & i t
R
< <
lso )
CC Iv
ls Iv
s
1 V t
i t
2 L

) ) )
)
CC
Iv
C Iv cs Iv ls Iv
s s s
V
t
1
i t i t i t 1
2 R L R

|

For saIe operation oI the BJT it will be necessary that

)
CC Iv s
C Iv CM CM LR
s LR s
V t L
1
i t I or 1 I where t
2 R t R


|


Iter t
Iv
V
CE
0, i
ls
increases linearly with a slope V
CC
/L
s
and is given by

) )
CC Iv CC
Iv
s s
1 V t V
t
2 L L
8
i t t

)
)
CC Iv CC
Iv Iv
s s
V t V
1
t - t . t - t
2 L z L


|



)
Iv
s s
t-t
-
R C CC
cs
s
V
i e
R
<


)
Iv
RC
- t -t
t CC Iv
c ls cs RC s s
s LR LR
V t 1 t
i i i - e t R C
R t 2 t

<


|


Turn on process ends when
s L
ls L Iv
CC
L I
1
i I at t t
2 V


t that tine
L I
s L 1
- - t
Iv
2 V
CC
Rc
t
CC s L
C CF
s CC LR
V L I
i i e
R V t


|



|

Or
)
Iv s s L
2
Rc CC s s
t L C I
1
-
2 t V R R
CC
CF L
s
V
i I e
R

|

For saIe operation oI the BJT it will be necessary that

i
CF
I
CM


Turn oII process starts with the base drive voltage going negative. Now V
CE
can not rise
without charging C
s
. ThereIore i
c
starts Ialling with a Iall live t
Ii
and is given by
)
c L Ii
i I 1- t t , But i
ls
I
L

25

cs L c L
Ii
2
t t
L L
c cs
o o
s s Ii s Ii
t
i I - i I
t
1 I 1 I t
v i dt t dt
C C t 2 C t

L Ii
Ii c c Ls L
s
1 I t
at t t , v & i o, i I
2 C


Iter words v
c
charges with constant current i
c
i
Ls
I
L
and is given by

)
)
Ii L L
c L Ii Ii
s s s
1 t I I
1
v I t - t t - t
2 2 C C C


v
c
reaches V
CC
at
CC s
Ii
L
V C
1
t t
2 I

)
)
Ii
CC L s
CC L s
t
1
V I C 1
2
V I C
+

' '

Iter this time i
ls
starts Ialling through resonance between L
s
& C
s



s
CC s c
diL
V L v
dt


)
) )
ls
CC Ls s ls c CC ls CC ls
ls
s ls c CC c CC
di
or V i L i v - V i V i
dt
di d
or L i v - V c v - V 0
dt dt


) )
) )
CMax CC L
s ls ls c CC c CC
V -V I
c CC c CC s ls ls
o o
L i di c v - V d v - V 0
v - V d v - V L i di

)
2
2
s L CMax CC
1 1
L I C V - V
2 2


s
CMax CC L
s
L
or V V I
C

For saIe operation oI the transistor it is necessary that

V
CMax
V
CBO


V
c
then discharges through R
s
& D towards V
CC

26
Lcsson-4

L 4.1
%hyristor Protection Back

In a converter circuit a thyristor circuit needs to be protected against (i) large
di
dt
, (ii)
large
dv
dt
, (iii) over voltage and (iv) over current. In addition the thyristor gate circuit
also needs to be protected against over voltage over current and spurious noise signals.

di
dt
protection: s discussed in connection with turn on switching oI a thyristor, the
anode current, just aIter turn on is restricted to a small area oI the cathode which
increases with time at a Iinite rate. Now iI the rate oI rise oI anode current

di
dt
+

' '
is
larger than that rate the current density in a portion oI the cathode cross section will keep
on increasing leading to the Iormation oI local hot spots. The device may be destroyed in
the process. The manuIacturers usually speciIy a limiting value oI

di
dt
(20-500 /s)
which should not be exceed to avoid this type oI Iailure. In a thyristor converter circuit
the rate oI rise oI anode current is restricted by connecting on inductor oI appropriate
value in series with the thyristor. This is called the
di
dt
limiting inductor.

dv
dt
protection: When a Iorward voltage is suddenly applied across reverse biased
thyristor there will be considerable redistribution oI minority carriers across all three
junctions. The process is akin to charging the junction capacitances with the opposite
polarity. II the rate oI change oI the applied
)
dv
dt
is large this 'capacitor charging
current
j
c dv
dt
+

' '
across the junctions may become suIIicient to satisIy the latching
condition oI the thyristor (i.e, 1 2 1) and the thyristor may turn on even in the
absence oI a gate pulse. To protect against such spurious turn on oI the thyristor a
properly designed RC snubber circuit (as discussed in connection with diode circuit)
should be used across the thyristor. The snubber components should be designed such
that they along with the
)
di
dt
limiting inductor and the load Iorms a slightly under
damped circuit.

Over voltage protection: Over voltage across a thyristor may occur due to several
reasons such as due to snappy reverse recovery, due to commutation in other thyristors in
the same circuit, network switching, lightning surges etc. OI these, the Iirst two types can
be handled by a properly designed snubber circuit across the thyristor. However, Ior the
27
last two types, over voltage protection oI a thyristor must be upgraded by using a voltage
clamp device across the thyristor.

voltage clamp device is a non linear resistance which acts as an open circuit under
normal condition (i.e. below clamping voltage) and as a short circuit when voltage across
it crosses the clamping level. The surge energy is dissipated in the non linear resister.
Metal oxide Varistors are commonly used as voltage clamp devices.

Over current protection: Over current in a thyristor circuit occurs due to a Iault or short
circuit. Thyristor can with stand Iault currents Iar in excess oI its rated average or RMS
Iorward current Ior short durations (several cycles oI the supply Irequency). ThereIore, iI
the Iault impedance is high or the supply ac network has a relatively low short circuit
level, the thyristor may be protected using a normal circuit breaker. However, Ior a short
circuit Iault when the ac network supplying the thyristor circuit is stiII the Iault current
may rise to dangerous level and destroy the device. To protect a thyristor against such
Iaults Fast cting Current Limiting Fuse (F..C.L Iuse) is connected in series with a
thyristor. For proper protection co-ordination oI the Iuse and the thyristor is important.
The i
2
t rating oI the Iuse must be less than that oI the thyristor and the 'peak let through
current should be less than the sub cycle surge current rating oI the thyristor. The Iuse
voltage rating should also be less than the surge voltage rating oI the thyristor.

Gate protection: The gate circuit should be protected against over voltage and over
current. series resistance and a zener diode across the gate cathode terminals are
provided Ior this purpose. To prevent conducted or radiated EMI to aIIect the gate circuit
the gate supply cables are twisted and shielded. In addition, a small capacitor (a Iew
hunded nF) in parallel with another resistance is connected just across the gate and
cathode terminals to protect the gate against spurious noise voltages. In very large power
application Light activated Thyristors using optical Iiber signal transmission is used Ior
maximum protection against spurious turn on. Fig 1. shows typical protection
arrangement Ior a high power thyristor.














From
Supply
Circuit
Breaker
F..C.L
Fuse
R.C snubber
di/dt limiting
inductor
Voltage clamp
device (MOV)
Gate pulse

To
LOD
Fig. 1: Thyristor protection circuit.
28
L 4.2
$eries and Parallel onnection of thyristors Back

In some industrial applications the voltage and current levels are in excess oI a single
available thyristor. In such cases series / parallel connection oI multiple thyristors are
employed. For series or parallel connected thyristors it should be ensured that each
thyristor rating is utilized Iully and the system perIormance is satisIactory. String
eIIiciency is a term used to measure the degree oI utilization oI thyristors in series /
parallel connection and is deIined as


ctual Voltage / current rating oI the whole string
String eIIiciency
Individual voltage / current rating oI each thyristor no. oI
thyristors in the string


For obtaining the highest possible string eIIiciency the thyristors connected in series /
parallel must have identical i-v characteristics. Even then, unequal voltage / current
sharing does occur which makes string eIIiciency lees than unity. However, unequal
voltage / current sharing by the thyristors in a string can be minimized to a great extent
by using external equalizing circuits. These are discussed next.

$eries connection of thyristors















Fig 1 (b) shows the static i-v characteristics oI two series connected thyristors oI Fig 1
(a). It is seen that slight diIIerence in the Iorward blocking characteristics oI the two
V
1
V
2
I

Th
1
Th
2
(a) V
2
V
1
V
K
Th
1
Th
2
I

i

(b)
Fig. 1: Characteristics of series connected thyristors.
29
thyristors results in considerable diIIerence in the Iorward voltage blocked by each
thyristor. Similar diIIerence will be Iound Ior reverse blocking voltage.

The problem oI unequal voltage sharing will be more prominent during dynamic
conditions. It is likely that SCRs will not have identical dynamic characteristics. In such
cases, series connected SCRs will have unequal voltage distribution during the transient
conditions oI turn ON and turn OFF.

















Fig 2: Turn ON and Turn OFF characteristics oI series connected Thyristors.
(a) Turn ON characteristics; (b) Turn OFF characteristics.

The Top Iigures oI Fig 2 (a) & (b) shows the individual Turn ON and Turn OII
characteristics oI series connected thyristors TH
1
and TH
2
oI Fig 1(a). It is assumed that
TH
2
has a larger turn on delay time and larger turn oII time. s a result when the series
combination oI TH
1
and TH
2
are gated together TH
1
turns on Iaster while the voltage
across TH
2
rises to the Iull supply voltage V
s
.

During Turn oII as the Iorward current through the series combination goes negative TH
1

recovers earlier blocking the path Ior reverse recovery oI Th
2
. Consequently the reverse
voltage is supported by TH
1
alone while the voltage across TH
2
remains almost zero.

simple resistor as shown in Fig 1(b) will not ensure equal voltage distribution across
devices during dynamic condition. The reverse biased junctions oI thyristor are likely to
V
K
V
K
V
K
V
K1
V
K1
V
K2
V
K2
V
K2
V
K1
V
S
V
S/2
V
S
t
t
t
t
Th
2

Th
1

i
a

(a)
(b)
Fig. 2: Turn ON and Turn OFF characteristics of series connected thyristors.
30
have diIIerent capacitances and when connected in series, are likely to share dynamic
voltage unequally during Turn on and Turn oII.

This problem can be avoided by connecting shunt capacitors across thyristors as shown in
Fig 3. These shunt capacitors being much larger than the reverse biased junction
capacitors oI the thyristors tends to equalize the eIIective capacitance oI the circuit.
series resistance R
C
is also used along with the shunt capacitance in order to limit the
capacitor discharge current during 'Turn on oI the thyristor. diode D by passes R
C

when Iorward voltage appears across the series combination. This makes the capacitor
more eIIective Ior voltage equalization and Ior limiting
dv
dt
across the thyristor.














Parallel connection of %hyristors

number oI thyristors are connected in parallel to supply load currents in excess oI the
individual ratings oI the thyristors. For equal sharing oI current the i-v characteristics oI
parallel connected thyristors should be as Ior as possible identical. Otherwise diIIerence
in current sharing will occurs as shown in Fig 4.








R
R
Static voltage equalizer
R
C

R
C

TH1
TH2
D
D
C
C

Dynamic
voltage
equalizer
Fig. 3: Static and dynamic voltage equalizer for series connected thyristor.
31











In this case TH
1
has a lower voltage drop and hence it shares larger current. DiIIerence in
current sharing may occur due to diIIerence in the dynamic characteristics oI the
thyristors. For example, iI one oI the thyristors have a larger turn on delay time compared
to other thyristors with which it is paralled it will not turn on at the same instant as the
other thyristors turn ON. However, voltage across it will collapse due to turning ON oI
other thyristors. For a given gate current a minimum anode cathode voltage is required
Ior a thristor to turn ON which may not be available in this case. Thus the thyristor with
larger turn ON delay time will never turn ON.

Unequal current sharing also causes unequal heating oI thyristor junctions. The ON state
voltage drop across a conducting thyristor is a strong Iunction oI the junction temperature
and decreases with increasing junction temperature. Thus the thyristor carrying the
largest current tend to share even more current as its junction temperature rises. This may
lead to 'thermal run away and destroy all parallels connected thyristors.

In an ac circuit unequal current sharing between parallel connected thyristors can be
avoided by using a reactor as shown in Fig 4 (c). The reactor oIIers little impedance to
the common mode current (I
1
I
2
) but a large impedance to any circulating current (I
1

I
2
). Unequal current sharing is thus minimized.
TH1 TH2
V
K
I
a
I
2
I

I
1
(a)
TH1
TH2
V
K
V
K
I
1
I
2
(b)
i
a
TH2
I
1

TH1
I
2

K

(c)
Fig.4: Current sharing of parallel connected thyristors.