VHDL Code

Top level QDR SRAM Controller:

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity QDR_TOP is Port (HOST_CLK: in std_logic; HOST_DWL: in std_logic_vector(17 downto 0); HOST_DWH: in std_logic_vector(17 downto 0); HOST_DRL: out std_logic_vector(17 downto 0); HOST_DRH: out std_logic_vector(17 downto 0); HOST_A_R: in std_logic_vector(17 downto 0); HOST_A_W: in std_logic_vector(17 downto 0); CMD_RW: in std_logic_vector(1 downto 0); RST: in std_logic; QDR_K_CLK: out std_logic; QDR_Kn_CLK: out std_logic; QDR_C_CLK: out std_logic; QDR_Cn_CLK: out std_logic; QDR_A_RD: out std_logic_vector(17 downto 0); QDR_A_WR: out std_logic_vector(17 downto 0); QDR_WD_BW0: out std_logic_vector(17 downto 0); QDR_WD_BW1: out std_logic_vector(17 downto 0); QDR_D_R: in std_logic_vector(17 downto 0); QDR_W: out std_logic; QDR_R: out std_logic); end QDR_TOP; architecture RTL of QDR_TOP is --*********************************************** --* Components declaration --*********************************************** component ADD_GEN Port (CLK90: in std_logic; ADD_R: in std_logic_vector(17 downto 0); ADD_W: in std_logic_vector(17 downto 0); CMD_R: in std_logic; CMD_W: in std_logic; RST: in std_logic; LOCK_PLL: in std_logic; QDR_RD_A: out std_logic_vector(17 downto 0); QDR_WR_A: out std_logic_vector(17 downto 0)); end component; component CLK_GENERATE Port (CLKIN: in std_logic; RST: in std_logic;

CLK0: out std_logic; CLK90: out std_logic; K_CLK: out std_logic; Kn_CLK: out std_logic; C_CLK: out std_logic; Cn_CLK: out std_logic; CLK_LOCKED: out std_logic); end component; component WRITE_BURST Port (CLK90: in std_logic; D0: in std_logic_vector(17 downto D1: in std_logic_vector(17 downto CMD_W: in std_logic; RST: in std_logic; LOCK_PLL: in std_logic; Q_WD_BW0: out std_logic_vector(17 Q_WD_BW1: out std_logic_vector(17 end component;

0); 0);

downto 0); downto 0));

component READ_BURST Port (C_CLK: in std_logic; CLK90: in std_logic; D: in std_logic_vector(17 downto 0); CMD_R: in std_logic; RST: in std_logic; Q0: out std_logic_vector(17 downto 0); Q1: out std_logic_vector(17 downto 0)); end component; component CTRL_RW Port (CMD_W: in std_logic; CMD_R: in std_logic; RST: in std_logic; W_CYCLE_GEN: out std_logic; R_CYCLE_GEN: out std_logic); end component; --*********************************************** --* Signals declaration --*********************************************** signal CLK0: std_logic; signal CLK90: std_logic; signal K_C_LOCK: std_logic; begin ADD_W_R: ADD_GEN port map (CLK90 => CLK90, ADD_W => HOST_A_W, ADD_R => HOST_A_R, CMD_W => CMD_RW(1), CMD_R => CMD_RW(0), RST => RST, LOCK_PLL => K_C_LOCK, QDR_RD_A => QDR_A_RD,

QDR_WR_A => QDR_A_WR); IN_OUT_CLK: CLK_GENERATE port map (CLKIN => HOST_CLK, RST => RST, CLK0 => CLK0, CLK90 => CLK90, K_CLK => QDR_K_CLK, Kn_CLK => QDR_Kn_CLK, C_CLK => QDR_C_CLK, Cn_CLK => QDR_Cn_CLK, CLK_LOCKED => K_C_LOCK); WRITE_D_H_L: WRITE_BURST port map (CLK90 => CLK90, D0 => HOST_DWL, D1 => HOST_DWH, CMD_W => CMD_RW(1), RST => RST, LOCK_PLL => K_C_LOCK, Q_WD_BW0 => QDR_WD_BW0, Q_WD_BW1 => QDR_WD_BW1); READ_D_H_L: READ_BURST port map (C_CLK => CLK0, CLK90 => CLK90, D => QDR_D_R, CMD_R => CMD_RW(0), RST => RST, Q0 => HOST_DRL, Q1 => HOST_DRH); CTRL_W_R_OP: CTRL_RW port map (CMD_W => CMD_RW(1), CMD_R => CMD_RW(0), RST => RST, W_CYCLE_GEN => QDR_W, R_CYCLE_GEN => QDR_R); end RTL;

Lower level components:

Address Generator:
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity ADD_GEN is Port (CLK90: in std_logic; ADD_W: in std_logic_vector(17 downto 0); ADD_R: in std_logic_vector(17 downto 0); CMD_W: in std_logic; CMD_R: in std_logic; RST: in std_logic; LOCK_PLL: in std_logic; QDR_RD_A: out std_logic_vector(17 downto 0); QDR_WR_A: out std_logic_vector(17 downto 0)); end ADD_GEN; architecture RTL of ADD_GEN is --*********************************************** --* Components declaration --*********************************************** component ASYNR_DFF port(CLK: in std_logic; D: in std_logic; RST: in std_logic; Q : out std_logic); end component; component ASYNR_DFF18 port(CLK: in std_logic; D: in std_logic_vector(17 downto 0); RST: in std_logic; Q : out std_logic_vector(17 downto 0)); end component; component SDR_MUX18 port(CLK: in std_logic; D: in std_logic_vector(17 downto 0); CE: in std_logic; RST: in std_logic; Q: out std_logic_vector(17 downto 0)); end component; --*********************************************** --* Signals declaration --*********************************************** signal signal signal signal CLK270: std_logic; A_W_DELAY: std_logic_vector(17 downto 0); C_W_DELAY: std_logic; A_R_LATCH: std_logic_vector(17 downto 0);

signal A_W_LATCH: std_logic_vector(17 downto 0); signal QDR_A_R: std_logic_vector(17 downto 0); signal QDR_A_W: std_logic_vector(17 downto 0); begin CLK270 <= not CLK90; QDR_RD_A <= QDR_A_R; QDR_WR_A <= QDR_A_W; W_A_DELAY: ASYNR_DFF18 port map(CLK => CLK90, D => ADD_W, RST => RST, Q => A_W_DELAY); W_C_DELAY: ASYNR_DFF port map(CLK => CLK90, D => CMD_W, RST => RST, Q => C_W_DELAY); R_A_LATCH: SDR_MUX18 port map(CLK => CLK90, D => ADD_R, CE => LOCK_PLL, RST => RST, Q => A_R_LATCH); W_A_LATCH: SDR_MUX18 port map(CLK => CLK270, D => A_W_DELAY, CE => LOCK_PLL, RST => RST, Q => A_W_LATCH); R_A_BUFFER: SDR_MUX18 port map(CLK => CLK90, D => A_R_LATCH, CE => CMD_R, RST => RST, Q => QDR_A_R); W_A_BUFFER: SDR_MUX18 port map(CLK => CLK270, D => A_W_LATCH, CE => C_W_DELAY, RST => RST, Q => QDR_A_W); end RTL;

Clock Generator:

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity CLK_GENERATE is Port (CLKIN: in std_logic; RST: in std_logic; CLK0: out std_logic; CLK90: out std_logic; K_CLK: out std_logic; Kn_CLK: out std_logic; C_CLK: out std_logic; Cn_CLK: out std_logic; CLK_LOCKED: out std_logic); end CLK_GENERATE; architecture RTL of CLK_GENERATE is --*********************************************** --* Signals and constants declaration --*********************************************** signal signal signal signal signal signal signal begin CLK_0: std_logic := '0'; CLK_90: std_logic := '0'; CLK_1X: std_logic := '0'; LOCKED_DLL: std_logic := '0'; clk_buf: std_logic := '0'; clk_fbbuf: std_logic := '0'; clk_100: std_logic := '0';

clk_buf <= CLKIN; clk_fbbuf <= CLK_1X; process (RST,clk_buf,clk_100) begin if(RST = '0')then CLK_0 <= '0'; CLK_90 <= '0'; CLK_1X <= '0'; else clk_100 <= clk_buf after 2.5 ns; CLK_0 <= clk_buf xor clk_100; CLK_90 <= (clk_buf xor clk_100) after 1.25 ns; CLK_1X <= clk_buf; end if; end process; process (RST,clk_buf,clk_fbbuf) begin if(RST = '0')then LOCKED_DLL <= '0'; else

if(clk_buf = clk_fbbuf)then LOCKED_DLL <= '1'; end if; end if; end process; CLK0 <= CLK_0; CLK90 <= CLK_90; K_CLK <= CLK_90; Kn_CLK <= not (CLK_90); C_CLK <= CLK_0; Cn_CLK <= not (CLK_0); CLK_LOCKED <= LOCKED_DLL; end RTL;

Control Write:
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity CTRL_RW is Port (CMD_W: in std_logic; CMD_R: in std_logic; RST: in std_logic; W_CYCLE_GEN: out std_logic; R_CYCLE_GEN: out std_logic); end CTRL_RW; architecture RTL of CTRL_RW is --*********************************************** --* Signals and constants declaration --*********************************************** signal w_cycle: std_logic; signal r_cycle: std_logic; begin r_cycle <= '1' w_cycle <= '1' W_CYCLE_GEN <= R_CYCLE_GEN <= end RTL; when (RST = '1' and CMD_R = '1') else '0'; when (RST = '1' and CMD_W = '1') else '0'; not w_cycle; not r_cycle;

Read Burst:
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity READ_BURST is Port (C_CLK: in std_logic; CLK90: in std_logic; D: in std_logic_vector(17 downto 0); CMD_R: in std_logic; RST: in std_logic; Q0: out std_logic_vector(17 downto 0); Q1: out std_logic_vector(17 downto 0)); end READ_BURST; architecture RTL of READ_BURST is --*********************************************** --* Components declaration --*********************************************** component ASYNR_DFF port(CLK: in std_logic; D: in std_logic; RST: in std_logic; Q : out std_logic); end component; component ASYNR_DFF18 port(CLK: in std_logic; D: in std_logic_vector(17 downto 0); RST: in std_logic; Q : out std_logic_vector(17 downto 0)); end component; --*********************************************** --* Signals and constants declaration --*********************************************** signal C_CLK_BAR : std_logic; signal CLK270: std_logic; signal C_RD: STD_LOGIC; begin CLK270 <= not CLK90; C_CLK_BAR <= not(C_CLK); C_DELAY1: ASYNR_DFF port map(CLK => CLK270, D => CMD_R, RST => RST, Q => C_RD); RD_FDC_D0_C: ASYNR_DFF18 port map(CLK => C_CLK,

D => D, RST => C_RD, Q => Q0); RD_FDC_D1_C: ASYNR_DFF18 port map(CLK => C_CLK_BAR, D => D, RST => C_RD, Q => Q1); end RTL;

Write Burst:
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity WRITE_BURST is Port (CLK90: in std_logic; D0: in std_logic_vector(17 downto D1: in std_logic_vector(17 downto CMD_W: in std_logic; RST: in std_logic; LOCK_PLL: in std_logic; Q_WD_BW0: out std_logic_vector(17 Q_WD_BW1: out std_logic_vector(17 end WRITE_BURST; architecture RTL of WRITE_BURST is --*********************************************** --* Components declaration --*********************************************** component ASYNR_DFF port(CLK: in std_logic; D: in std_logic; RST: in std_logic; Q : out std_logic); end component; component SDR_MUX18 port (CLK: in std_logic; D: in std_logic_vector(17 downto 0); CE: in std_logic; RST: in std_logic; Q: out std_logic_vector(17 downto 0)); end component;

0); 0);

downto 0); downto 0));

Asynchronous D flip-flop:
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity ASYNR_DFF is Port (CLK: in std_logic; D: in std_logic; RST: in std_logic; Q: out std_logic); end ASYNR_DFF; architecture RTL of ASYNR_DFF is begin process (CLK,RST) begin if(RST = '0')then Q <= '0'; elsif(CLK'event and CLK = '1')then Q <= D; end if; end process; end RTL;

18- bit Asynchronous D flip- flop:

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity ASYNR_DFF18 is Port (CLK: in std_logic; D: in std_logic_vector(17 downto 0); RST: in std_logic; Q: out std_logic_vector(17 downto 0)); end ASYNR_DFF18; architecture RTL of ASYNR_DFF18 is begin process (CLK,RST) begin if(RST = '0')then Q <= "000000000000000000"; elsif(CLK'event and CLK = '1')then Q <= D; end if; end process; end RTL;

18- bit SDR- multiplexer:

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity SDR_MUX18 is Port (CLK: in std_logic; D: in std_logic_vector(17 downto 0); CE: in std_logic; RST: in std_logic; Q: out std_logic_vector(17 downto 0)); end SDR_MUX18; architecture RTL of SDR_MUX18 is begin process (CLK) begin if(CLK'event and CLK = '1')then if(RST = '0')then Q <= "000000000000000000"; elsif(CE = '1')then Q <= D; end if; end if; end process; end RTL;