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Lab 6

This document provides instructions for building a 4-bit binary counter using Verilog. It describes using a multiplexer (mux) and D flip-flops to count from 0000 to 1111 and then restart at 0000. Truth tables (K-maps) should be completed for each of the 4 counter bits to determine the next state logic. Modules must be created for the mux and D flip-flop. A testbench is also required to initialize the counter and demonstrate it counting up and restarting, as well as verify the D flip-flop is positive-edge triggered.

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22 views2 pages

Lab 6

This document provides instructions for building a 4-bit binary counter using Verilog. It describes using a multiplexer (mux) and D flip-flops to count from 0000 to 1111 and then restart at 0000. Truth tables (K-maps) should be completed for each of the 4 counter bits to determine the next state logic. Modules must be created for the mux and D flip-flop. A testbench is also required to initialize the counter and demonstrate it counting up and restarting, as well as verify the D flip-flop is positive-edge triggered.

Uploaded by

Swati Gupta
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Lab 6: Four-Bit Counter Basic Setup:

Mux:

D Flip-Flop (positive-edge triggered): For the D Flip-Flop you can use any structural setup you would like. It is possible to do this using only nand gates (http://www.play-hookey.com/digital/d_nand_flip-flop.html) or with only nor gates (http://www.play-hookey.com/digital/d_nor_flip-flop.html). These two representations are negative edge triggered however and you will need to add an inverter (just one inverter at the start of clock) to the clock input of these gates to make them positive edge triggered. You can also use a mix of AND, OR, NOR, NAND, etc. as long as the flip-flop is positive-edge triggered (only latches the input on a 0->1 transition) and is done in structural verilog. Assignment: You will be making a 4-bit Binary Counter that counts from 0000 to 1111 and then starts over at 0000. You will initialize the counter by setting the select to the mux to select a input of 0 (you can do this using a supply0 Gnd; instead of wire Gnd;) For each of the four inputs (D0, D1, D2, D3) you will need to do a kmap with the outputs (Q0, Q1, Q2, Q3) as the inputs and each value in the kmap is the value for the following number (D3 means the following value of D3, this is what you are solving for D3, D2, D1, D0). This means that for 0000 (Q3, Q2, Q1, Q0) the next value of Q0 is 1, for 0001, and for 0001, the next value of Q0 is 0, for 0010, and so on.

You will need a module for the D Flip-Flop and a module for the MUX. Place them in the same file as your Four-Bit Counter Module. You will need a testbench file that shows you initializing the counter, and running the counter from its initial state of 0000 to 1111 followed by 0000. The testbench also needs to show that the flip-flop you made is positive-edge triggered (0->1 transition) and not negative-edge triggered (1->0 tranisition) or level-sensitive (meaning that when the clock is either high or low the input goes directly through to the output, this is how a latch works, not a flip-flop). The only other thing I need is the four K-maps on paper for each of the four D values.

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