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Problem Solutions To Problems Marked With A in Logic Computer Design Fundamentals, Ed. 2

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67 views6 pages

Problem Solutions To Problems Marked With A in Logic Computer Design Fundamentals, Ed. 2

Uploaded by

afsanehtowhidi
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Problem Solutions to Problems Marked With a * in

Logic Computer Design Fundamentals, Ed. 2

CHAPTER 3
2000 by Prentice-Hall, Inc.

3-2.
D

T1 =
T3 =
X =
=
Y =
=

T3
X

C
B

T4

T1

BC,
T2 = AD
1
T4 = D + BC
,
T3T4
D + BC
T2T4
AD(D + BC) = A BCD

T2

Y
X

1
1

X
0
0
0
0
1
1
1
1

1
Z

XZ + ZY

X
Z

Y
0
0
1
1
0
0
1
1

Z
0
1
0
1
0
1
0
1

T1
1
1
1
1
1
1
0
0

T2
1
1
1
1
0
0
1
1

T4
1
0
1
1
1
1
1
0

T5
1
0
1
1
1
0
1
0

F
0
1
0
0
0
1
0
1

T2

X
F

Z
Y

T3
1
1
0
0
1
1
1
1

T4

T1

Y
Z

T5

T3

3-3.
X
0
0
1
1

X
T2
F

T1

T3

Y
0
1
0
1

T1
1
0
0
0

T2
0
1
0
0

T3
0
0
1
0

F
1
0
0
1

3-6.
A

M = AS + BS

T1 = ZY + ZY
Y
X

Z
Y

A
S
B

A
S
B

F = YX + T1X

= YX + X(ZY + ZY)

= XY + XYZ + XYZ

T1

X
Z

A
S
B

G =
M

T1X + ZX

= XZ + X(Z + Y)(Z + Y)

XZ + X(YZ + Y Z) =

XZ + XYZ + X Y Z

Problem Solutions Chapter 3

3-11.
C

1 1
1

D
F = AB + AC

3-13.
AC

AB

AB

A D

ABD BCD ABC ACD ACDACD ABC ABC ABD ABCD

3-15.
C
1
1
A

1
1

1
1

X X X X
1 1 X X

C
1 1

X X X X
1

C
1
1

B
A

1 X X

1
1 1

X X X X
1

b = B + C D + CD

c=B+C+D

X X X X

X X

1 X X
D

C
1 1

X X X X
1 1 X X

D
e = B D + CD

B
A

1 X X

1
X X X X

f = A + BD + BC + C D

g = A + CD + BC + BC

3-20.
D3
0
X
X
X
1

D2
0
X
X
1
0

D1
0
X
1
0
0

D0
0
1
0
0
0

A1
X
0
0
1
1

A0
X
0
1
0
1

V = D0 + D1 + D2 + D3

V
0
1
1
1
1

A0

A1

D2
X

D2
X

1 1

D3

A0 = D1 + D0 D2
A1 = D0 D1

1
D1

D1
D0

D0

d = BCD + A + B D + BC + CD

1
1

X X X X

C
1

X X

a = A + C + BD + B D

C
1

D3

Problem Solutions Chapter 3

3-25.
8/1 MUX

D(0-7)

D(0-7) Y
0

A(0-2)

A(0-2)
8/1 MUX

D(8-14)

D(0-6) Y
0
D(7)
A(0-2)

A(3)

3 OR gates

3-29.
A
0
0
0
0
0
0
0
0

B
0
0
0
0
1
1
1
1

C
0
0
1
1
0
0
1
1

D
0
1
0
1
0
1
0
1

F
0
1
D
0
1
1 CD
0
0
0

A
1
1
1
1
1
1
1
1

B
0
0
0
0
1
1
1
1

C
0
0
1
1
0
0
1
1

D
0
1
0
1
0
1
0
1

F
0 CD
0
0
1
1 +V
1
1
1

C
D
C
D

A
B
D

4/1 MUX
A0
A1
0
1
Y
2
3

+V

3-35.
C 1 = T 3 + T 2 = T 1 C 0 + T 2 = A 0 B 0 C 0 + A 0 + B 0 = ( A 0 + B 0 )C 0 + A 0 B 0 = ( A 0 B 0 + C 0 ) ( A 0 + B 0 )
C1 = A0 B0 + A0 C0 + B0 C0
S0 = C0 T4 = C0 T1 T2 = C0 A0 B0 ( A0 + B0 ) = C0 ( A0 + B0 ) ( A0 + B0 ) = C0 A0 B0 + A0 B0
S0 = A0 B0 C0

3-38.
1 0 0 1 1 0 0 0 1 0 0 1 1 0 0 1 1 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0
0 1 1 0 0 1 1 1 0 1 1 0 0 1 1 0 0 1 0 1 0 0 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1
0 1 1 0 1 0 0 0 0 1 1 0 0 1 1 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0

3-41.
+43

0101011

43
+(17)

= 26

-17

1101111

-43

1010101

+17

0010001

0101011
1101111
10011010

43

0011010
1010101

+ 17

0010001

= 26

1100110

Problem Solutions Chapter 3

3-45.
a)
b)
c)
d)
e)

3-49.

S
0
0
1
1
1

A
0111
0100
1100
0101
0000

B
0110
0101
1010
1010
0010

C4
0
0
1
0
0

S3 S2 S1
1 1 0
1 0 0
0 0 1
1 0 1
1 1 1

S0
1
1
0
1
0

78430258 98989899 09580089 99999999

3-52.
BCD
0
1
2
3
4
5
6
7
8
9

EXCESS-3
A
0
0
0
0
0
0
0
0
1
1

B
0
0
0
0
1
1
1
1
0
0

C
0
0
1
1
0
0
1
1
0
0

D
0
1
0
1
0
1
0
1
0
1

E
1
1
0
0
0
0
0
0
0
0

F
0
0
1
1
1
1
0
0
0
0

G
0
0
1
1
0
0
1
1
0
0

H
1
0
1
0
1
0
1
0
1
0

0
1
2
3
4
5
6
7
8
9

A
0
0
0
0
0
1
1
1
1
1

H = D

H = D

G = C

G = C

F = BC + BC

F = B

E = ABC

B
0
1
1
1
1
0
0
0
0
1

C
1
0
0
1
1
0
0
1
1
0

D
1
0
1
0
1
0
1
0
1
0

E
1
1
1
1
1
0
0
0
0
0

E = A

Gates:

Gates:

Literals:

Literals:

3-55.

3-58.
X1
X2

N1
N2

N6

N3

N4

X3
N5
X4

F
1
0
0
0
0
1
1
1
1
0

G
0
1
1
0
0
1
1
0
0
1

H
0
1
0
1
0
1
0
1
0
1

Problem Solutions Chapter 3

3-62.
From 3-2: F = X Z + Z Y
Using Nand Gates:
...
signal T: std_logic_vector(0 to 2);
begin
g0: NOT1 port map (Y, T(0));
g1: NAND2 port map (X, Z, T(1));
g2: NAND2 port map (Z, T(0), T(2));
g3: NAND2 port map (T(1), T(2), F);
end

3-66.

3-69.

3-72.
X1
X2

N1
N2

N6

N3

N4

X3
N5
X4

Problem Solutions Chapter 3

3-76.
//Fucntion F from problem 3-2 = X Z + Z Y
module cicuit_3_76(X, Y, Z, F);
input X, Y, Z;
output F;
assign F = (X & Z) | (Z & ~Y);
endmodule

3-80.

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