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Wired-Or INT Lines

The document describes an open collector "wired-OR" circuit with two chips that can interrupt a microprocessor through a shared interrupt line. When either chip asserts an interrupt, its output goes low, pulling the shared interrupt line low. Because the outputs are open collector, the chips do not conflict even when asserting interrupts simultaneously.

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116 views1 page

Wired-Or INT Lines

The document describes an open collector "wired-OR" circuit with two chips that can interrupt a microprocessor through a shared interrupt line. When either chip asserts an interrupt, its output goes low, pulling the shared interrupt line low. Because the outputs are open collector, the chips do not conflict even when asserting interrupts simultaneously.

Uploaded by

api-3838221
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Here is a sample circuit with open collector “wired-OR” interrupt lines...

Either Chip A or Chip B can interrupt the microprocessor. Both interrupt lines come in on the same IRQ line.
Because both are open-collector and each has a pull-up resistor, no “bus fight” will occur.

Pullup resistor

Chip A INT/ Chip B INT/

uP
C C
B B
Chip A Chip B
INT/

E E
When no interrupts are asserted, all INT/ lines are HIGH.
This is because neither BJT is conducting – no current
flows through the BJT or the pullup resistor. That means
the voltages at the collectors are HIGH.
These 4 scenarios can happen...
Consider the second row, when Chip A asserts it’s
Chip A INT/ Chip B INT/ INT/
interrupt. The BJT turns ON and conducts, so
No one interrupts the uP HIGH HIGH HIGH Chip A INT/ goes LOW. This pin is also connected to the
uP INT/ and Chip B INT/. That means the voltage at all
Chip A interrupts the uP LOW HIGH LOW those places is LOW.
Chip B interrupts the uP HIGH LOW LOW
Both Chip A and B interrupt the uP LOW LOW LOW So Why isn’t there a short circuit at Chip B, because
Chip B’s INT/ line is high?

The critical point is that Chip B is NOT CONDUCTING.


It looks like a high impedance open circuit to the rest of
the world. So there is NO short circuit to ground through
the Chip B BJT. That means point C can be pulled low
EXTERNALLY by Chip A, and the current flows through
both resistors and then through the Chip A BJT only.

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