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Sap 2 Architecture

DOWNLOAD HERE: http://adf.ly/aHggp ====== Simple-As-Possible 2 CENGO3 - Computer System Architecture

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Yzza Veah Esquivel
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8K views7 pages

Sap 2 Architecture

DOWNLOAD HERE: http://adf.ly/aHggp ====== Simple-As-Possible 2 CENGO3 - Computer System Architecture

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Yzza Veah Esquivel
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© Attribution Non-Commercial (BY-NC)
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n|@ SAP-2 SAP-1 is a computer because it stores a program and data before calculations begin: then it automatically carries aut the progam instructions without human intervention. And yet, SAP-L is a primitive computing machine. It compares to a modern computer the way a Neanderthal human would compare to a modern person. Something is missing, some thing found in every modem computer. SAP-2 is the next step in the evolution toward modem computers because it includes jump instructions. These new instructions force the computer to repeat or skip part of program. As you will discover, jump instructions open up 2 whole new world of computing power 11-1 BIDIRECTIONAL REGISTERS To reduce the wiring capacitance of SAP-2, we will run aly ont set of wires between each register and: the bus. Figure 11-1a shows the idca. The input and owlput pins are shorted; only onc group of wires is connected to the bus Dots this shorting the input and output pins ever cause trouble? No. During a computer run, either LOAD or ENABLE may be active, but not both at the same time. An active LOAD means that a binary ward flows from the bus to the register input; during a load operation, the output lines are floating. On the other hand, an active ENABLE means that a binary word. flows from the register to the bus, in this case, the input fines float, ‘The IC manufacturer can internally connect the input and ‘output pins of a three-state register. This not only reduces the wiring. capacitance; it also reduces the number of 1/0 ns. For instance, Fag. 11-16 has four 1A pins instead of ight. Figure 1 -Ic ix the symbol for a three-state register with internally connected input and output pins. The double- headed arrow reminds us that the path is bidirectional; data can move either way 11-2 ARCHITECTURE Figure 11-2 shows the architecture of SAP-2. All register onipats fo the W bus are three-state; those not connected to the bus are two-state, As before, the controlier-sequencer sends control signals {not shown) to cach register. These contiol signals load, enable, or otherwise prepare the register for the next positive clock edge. A brief description of each box is given now Input Ports SAP-2 has two input ports, numbered 1 and 2..A’hexade- cimal keyboard cncoder is comected to port 1. Ht allows Us to enter hexadecimal instructions and data through pot 1, Notice that the hexadecimal keyboard enceder sends a READY signal to it 0 of port 2. This signal indicates when the data in port | is valid ‘Also notice the SERIAL 1M signal going to pin 7 of por 2. A later example will shew you how to convert serial input data to parallel dats Program Counter This time, the program counter has 16 bits; therefore, it can count fram PC = 0000 0000 10000 0000 to Pe = Wen Le This is equivalent to OO00H to FFFFH, or decimal @ to 65,535, ‘A low CLR signal resets the PC before each computer run; so the data processing starts with the instruction stored in memory location O000H. 473 on— enanis — Fig. 11-1 Bidirectional register ‘MAR and Memory [During the fetch cycle, the MAR cecetves | f-bit adklsesses roma the program coupes. ‘The two-state MAK output then addresseé the desired memory hocalion. The memory thas a 2K ROM with adkiessex of 0000H to OTFFH. This ROM ‘contains a program called! x monitor that intialiaes the Sc eco, er toed pt, se forth. The reat of the memory is 2 62K RAM with addresses fm ORDOEL toe FFFFH Memory Data Register ‘The memory data register (MDR) is an #-bit buffer register, ‘ts ouput kets up the RAM. The mcmory data mpisict receiver dita fit the bus before u wise operation, and it ‘send. data to the bus after a read operation. ‘Instruction Register ‘Became SAP-2 has move fnstructioas than SAP-1, we will Use 8 bits for the ap code rather than 4 An 8.bit op cade an accommodate 256 instructions. SAP-2 has amly 42 174. digit Computer Electronics ain illite ‘structions, 40 there will be 0 problem covbing them with ‘bits Using an &-bit op cove also allows upward compat ibulity with the S080/R08S instruction set because itis based on an bit op code As mentioned earlice, all SAP instructions are identical with AOBOMSORS instructions, Controtler-Sequencer ‘The controller-sequencer produces the control words or rmicroinstructions that coordinate and direct the rest of the computer. Because SAP-2 has'a bigger instruction set, the controller-sequerncer has tare handwage. Although the CON word is bigger, the idea ts the same: the contol word or microinstruction determine’:how the segisters react to the next positive clock edge Accumulator The two-state oulpat of the accurmulator goes Wo the: ALU; the shree-state output to the W bus. Therefore, the S:bit word in the accumutator continuously drives the AL, Bat thes same word appears om the bus only when F, is active ACKNOWLEDGE —e} Fig. 11-2 SAP-2 block architecture ALU and Flags Standard AILUs are commercially available as integrated cirewits. These ALUs have 4 or more control bits that determine the arithmetic or logic aperation performed on words A.and B. The ALU used in SAP-2 includes arithmetic and logic operations In this book a flag is & fip-fop that keeps track of a changing condition during a computer run. The SAP-2 computer has two flags. The sign flag is set when the accumulator contents become negative during the execution ACCUMULATOR ‘of some instructions. The zero flag 1s set when the accu ‘tulator contents become zero, TMP, B, and C Registers Instead of using the B register to hold the deta being addled ox subtracted from the accumulator, 3 temporary (TMP) register ts used. This allows us more freedom in using the Bregister. Besides the TMP and B regisicrs, SAP-2 includex aC reguster. This gives us mote flexibility in moving, data during. a computer ran, Chopteri1 sepa 175

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