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How To Generate A SDF File For A Single Module

The document discusses generating an SDF file for only the digital block of a mixed-signal design in Cadence FE version 7.1. It describes trying to save the netlist and generate SPEF files for just the digital block module, but FE is unable to generate parasitics for a single instance. An alternative proposed is to use partitioning in FE to isolate the digital block during placement and routing, then incorporate it back into the top-level design after timing closure. The person was able to generate the SDF files using ETS instead.

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Murali
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223 views

How To Generate A SDF File For A Single Module

The document discusses generating an SDF file for only the digital block of a mixed-signal design in Cadence FE version 7.1. It describes trying to save the netlist and generate SPEF files for just the digital block module, but FE is unable to generate parasitics for a single instance. An alternative proposed is to use partitioning in FE to isolate the digital block during placement and routing, then incorporate it back into the top-level design after timing closure. The person was able to generate the SDF files using ETS instead.

Uploaded by

Murali
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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ow to generate a SDF file for a single module?

Reply Hi, Currently I am working on the physical implementation of a simple mixed-signal design. The problem is that all testcases for functional verification were written only for the digital block (I/O and analog blocks were not considered). Therefore I need to generate the verilog and SDF files only for the digital block. How to do this in FE (version 7.1)? For the verilog file, I tried the command "saveNetlist -module xyz.v" but this not work recursively into the submodules. I tried also to generate the SPEF files for the digital block and so use the ETS to generate the SDF files, but it seems FE is not able to generate a parasitics file for an instance/module. Can anyone help me? Thanks, Cristiano.

Originally posted in cdnusers.org by clsantos


Post Points: 0

Tue, Feb 12 2008 8:55 AM archive RE: How to generate a SDF file for a single module? Reply When you floor-plan the chip in FE, Is it possible to use "partition" to isolate your digital block from the others?, if so, you get a work-around for the issue: you can place&route the digital partition first (separately), create .v and spef file for the partition and get time closure, then, push it back into top (chip) level and finish chip route. I did this way for a Joined on Fri, Jul mixed-signal block and FE worked pretty well for me. Tongju 4 2008 Posts 88 Originally posted in cdnusers.org by Tongju Points 4,070

Post Points: 0

Tue, Feb 12 2008 10:15 AM archive RE: How to generate a SDF file for a single module? Reply Hello Tongju, As the physical implementation was done I preferred to write out set_load and set_resistance files (rcout -setload xyz.load -setres xyz.res) and edit them by hand to point directly to the target module. So I Joined on Fri, Jul generated the SDF files using ETS and it seems they are ok. In the next designs I will follow your suggestion. Thanks for your help.

4 2008 Posts 88 Points 4,070

Regards, Cristiano.

Originally posted in cdnusers.org by clsantos

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