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Membangun Finite State Machine (FSM) Dengan Pemodelan Behavioral Dalam VDHL

This document discusses building finite state machines (FSM) in VHDL. It provides examples of a 1Hz clock generator, a sequential logic design, a mod-4 up counter, and the behavioral design of a mod-4 counter in VHDL. It also describes a 4-to-1 multiplexer and shows how to multiplex a 7-segment display using a hex-to-7-segment decoder, 4-to-1 multiplexer, and 2-bit counter.

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44 views5 pages

Membangun Finite State Machine (FSM) Dengan Pemodelan Behavioral Dalam VDHL

This document discusses building finite state machines (FSM) in VHDL. It provides examples of a 1Hz clock generator, a sequential logic design, a mod-4 up counter, and the behavioral design of a mod-4 counter in VHDL. It also describes a 4-to-1 multiplexer and shows how to multiplex a 7-segment display using a hex-to-7-segment decoder, 4-to-1 multiplexer, and 2-bit counter.

Uploaded by

argawahyumianto
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Finite State Machine dalam VHDL

Membangun Finite State Machine (FSM) dengan pemodelan behavioral dalam VDHL.

1Hz Clock Generator


entity c1hz is port( clk:in std_logic; clkout:out std_logic); end c1hz; architecture behavior of c1hz is begin process(clk) variable cnt : integer range 0 to 50000000; begin if(clk'event and clk='1') then if(cnt=50000000)then cnt := 0; clkout <= '1'; else cnt := cnt+1; clkout <= '0'; end if; end if; end process; end behavior; 2

Sequential Logic Design


Q0(next) = D0 = Cnt Q0 Q1(next) = D1 = Cnt'Q1 + CntQ1'Q0 + CntQ1Q0' Present State Q1Q0 00 01 10 11 Next State Q1(next)Q0(next) Cnt=0 Cnt=1 00 01 10 11 01 10 11 00
Cnt=0 Cnt=0 Cnt=1

Q1Q0=00
Cnt=1

Q1Q0=01
Cnt=1

Q1Q0=11
Cnt=0

Cnt=1

Q1Q0=10
3

Cnt=0

Mod-4 Up Counter
Cnt

D0

Q0

Q0'

7
7-seg Decoder

0 0
D1 Q1

Clk

Q1'
4

Mod-4 Counter Behavioral Design (1)


Entity FSM is port( Clk, Cnt : in std_logic; O : out std_logic_vector(1 downto 0)); end FSM; Architecture behavior of FSM is type State_type is (State0, State1, State2, State3); signal State : State_type := State0; -- Initialization begin process (Clk) begin if rising_edge(Clk) then case State is when State0 => O <= "00"; if Cnt = '1' then State <= State1; else State <= State0; end if;

Cnt=0

Cnt=0 Cnt=1

Q1Q0=00
Cnt=1

Q1Q0=01
Cnt=1

Q1Q0=11 Cnt=1 Q1Q0=10


Cnt=0 Cnt=0
5

Mod-4 Counter Behavioral Design (2)


when State1 => O <= "01"; if Cnt = '1' then State <= State2; else State <= State1; end if; when State2 => O <= "10"; if Cnt = '1' then State <= State3; else State <= State2; end if; when State3 => O <= "11"; if Cnt = '1' then State <= State0; else State <= State3; end if; when others => end case; end if; end process; end behavior;

Cnt=0

Cnt=0 Cnt=1

Q1Q0=00
Cnt=1

Q1Q0=01
Cnt=1

Q1Q0=11 Cnt=1 Q1Q0=10


Cnt=0 Cnt=0
6

4-to-1 MUX
I3 I2 I1 I0 A B
3 2 1 0

I3 A B

I2

I1

I0

Selector F A B 0 0 1 1 0 1 0 1 F I0 I1 I2 I3

4-to-1 MUX
F = (not A and not B and I0) or (not A and B and I1) or (A and not B and I2) or (A and B and I3); Sel <= A & B; case Sel is when 00 => F <= I0; when 01 => F <= I1; when 10 => F <= I2; when 11 => F <= I3; end case;

I3 A B

I2

I1

I0

F Sel <= A & B; F <= I0 when Sel = 00 else I1 when Sel = 01 else I2 when Sel = 10 else I3;
8

Multiplexed 7-Segment Display


Hex-to-7-seg Decoder

4
Decoder 4-to-1 Mux 4 4 4 4 2-bit Counter

D3 D2D1 D0
Clock Divider

50Mhz

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