ARM Programming and Optimisation Techniques

Vijaya Sagar Vinnakota ([email protected])

Wipro Technologies

Abstract necessarily single-cycle) instruction

architecture commonly seen in all
This tutorial paper presents some RISC processors. It uses an instruction
optimisation techniques for pipeline to improve the processor
programming with ARM processors, performance.
addressing both memory (footprint)
and execution time optimisation. For Since pure RISC implementations are
purposes of illustration, the ARM7TDMI prone to induce program size inflation,
is chosen as a representative of the the ARM designers chose to borrow a
ARM family. The 32-bit ARM few CISC concepts in carefully chosen
instruction set is chosen as the vehicle areas. For instance, multiple load /
to convey various optimisation store, stack addressing and auto-
techniques while programming indexing are all new to the RISC
references to the 16-bit Thumb philosophy. At the same time, a few
instruction set are minimal. RISC concepts were left out of the
architecture for power, die-size and
The tutorial does not assume prior performance considerations. For
knowledge of the ARM architecture. instance, register-files and single cycle
Experience in programming with any execution have been dropped off the
RISC assembly language makes ARM architecture.
understanding easier, though.
For the footprint conscious system
designers and developers, the ARM
Keywords architects provided a novel solution by
way of a restricted 16-bit instruction
ARM, RISC, CISC, footprint, Thumb, set (as against the standard 32-bit)
pipeline, stall, auto-indexing, profiling, known as ‘Thumb’. While a 50%
loop unrolling reduction program size over ARM
instruction set may not be feasible, the
gains are seldom less than 30%.
Introduction
These novel designs in the ARM
From being the first commercial architecture resulted in demonstrated
implementation of RISC architecture, gains such as die-size reduction, low
the ARM processor family has come a gate-complexity, high MIPS/watt and
long way over the past decade in increased code density.
becoming the primary choice for low-
power (yet powerful) embedded
applications. The ARM architecture
ARM follows the standard load-store To write efficient programs, a
(read as ‘no memory-memory thorough understanding of the target
operations’) and fixed-length (not processor architecture is a
ARM programming and optimisation techniques 2

prerequisite. As shall be seen in the processor performance and utilisation

course of the tutorial, even the best of of its functional units.
the compilers have their limitations.
There is always scope for improvement I#
in the code that they generate, for 1 F D E
they are tools meant for generic use.
2 F D E
They know very little (if at all) of the
specific program instance to be
3 F D E
compiled. Only the programmer1
knows his program best – and hence 4 F D E
stands the best chance of converting it
into code that is most optimised for Cycles (time) ->
the target processor, provided its Fig.1 – steady state ARM pipeline
architecture is well understood. With
F: Fetch D: Decode E: Execute
this as the motivation, let us take a
In the fetch stage, the instruction is
quick tour of the ARM architecture.
brought into the pipeline from memory
(cache / ROM / RAM).
Building blocks
An ARM processor is made up of the In the decode stage, the instruction is
following blocks: decoded and control signals are made
o The register bank – contains 37 ready for activities such as fetching
registers2 visible to the the next-but-one instruction and
programmer memory address calculation.
o The barrel shifter – for shifting
and rotating data In the execute stage, the instruction
o The ALU takes effect, primarily in the form
o The instruction decoder modification to one or more of the
o The control logic – for registers (even in the case of a
generating necessary signals load/store instruction as memory
such as memory-read/write interaction is through the invisible
o The address and data registers address and data latch registers).
- to serve as latches (these are
not ‘programmable’) Fig.1 depicts an ideal case, steady
o The CP15 – ARM system control state scenario for the ARM pipeline,
coprocessor which serves, where in each instruction takes exactly
among other things, as an MMU three cycles to complete (i.e., each
and cache controller stage of the instruction needs exactly
one cycle). For example, consider a
Some of these blocks are of direct simple ‘add’ instruction:
interest to the programmer and would
be discussed in greater detail later. ADD r0, r0, r1 ; r0 = r0 + r1

Pipelined execution This instruction goes through the

The ARM architecture has a 3-stage 3 following stages:
instruction pipeline for improving the
1. Fetch the instruction from
memory
2. Decode the instruction and
1
Though referred to only as a male - purely for identify that it is an ADD
writing convenience, the author acknowledges
many a fine female programmer, right since the
3
days of Lady Ada. Since ARM8, pipelining schemes other than the
2
20 of these registers are banked and are not simple “fetch-decode-execute” have been
directly visible to the programmer implemented
ARM programming and optimisation techniques 3

instruction (of type register- understandable because #1 would

register) ‘see’ the value of PC in its ‘execute’
3. Pass the current values of the stage, by which time/cycle the PC has
operand registers (r0 and r1) to been incremented twice (for fetching
the ALU, obtain their sum and #2 and #3). Thus, PC runs ahead of
store it in the destination register the current instruction and holds the
(r0) address of the next but one
instruction. Assembly language
However, this need not always be the programmers must factor this while
case. For example, consider the case directly accessing the PC value.
of a ‘load’ instruction:
Pipeline stall: Instructions such as
LDR r0, [r1], #0 ; r0 = *r1 load/store that take multiple cycles to
complete the ‘execute’ stage adversely
This instruction goes through the affect the pipeline throughput. This is
following stages: due to the fact that such instructions
occupy the processor functional units
1. Fetch the instruction from for more than one cycle in the
memory ‘execute’ stage, thus stopping the
2. Decode the instruction and progress of subsequent instructions in
identify that it is an LDR the pipeline. This condition is
instruction described as a stall in the pipeline.
3. Compute the memory address
which contains the data to be I#
loaded, using the base register 1 F D E
(r1) and offset (#0)
4. Fetch the data word from memory 2 F D E1 E2 E3 load
into the data latch register
3 F D E
5. Transfer the data word from the
latch register to the destination
4 F D E
register (r0)
5 F D E
It can be seen that ‘add’ takes 1-cycle Fig.2 – ARM pipeline with stalls
for its ‘execute’ stage whereas ‘load’
needs 3-cycles for the same (shown in Fig.2 depicts a stall condition when a
a grey shade). See also, fig.2. ‘load’ (#2) is mixed with simple
instructions such as ‘add’ and ‘sub’.
The ARM instruction set designers ‘En’ stands for cycle-#n in the
have made good use of this extra execution stage of the load instruction
latency by adding auto-indexing described in detail earlier.
capability to ‘load’/‘store’ instructions.
Since the ALU and barrel-shifter would The decode stage of the subsequent
otherwise be idle during the data-word instruction (#3) cannot happen along
cycle (#4) of the ‘execute’ stage, they with E1 since the decode logic is
can be used to add an offset (index) to occupied for generating data-fetch
the base register. This feature is related control signals.
frequently used in the programs
illustrated in this paper. Instruction#3 cannot enter its decode
stage along with E2 either, but for a
PC runs ahead! If instruction #1 in different reason altogether. For even if
fig.1 were to refer to PC, it would find it were allowed, the control signals
that the register value is not the same generated cannot be used in the
as the instruction address. This is immediate next cycle because of E3
ARM programming and optimisation techniques 4

being in progress. Another way to view decode / execute stage) are discarded
this is to understand that during E2, without getting executed.
the control logic was busy generating
signals for transferring data from the Thus, branch instructions impose a
latch register to its destination in the significant overhead and disrupt the
register bank. smooth flow in the pipeline. This is not
to say that branches should not be
For obvious reasons, instruction #4 used (for it is impractical), but only to
also experiences the effects of this emphasise the fact that knowledge of
stall. the pipeline behaviour guides a better
program design, which leads to lesser
Pipeline breaks: Another throughput number of branches.
limiting condition arises when a branch
instruction enters the pipeline.
ARM instruction set

The ARM instruction set can be

I#
organized into the following broad
1 F D E1 E2 E3 branch
categories5:
2 F D E 1. Data transfer instructions
2. Data processing instructions
3 F D E 3. Branch instructions
4. Coprocessor instructions
4 F D E 5. Miscellaneous instructions

5 F D E The purpose of this tutorial is served

Fig.3 – ARM pipeline with a branch
better if, instead of exhaustively listing
all the instructions, the most
As shown in fig.3, a branch instruction
frequently used ones are explained in
(#1) takes three cycles in its ‘execute’
the context of common programming
stage of the pipeline. This view holds
tasks.
both for unconditional and condition-
satisfied branch instructions.

In E1, the branch target address is ARM assembly examples

computed and fed to the addressing
logic. In E2, if a ‘branch and link’ has Simple arithmetic
been requested, the link register is
updated with the return address. int a, b, c;
During the same time, the branch
target instruction is fetched into the Say, variables a, b and c are in
pipeline. In E34, as the pipeline registers r0, r1 and r2 respectively.
continues to be filled, the link register
is adjusted to offset the PC-run-ahead Addition:
effect. a = b + c;
ADD r0, r1, r2 ; r0 = r1 + r2
Instructions #2 and #3 (which entered
the pipeline as #1 was still in its a += b;
ADD r0, r0, r1

4 5
E3’s primary purpose is to generate control This categorisation is not from the instruction
signals for fetching instruction #5. Then on, the set design viewpoint but only from that of an
pipeline is back to steady state. assembly programmer.
ARM programming and optimisation techniques 5

Subtraction: register) – Negative, Zero, Carry,

a = b – c; oVerflow. Some of these codes are:
SUB r0, r1, r2 ; r0 = r1 – r2
code description condition
a -= b; MI minus N is set
SUB r0, r0, r1 EQ equals [to zero] Z is set
LO unsigned lower C is clear
a = 25 – b;
VC no overflow V is clear
RSB r0, r1, #25 ; r0 = 25 – r1
; RSB = reverse subtract
These two letter condition codes are to
be suffixed to an instruction mnemonic
Multiplication:
a = b * c; to affect the desired conditional
MUL r0, r1, r2 ; r0 = r1 * r2 execution.

a *= b; Now, if such were indeed the case,

MUL r0, r0, r1 ; illegal ! how is it that the arithmetic examples
listed earlier used no such suffixes?
MUL cannot be used with the same The answer lies in the default condition
register for the multiplicand and the code – AL (always) which implies
product. In practice, this restriction execution irrespective of the condition
does not pose a significant handicap as flags’ status. The net effect is one of
multiplication is commutative. The unconditional execution! The previous
instruction can simply be re-written examples could as well have been
as: written as:

MUL r0, r1, r0 ; r0 = r1 * r0 ADDAL r0, r1, r2 ; r0 = r1 + r2

SUBAL r0, r1, r2 ; r0 = r1 – r2
MULAL r0, r0, r1 ; illegal ;^)
Multiply and accumulate:
a += b * c;
MLA r0, r1, r2, r0 However, for the sake of readability,
; r0 = r1 * r2 + r0 AL is better left unspecified.

While the 15 condition codes6 alone

Conditional execution – a lend a lot of utility to the ARM
instruction set, the flexibility allowed in
digression setting the CPSR flags (N, Z, C, V)
combined with persistence of those
Before going through any further flag values (until further modification)
instructions, let us take a quick look at makes conditional execution all the
conditional execution – arguably the more powerful. As a rule:
most powerful feature in the ARM
instruction set. An instruction can be conditionally
executed, based on the CPSR flags set
Every single ARM instruction can be in a previous (already executed)
executed conditionally. In fact, every instruction after zero or more
single ARM instruction is executed intermediate instructions that have not
conditionally. To achieve this, the modified the flags.
instruction set designers have set
aside 4-MSbits out of the 32-bit This implies that unlike instructions of
instruction word for specifying a many other processors, most ARM
condition code. This condition code is
related to the status of four flags in 6
the CPSR (current program status Of the 16 possible values, the code ‘1111’
(binary) is reserved.
ARM programming and optimisation techniques 6

instructions have a choice of not

disturbing the CPSR flags. By default, if (a == 13)
but for a few instructions such as CMP if (b == 12)
(compare) and TST (test), ARM c = c & 74;
instructions do not modify the flags. In TEQ r0, #13
order to affect such modification, the TEQEQ r1, #12
letter ‘S’ must be suffixed to ANDEQ r2, r2, #74
instruction mnemonics.

Armed with this knowledge of Memory access

conditional execution, let us move
ahead with further code sequences Let us assume the following
and programming examples. definitions:

int *pa = &a, *pb = &b;

Data processing
And also that ‘pa’ and ‘pb’ are held in
Moving data: r3 and r4 respectively.
a = b;
MOV r0, r1 ; r0 = r1 Loads:
b = *pa;
a = b << 5; LDR r1, [r3] ; r1 = *r3
MOVS r0, r1, LSL #5
; r0 = r1 << 5 c = *(pb + 1);
; ‘S’ forces flags update LDR r2, [r4, #4]
; r2 = *(r4 + 4)
a = ~b; ; sizeof(int) = 4
MVN r0, r1 ; r0 = ~r1 ; pre-indexing

Logical operations: c = *pb++;

a = b | c; LDR r2, [r4], #4;
ORR r0, r1, r2 ; r0 = r1 | r2 ; r2 = *r4, r4 += 4
; auto (post) indexing
a = b & ~c;
BIC r0, r1, r2 ; r0 = r1 &~r2 c = *++pb;
; BIC = bit clear LDR r2, [r4, #4]!
; r2 = *(r4 + 4), r4 += 4
; auto (pre) indexing
Comparators: ; ‘!’ to update index r4
(a </>/==/<=/>= b);
CMP r0, r1
; CMP updates CPSR flags based Stores:
; on the result of ‘r0 – r1’ *pb = a;
STR r0, [r4] ; *r4 = r0
if (a > 13)
a = b << c; pa[1] = c;
CMP r0, #13 ; r0 - 13 STR r2, [r3, #4]
MOVGT r0, r1, LSL r2 ; *(r3+4) = r2
; GT: greater than
*pa++ = c;
(a == b); STR r2, [r3], #4
TEQ r0, r1 ; *r3 = r2, r3 += 4
; TEQ updates CPSR flags based
; on the result of ‘r0 ^ r1’ *++pa = c;
ARM programming and optimisation techniques 7

STR r2, [r3, #4]! Miscellaneous

; *(r3 + 4) = r2, r3 += 4
No Operation:
NOP ; typically a ‘MOV r0, r0’
Branching
Unconditional branch: Load an address:
goto label_1; pa = &a;
B label_1 ADR r3, a
; |label_1 – PC| <= 32MB ; ‘a’ being the label for the
; variable’s storage
Function call: ;
foo(); ; ADR is a pseudo-instruction
BL _foo ; that translates to a ADD/SUB
; branch and link(L) ; PC/register relative address
; r14 = return addr, goto _foo
Swap:
Conditional branches: c = *ap; *ap = b; b = c;
if (!a) /* swap ‘*ap’ and ‘b’ */
goto label_1; SWP r1, r1, [r3]
TEQ r0, #0 ; SWP swaps data between a
BEQ label_1 ; register and a memory location

if (b & c)
foo();
TST r1, r2
BLNE _foo
; TST is similar to ANDS, but
; does not modify any register

Optimisation techniques
Here on, program fragments in C are listed alongside their equivalent ARM assembly
code. Concepts specific to the ARM instruction set and relevant optimization
techniques are introduced at appropriate places.

Note:
All ARM assemblers by convention use r13 as the stack pointer. The architecture
supports r14 as the link register.

A simple search example:

ARM programming and optimisation techniques 8

#include <stdio.h>

int main(void)
{
int a[10] = {7, 6, 4, 5, 5, 1, 3, 2, 9, 8};
int i;
int s = 4;

for (i = 0; i < 10; i++)

if (s == a[i])
break;

if (i >= 10)
return 1; /* 1 => not found */
else
return 0; /* 0 => found */
}

This C-program hand-translated to assembly, without any optimisation may be

similar to the listing given below.

.text
; Program labels are terminated by ‘:’ for readability
; Stack ‘grows’ downward, caller saves registers.

1 ; Make 48bytes of space for a[], i and s on the stack

ADD r13, r13, #-48 ; r13 is SP

; a[]: (sp + 12) .. (sp + 48), i: (sp + 8), s: (sp + 4)

; Assume that a run-time library routine initialises a[] and s with

; the required values

MOV r0, #0 ;
STR r0, [r13, #8] ; for (i = 0; ...)
2 loop_start:
; loop entry condition check
LDR r0, [r13, #8] ; load ‘i’
CMP r0, #10 ; for (...; i < 10; ...)
BGE loop_end
3 LDR r1, [r13, #4] ; load ‘s’ (already initialised to 4)

; get a[i]
MOV r2, #4 ; sizeof(a[i])
MUL r3, r0, r2 ; r3 = i * 4 (serves as an index in a[i])
ADD r3, r3, #12 ; adjust r3 relative to base of a[]
LDR r4, [r13, r3] ; r4 = *(r13 + r3) i.e., a[i]

TEQ r1, r4
BEQ loop_end ; if (s == a[i]) break;

ADD r0, r0, #1 ; for (...; i++)

4
ARM programming and optimisation techniques 9

STR r0, [r13, #8] ; update i

B loop_start ; next iteration

5 loop_end:
LDR r0, [r13, #8] ; load ‘i’
CMP r0, #10
BGE return_1 ; if (i >= 10)

MOV r0, #0 ; by convention, r0 holds the return-value

B prog_end

return_1:
MOV r0, #1

prog_end:
ADD r13, r13, #48 ; pop the function frame off the stack
MOV r15, r14 ; load LR into PC (r15) [causing a return]

Albeit deliberately under-optimised, this assembly listing gives scope for non-trivial
optimisations. But firstly, let us remove some glaring redundancies.

Unnecessary loads/stores:
The variables ‘i’ and ‘s’ need not be stored on the stack. Registers can be used
instead, to server their purpose. With this simple change, we save:
o 8-bytes on the stack (see grey-shaded #1)
o 20-bytes (5-instructions) in the program space (see grey-shaded #2-5)
o 3 of the load/store instructions off the loop, which in the worst-case scenario
(of the element being searched for being the last one in the array) saves
them from being executed 9 times (i.e., a minimum of 126-cycles7)

The compiler is good at tasks such as register allocation. But before we look at a
compiler generate code, let us attempt utilising the knowledge we have acquired of
the ARM instruction set.

Loop invariants:

‘r2’ is initialised to ‘#4’ in the loop, but never modified. So, the initialisation can be
moved out of the loop, say ahead of ‘loop_start’. This, in the worst-case scenario
saves it from being executed 9 times (i.e., a minimum of 27-cycles)

Conditional execution:

o The ‘BEQ’ ahead of the grey-shaded region #4 can be eliminated by making

the succeeding ‘ADD’ and ‘B’ conditional on ‘NE’ (saving of 4-bytes and a
worst-case 45-cycles)
o The ‘BGE’ and ‘MOV’ after the grey-shaded region #5 can be replaced with a
single ‘MOVLT’ (saving of 4-bytes)
o The unconditional branch to ‘prog_end’ can be removed if the succeeding
‘MOV’ instruction is replaced with a ‘MOVGE’ (saving of 4-bytes)

Let us re-visit the assembly listing after incorporating these optimisations.

7
Four cycles per store and five per load
ARM programming and optimisation techniques 10

.text

; Stack ‘grows’ downward, caller saves registers.

; Make 40bytes of space for a[] on the stack

ADD r13, r13, #-40

; a[]: (sp + 4) .. (sp + 40)

; Assume that a run-time library routine initialises a[] with

; the required values

MOV r0, #0 ; for (i = 0; ...)

MOV r1, #4 ; s = 4

MOV r2, #4 ; sizeof(a[i])

loop_start:
; loop entry condition check
CMP r0, #10 ; for (...; i < 10; ...)
BGE loop_end

; get a[i]
MUL r3, r0, r2 ; r3 = i * 4 (serves as an index in a[i])
ADD r3, r3, #4 ; adjust r3 relative to base of a[]
LDR r4, [r13, r3] ; r4 = *(r13 + r3) i.e., a[i]

TEQ r1, r4 ; s == a[i] ?

ADDNE r0, r0, #1 ; for (...; i++) (if ‘s’ not found)
BNE loop_start ; next iteration (if ‘s’ not found)

loop_end:
CMP r0, #10

MOVLT r0, #0 ; if (i < 10) ...

MOVGE r0, #1 ; else

prog_end:
ADD r13, r13, #40 ; pop the function frame off the stack
MOV r15, r14 ; load LR into PC (r15) [causing a return]

This seems to be as good as it can get. Yet, there is one little trick left – eliminating
the multiplication – to be tried out.

Shift to multiply:

We have already seen the second operand of ARM load/store instructions being used
for auto-indexing. It can also be used to specify a register with an optional shift as
follows:

LDR/STR{cond} Rd, [Rn, {-}Rm{,shift}]{!} ; pre-indexing

-OR-
LDR/STR{cond} Rd, Rn, [{-}Rm{,shift}] ; post-indexing
ARM programming and optimisation techniques 11

where shift can be one of:

ASR #n arithmetic shift right n bits; n = [1..32]
LSL #n logical shift left n bits; n = [0..31]
LSR #n logical shift right n bits; n = [1..32]
ROR #n rotate right n bits; n = [1..31]
RRX rotate right one bit with carry (extend)

The multiplication in the listing can now be replaced with a simple left shift:

.text

; Stack ‘grows’ downward, caller saves registers.

; Make 40bytes of space for a[] on the stack

ADD r13, r13, #-40

; a[]: (sp + 4) .. (sp + 40)

; Assume that a run-time library routine initialises a[] with

; the required values

MOV r0, #0 ; for (i = 0; ...)

MOV r1, #4 ; s = 4

ADD r2, r13, #4 ; r2 = &a[0]

loop_start:
; loop entry condition check
CMP r0, #10 ; for (...; i < 10; ...)
BGE loop_end

; get a[i]
LDR r3, [r2, r0, LSL #2] ; r3 = *(r2 + r0*4) i.e., a[i]

TEQ r1, r3 ; s == a[i] ?

ADDNE r0, r0, #1 ; for (...; i++) (if ‘s’ not found)
BNE loop_start ; next iteration (if ‘s’ not found)

loop_end:
CMP r0, #10

MOVLT r0, #0 ; if (i < 10) ...

MOVGE r0, #1 ; else

prog_end:
ADD r13, r13, #40 ; pop the function frame off the stack
MOV r15, r14 ; load LR into PC (r15) [causing a return]

After a string of optimisations, we achieved a program length of 15-words (as

compared to the original size of 24-words). We have also been able to significantly
reduce the execution time. This is better than the code generated by an optimising
ARM programming and optimisation techniques 12

compiler8 (even after making an allowance for ‘a[]’ initialization code). This
improvement can primarily be attributed to our understanding of the application on
hand. For instance, it is difficult to imagine a compiler generate the ‘TEQ, ADDNE,
BNE’ sequence for this program!

Caution! You cannot replace a compiler:

It is very tempting to hand code a program in assembly as the returns are rewarding
enough, especially in the case of small programs. But any non-trivial program should
first be run through a respectable compiler. Further optimisation can then be
attempted on the generated assembly code. Not only does this cut the development
effort by an order of magnitude but also greatly reduces the chances of defects
creeping in due to oversight and weariness that sets on the programmer (on the
second sleepless night when the coffee maker runs out of the refill). For, modern
compilers incorporate many advanced optimisation techniques and are good at
applying them tirelessly, over and over, to large chunks of code.

To explore ARM optmisation further, let us now move on to ‘block copy’ - an example
no ARM programming tutorial can do without:

An optimised bcopy:

void bcopy(char *to, char *from, unsigned int nbytes)

{
while (nbytes--)
*to++ = *from++;
}

Translation:

_bcopy:

; by procedure call convention, the arguments to this function are

; passed in r0, r1, r2

TEQ r2, #0 ; nbytes == 0 ?

BEQ bcopy_end

bcopy_start:
SUB r2, r2, #1 ; nbytes--

; *to++ = *from++
LDRB r3, [r1], #1 ; LDRB/STRB loads/stores a byte
STRB r3, [r0], #1 ; auto indexing for post increment (++)

B bcopy_start ; next iteration

bcopy_end:
MOV r15, r14 ; PC = LR i.e., return

8
I make this claim after verifying the ‘release’ mode code generated by two popular compilers for ARM
ARM programming and optimisation techniques 13

There seems to be hardly any scope for optimization at the outset. Yet, in a task that
involves a condition check, we hardly seem to be using any conditional execution.
This gives us a clue for optimisation.

Optimisation-1:
_bcopy:

; rewriting ‘(nbytes--)’ as ‘(--nbytes >= 0)’, we get:

SUBS r2, r2, #1 ; set CPSR flags on --nbytes

LDRPLB r3, [r1], #1 ; PL: condition code for ‘PLus’

STRPLB r3, [r0], #1 ; ‘PLus’ stands for ‘positive or zero’
BPL _bcopy ; next iteration

MOV r15, r14 ; return

We were able to save 2 instructions out of 7 and bettered a compiler, again9.

Now let us move our focus from size to performance, as a 30% reduction does not
really mean much when the original footprint is only 28-bytes.

bcopy’s execution profile:

As obvious from the listing, bcopy spends its entire lifetime in a loop. The branch
instruction contributes 25% to the size of the loop. More importantly, it takes up
30% of the execution time (5-cycles out of every 17-cycles). This overhead is
unacceptable to any non-trivial and performance sensitive application. This
understanding drives our further attempts at optimisation.

We apply the popular loop-unrolling technique to reduce the percentage of time

taken by the branch instruction as compared to overall loop time.

Optimisation-2:

_bcopy:

; For simplicity of illustration, assume ‘nbytes’ is a multiple of 4

; Unrolling the loop, to copy four bytes per iteration, we get:

SUBS r2, r2, #4

LDRPLB r3, [r1], #1 ; copy byte-1

STRPLB r3, [r0], #1

LDRPLB r3, [r1], #1 ; copy byte-2

STRPLB r3, [r0], #1

LDRPLB r3, [r1], #1 ; copy byte-3

STRPLB r3, [r0], #1

9
Yes. With O2 optimisation for space in ‘release’ mode!
ARM programming and optimisation techniques 14

LDRPLB r3, [r1], #1 ; copy byte-4

STRPLB r3, [r0], #1

BPL _bcopy ; next iteration

MOV r15, r14 ; return

By adding 6 more instructions, we have been able to reduce the share of ‘BPL’ from
30% to 14% (5 out of 44-cycles). Yet, this gain is highly deceptive. For we could as
well have used a load/store-word combination in place of the four load/store-byte
instructions, thereby increasing the effective throughput of the original loop without
incurring a size/cycle penalty. That way we only need 17-cycles to transfer four
bytes (in spite of ‘BPL’ usurping 30% of the cycles)!

Caution! Each nail needs a different hit10

The de-optimisation seen above is due to a blind application of the ‘loop unrolling’
technique. And such cases are not unique to this technique alone. Each technique
needs to be tailored to the task on hand.

Optimisation-3:

_bcopy:

; For simplicity of illustration, assume ‘nbytes’ is a multiple of 16

; Unrolling the loop, to copy four words per iteration, we get:

SUBS r2, r2, #16

LDRPL r3, [r1], #4 ; copy word-1

STRPL r3, [r0], #4

LDRPL r3, [r1], #4 ; copy word-2

STRPL r3, [r0], #4

LDRPL r3, [r1], #4 ; copy word-3

STRPL r3, [r0], #4

LDRPL r3, [r1], #4 ; copy word-4

STRPL r3, [r0], #4

BPL _bcopy ; next iteration

MOV r15, r14 ; return

With this, the throughput has increased to 16bytes per 44-cycle iteration (a gain of
600% as compared to the original 1byte per 17-cycle iteration), with ‘BPL’ taking
14% of the execution time.

10
An old saying goes ‘When you have a hammer in the hand...’
ARM programming and optimisation techniques 15

Is further optimisation possible? Ignoring unreasonable options such as unrolling the

word-copy loop many more times, there hardly seems to be any technique left that
can be used to achieve a significant gain in performance. Well, we will re-visit this
example if we find one.

Multiple-load/store instructions – a detour

Consider a subroutine which needs to call other subroutines and also uses all the
available general-purpose registers for local use. Assuming a ‘callee-saves’ protocol,
a stack that grows from low to high address and a stack pointer that always pointing
to the next free word available, the subroutine’s entry and exit code looks similar to
this:

_foo: ; exit code start

; restore all registers
; entry code start
; save all registers LDR r14, [r13, #-4]!
; (r0 – r3 need not be saved LDR r12, [r13, #-4]!
; as are for parameter passing) LDR r11, [r13, #-4]!
STR r4, [r13], #4 LDR r10, [r13, #-4]!
STR r5, [r13], #4 LDR r9, [r13, #-4]!
STR r6, [r13], #4 LDR r8, [r13, #-4]!
STR r7, [r13], #4 LDR r7, [r13, #-4]!
STR r8, [r13], #4 LDR r6, [r13, #-4]!
STR r9, [r13], #4 LDR r5, [r13, #-4]!
STR r10, [r13], #4 LDR r4, [r13, #-4]!
STR r11, [r13], #4
STR r12, [r13], #4 ; exit code ends
STR r14, [r13], #4
; entry code ends MOV r15, r14 ; return

To a non-ARM RISC programmer, this listing is familiar and normal. For, each and
every instruction is very much relevant and essential to the task on hand. Only, an
ARM programmer would simply have written this equivalent code:

_foo:

STMEA r13!, {r4 – r12, r14} ; entry code

;
; body of _foo
;

LDMEA r13!, {r4 – r12, r15} ; exit code

There is no mysterious magic here. Any non-trivial programming task, whether

driven by structured, object oriented or functional design approach, involves
subroutines. And most programming languages use a stack based solution for
maintaining the activation of records of called (currently active thread) subroutines.
Given the limited number of registers on any processor, saving and restoring
registers across subroutine calls is inevitable. The special non-RISC-like ARM
ARM programming and optimisation techniques 16

instructions seen above (LDM&STM) are an explicit acknowledgement from the ARM
architecture of the frequency and importance of such multiple-register load/store
activity. These instructions can be used multiple ways such as:

STMEA & LDMEA: push(store)/pop(load) multiple-registers to/from an ‘empty

ascending’ stack i.e., the stack pointer points to the next free word on the stack as it
grows from low to high address. The suffix ‘EA’ can be replaced with a more generic
mnemonic ‘IA’ (increment after). E.g., STMEA r13!, {r3-r5, r11, LR}

STMFD & LDMFD: By replacing the suffix ‘EA’ with ‘FD’ you get a ‘full descending’
stack which is exactly opposite in behaviour to an ‘EA’ stack. ‘FD’ has a semantically
equivalent name ‘DB’ which stands for ‘decrement before’. E.g., LDMDB r0!, {r1-r10}

Other combinations such as ‘IB’ and ‘DA’ are also possible.

Obviously, these instructions cannot be taking the same number of cycles as an LDR
or an STR. The real gains are in program space, reduced chances of making coding
mistakes and enhanced readability.

Optimisation-4:

As you might have guessed by now, the time has come to rejoin the main road and
revisit the bcopy example. The previous throughput of 16bytes per iteration can now
be achieved on a smaller footprint by replacing the four pairs of LDRPL/STRPL with a
single LDMPL/STMPL combination such as:

LDMPL r1!, {r3 – r6} ; load r3-r6 from [r1], advance r1 by 16 bytes
STMPL r0!, {r3 – r6} ; store r3-r6 starting at [r0], advance r0

The blue print for a high throughput (close to 40byte) bcopy is as follows:

_bcopy:

; For every iteration, attempt to transfer 40bytes. The modulus value

; remaining (remainder of the division of ‘nbytes’ by 40) should be
; treated as a separate lesser throughput bcopy loop. Shown here is
; only the main 40byte throughput loop:

; Unrolling the loop, to copy ten words per iteration, we get:

SUBS r2, r2, #40

BMI copy_rest ; ‘MI’ stands for minus/negative

LDMPL r1!, {r3 – r12} ; load r3-r12 from [r1]

STMPL r0!, {r3 – r12} ; store the loaded words at [r0]

BPL _bcopy ; next iteration

; copy the residual bytes

copy_rest:
; completed copying

MOV r15, r14 ; return

ARM programming and optimisation techniques 17

By saving r13 and r14 on the stack before the start of the loop, the throughput can
be pushed closer to the maximum possible 48bytes per iteration. This is an example
of how two of ARM’s best features - conditional execution and multiple load-stores
put together11 improve the program characteristics by an order of magnitude.

Thumb – the final footprint solution

Before calling it a day, a brief12 overview of the 16-bit Thumb instruction set would
be appropriate. All the ARM listings seen earlier used the normal 32-bit ARM
instructions. However, many embedded systems designers show an inclination to
trade performance13 for footprint – provided there is an option. Not until the advent
of ARM did a single processor offer a solution of simultaneously executing both 32-bit
and 16-bit code with such little overhead (in terms of additional silicon, programming
complexity and cost).

The Thumb is a 16-bit instruction set architecture that is functionally complete but
relatively restricted in variety as compared to that of the regular 32-bit ARM
instruction set. Notable differences include 2-address format, unconditional updation
of CPSR flags for (almost) all instructions and less flexible ‘second operand’. The
Thumb architecture is cleanly implemented in silicon by way of including an on-the-
fly instruction de-compressor functional unit in the processor that translates 16-bit
ARM instructions into their 32-bit equivalents that are understood by the rest of the
processor. It must be noted though that it is only the instruction length that is
halved and not the register sizes themselves. As a side effect, the number of usually
visible registers is reduced by five14.

The programmer is not constrained to use a single instruction set throughout his
program. Complete freedom is given to freely intermix 32-bit and 16-bit code and
switch between them using the BX (branch and exchange) instruction. Whenever the
Thumb is found to be inadequate and restrictive for a particular functionality /
module / computation, the ARM instruction set can be used as a special case (or the
other way around, if at certain places the power of 32-bit seems an overkill15). It is
this flexibility which makes the ARM processor a very attractive option for an
embedded systems designer / programmer.

Conclusion
This paper made an attempt at introducing the ARM architecture to an embedded
systems designer / programmer by providing an overview of its functional units and
instruction set. ARM assembly optimisation techniques were introduced along with a
couple of examples in a graded exercise like fashion. This being targeted at those
who are new to the architecture, most fine grain details were left out of this paper
for fear of losing reader interest. However, the techniques presented herein should

11
Chess enthusiasts can liken this to an active Queen-Knight combination
12
Brief, not because its instruction length being only half as long as its more powerful 32-bit cousin, but
because of it requiring a completely dedicated tutorial to do justice.
13
Even in performance critical cases such as an RTOS, the emphasis is usually on predictability and
bounded response times rather than on searing speed.
14
r0-r7 known as ‘low’ registers are always visible while the high ‘r8-r12’ are visible only in certain
instructions in restricted formats.
15
If the reader wondered why there was a switch between a 2-column and single column mode, the
answer should now be evident ;^)
ARM programming and optimisation techniques 18

be sufficient enough to venture into serious software design and programming with
the ARM processor(s). The references provided towards the end of this paper can be
used to further hone ARM assembly programming skills.

References
• Dave Jagger (editor), ARM Architecture Reference Manual, Prentice Hall
• Steve B. Furber, ARM System Architecture, Addison-Wesley, 1996, ISBN 0-201-
40352-8
• http://www.arm.com/ - data sheets, instruction set summaries, white papers,
application notes and architecture references for the ARM family of processors
• Rupesh W. Kumbhare, Optimization Techniques for DSP based Applications – A
highly detailed paper on optimisation techniques for the TMS320C54x family of
DSPs. It describes with code-samples, concepts that are applicable to non-DSP
programming as well. Interested readers are can reach the author
([email protected]) for a copy of the same

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