Scribd
Upload
66 views2 pages

4 Bit State Machine

This Verilog code defines a state machine that detects a hit condition when its input x matches the 0110 binary waveform. The state machine contains 7 states and transitions between them based on the current state and the value of the input x at each clock cycle, setting the output hit to 1 if it reaches state 4 and the input is low.

Uploaded by

jufeldt
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
66 views2 pages

4 Bit State Machine

This Verilog code defines a state machine that detects a hit condition when its input x matches the 0110 binary waveform. The state machine contains 7 states and transitions between them based on the current state and the value of the input x at each clock cycle, setting the output hit to 1 if it reaches state 4 and the input is low.

Uploaded by

jufeldt
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
You are on page 1/ 2

State Machine Hit at 0110 binary Waveform

Codes `timescale 1ns/1ns module statemec( reset,clock,x, hit); input reset; input clock; input x; tri0 reset; tri0 x; output hit; reg hit; reg [6:0] fstate; reg [6:0] reg_fstate; parameter state1=0,state2=1,state3=2,state4=3,state5=4,s tate6=5,state7=6; always @(posedge clock) begin if (clock) begin fstate <= reg_fstate; end end always @(fstate or reset or x) begin if (reset) begin reg_fstate <= state1; hit <= 1'b0; end else begin hit <= 1'b0; case (fstate) state1: begin if (~(x)) reg_fstate <= state2; else if (x) reg_fstate <= state5; else reg_fstate <= state1; end state2: begin if (x) reg_fstate <= state3; else if (~(x)) reg_fstate <= state6; else reg_fstate <= state2; end state3: begin if (x) reg_fstate <= state4; else if (~(x)) reg_fstate <= state7; else reg_fstate <= state3; end state4: begin if (~(x)) begin hit <= 1'b1; end else begin hit <= 1'b0; end reg_fstate <= state1; end state5: begin reg_fstate <= state6; end state6: begin reg_fstate <= state7; end state7: begin reg_fstate <= state1; end default: begin hit <= 1'bx; $display ("Reach undefined state"); end endcase end end endmodule // statemech

You might also like