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Booth Multiplier VHDL Code

This document contains VHDL code for implementing a Booth multiplier. It defines an entity called boothmult with ports for the multiplicand, multiplier, result, and start signal. The architecture booth_arch contains a process that uses a for loop to iterate through the bits of the multiplier and multiplicand, shifting and adding the multiplicand to calculate the partial products based on the Booth recoding algorithm. It outputs the final product to the result port. There is also an entity called testbooth that instantiates the boothmult component and provides test vectors to simulate multiplication operations.

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Sameera Somisetty
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© Attribution Non-Commercial (BY-NC)
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Download as PDF, TXT or read online on Scribd
17K views

Booth Multiplier VHDL Code

This document contains VHDL code for implementing a Booth multiplier. It defines an entity called boothmult with ports for the multiplicand, multiplier, result, and start signal. The architecture booth_arch contains a process that uses a for loop to iterate through the bits of the multiplier and multiplicand, shifting and adding the multiplicand to calculate the partial products based on the Booth recoding algorithm. It outputs the final product to the result port. There is also an entity called testbooth that instantiates the boothmult component and provides test vectors to simulate multiplication operations.

Uploaded by

Sameera Somisetty
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as PDF, TXT or read online on Scribd
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VHDL Code for Booth Multiplier

library ieee; use ieee.std_logic_1164.all ; use ieee.std_logic_unsigned.all; library ieee; use ieee.std_logic_1164.all ; entity testbooth is end entity; entity boothmult is port ( mpcd, mplr : in std_logic_vector(7 downto 0); result : out std_logic_vector(15 downto 0) ; start : in std_logic ); end entity ; architecture booth_arch of boothmult is begin process(start) variable br,nbr : std_logic_vector(7 downto 0); variable acqr : std_logic_vector(15 downto 0); variable qn1 : std_logic ; begin if(start'event and start = '1') then acqr(15 downto 8):= (others=>'0'); acqr(7 downto 0) := mpcd; br:= mplr ; nbr := (not mplr) + '1' ; qn1 := '0' ; else loop1 : for i in 7 downto 0 loop if( acqr(0) = '0' and qn1 = '0') then qn1 := acqr(0); acqr(14 downto 0) := acqr(15 downto 1) ; elsif ( acqr(0) = '0' and qn1 = '1') then acqr(15 downto 8) := acqr(15 downto 8) + br; qn1 := acqr(0); acqr(14 downto 0) := acqr(15 downto 1) ; elsif ( acqr(0) = '1' and qn1 = '0') then acqr(15 downto 8) := acqr(15 downto 8) + nbr; qn1 := acqr(0); acqr(14 downto 0) := acqr(15 downto 1) ; elsif ( acqr(0) = '1' and qn1 = '1') then qn1 := acqr(0); acqr(14 downto 0) := acqr(15 downto 1) ; end if ; end loop loop1; result <= acqr ; end if ; end process ; end booth_arch; architecture test_arch of testbooth is component boothmult is port ( mpcd, mplr : in std_logic_vector(7 downto 0); result : out std_logic_vector(15 downto 0) ; start : in std_logic ); end component ; signal tmpcd, tmplr : std_logic_vector(7 downto 0); signal tresult : std_logic_vector(15 downto 0); signal tstart : std_logic := '0'; begin inst: boothmult port map (tmpcd, tmplr, tresult, tstart ); process begin tmpcd <= "11111110" ; tmplr <= "00000010" ; tstart <= '1'; wait for 1 ns; tstart <= '0'; wait for 10 ns ; tmpcd <= "00000101" ; tmplr <= "00000010" ; tstart <= '1'; wait for 1 ns; tstart <= '0'; wait for 10 ns ; end process; end test_arch ;

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