ISA System Architecture Third Edition MINDSHARE, INC. TOM SHANLFY AND DON ANDFRSON EDITED AND REVISED BY JOHN SWINDLE vw Addison-Wesley Publishing Company Reading, Massachusetts * Menlo Park, Calitornia * New York Don Mills, Ontario * Wokingham, England * Amsterdam Bonn * Sydney * Singapore * Tokyo * Madrid * San Juan Paris # Seoul * Milan * Mexico Cit TaipelMindShare, Inc (r) SINGLE-USER LICENSE AGREEMENT Please read this document carefully before proceeding. ‘Ihis Agreement licenses this electronic book to you and contains warranty and liability disclaimers, By viewing this book, you are con- firming your acceptance of the book and agreeing to become bound by the terms of this Agree- ‘ment. If you do not wish fo do so, immediately return the book to MindShare, Inc. Le NITIONS (a) "book or electronic book” means the electronic book covered by this Agreement, and any related updates supplied by MindShare, Inc. The book consists of the encrypted PDF file supplied in electronic form 2. LICENSE. ‘This Agreement allows the SINGLE END-USER to: (a) View the book on a computer or a stand-alone ebook viewer. (b) You may make and distribute copies of the book and electronically transfer the book from one computer to another or over a network. (c) Certain rights are not granted under this As agreement. If you would like to enter into a S ereement, but may be available under a separate ie or Network License, please contact MindShare. 3, RESTRICTIONS (a) You may not copy sereen im (b) You may not decompile, rever hhuman-perceivable form, (c) You may not modily, book or any part thereof. (d) You will not export or reexpor, directly or indirectly, the book into any country prohibited by the United States Export Administration Act and the regulations thereunder. (e) The book may not be used in a group viewing environment, es of the book, or any portion thereof. ineer, disassemble, or otherwise reduce the book to a -sell fr profit, distribute or create derivative works based upon the 4, OWNERSHIP. ‘The foregoing license gives you limited rights to use the book. You do not become the owner of, and MindShare retains title 10, the intellectual property contained within the book, and all copies thereof. All rights not specifically granted in this Agreement, including Federal and International Copyrights, are reserved by MindShare. 5, DISCLAIMER OF WARRANTIES AND OF TECHNICAL SUPPORT ‘The book is provided to you on an "AS IS" basis, without any technical support or warranty of any kind from MindShare including, without limitation, a warranty of merchantability, fitness for 4 particular purpose and non-infringement, SOME STATES DO NOT ALLOW THE EXCLU- SION OF IMPLIED WARRANTIES. SO THE ABOVE EXCLUSION MAY NOT APPLY YOU. YOU MAY ALSO HAVE OTHER LEGAL RIGHTS WHICH VARY FROM STATE. TiSTATE, ‘These limitations or exclusions of warranties and liability do not atfect or prejudice the statutory rights of a consumer; ie., a person acquiring goods otherwise than in the course of husiness 6, LIMEEATION OF DAMAGES: MINDSHARE SHALL NOT BE LIABLE FOR ANY INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES OR LOSS (INCLUDING DAMAGES FOR LOSS OF BUSI- NESS, LUSS OF PROFITS, OR THE LIKE), WHETHER BASED ON BREACH OF CON- ‘TRACT, TORT (INCLUDING NEGLIGENCE), PRODUCT LIABILITY OR OTHERWISE, EVEN IF MINDSHARE OR ITS REPRESENTATIVES HAVE BEEN ADVISED OF THE POS: SIBILITY OF SUCH DAMAGES. SUME STATES DO NOT ALLOW THE LIMETATION OR EXCLUSION OF LIABILITY FOR INCIDENTAL OR CONSEQUENTIAL DAMAGES, SO ‘THIS LIMITATION OR EXCLUSION MAY NOT APPLY TO YOU. The limited warranty, exclusive remedies and limited liability set forth above are fundamental elements of the basis of the bargain between Mindshare and you. You agree that Mindshare would not be able to provide the hook on an economic hasis without such lim 7. GOVERNMENT END USERS (USA only): RESTRICTED RIGHTS LEGEND The book is "Restricted Computer Software." Use, duplica- tion, or disclosure by the U.S. Government is subi set forth in this Agreement and as provided in DEARS 227.7202-I(a) and 227.7202-3(a) (1995), DEARS 252.227-1013 (OCT 1988), FAR 12.212(a)(1995 7-19, or FAR 52.227-14, as applicable." Manufac: turer: Mindshare, Inc., 4285 Slash Pine Drive, Colorado Springs, CO 80908. 8. GENERAL: ‘This Agreement shall be governed by the internal laws of the State of Colorado. This Agreement contains the complete agreement between the parties with respect to the subject matter hereot, and supersedes all prior or contemporaneous agreements or understandings, whether oral or written, All questions concerning this Agreement shall be directed to: Mindshare, Inc., 4285 Slash Pine Drive, Colorado Springs, CO 80908, Attention: Chief Financial Ollicer ‘Mindshare is registered trademark of Mindshare, Ine. Single-User License Agreement 9/8/.Many of the designations used by manufacturers and sellers to distinguish their prod- cts are claimed as trademarks. Where those designations appear in this book, and Ad- dison-Wesley was aware of a trademark claim, the designations have been printed in initial capital letters or all capital letters. The authors and publishers have taken care in preparation of this book, but make no expressed or implied warranty of any kind and assume no responsibility tor errors or omissions. No liability is assumed tor incidental or consequential damages in connec tion with or arising out of the use of the information or programs contained herein. Library of Congress Cataloging-in-Publication Data ISBN: 1-201-40996-8 Copyright © 1995 by MindShare, Inc. Alll rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted, in any form or by any means, electronic, mechanical, photo- copying, recording, or otherwise, without the prior written permission of the publisher. Printed in the United States ot America. Published simultaneously in Canada. Sponsoring Editor: Keith Wollman Project Manager: kleanor McCarthy Production Coordinator: Deborah McKenna Cover design: Barbara I. Atkinson Set in 10 point Palatino by MindShare, Inc. 123.4.56789-MA- 9998079695, First printing, February 1995 Addison-Wesley books are available tor bulk purchases by corporations, institutions, and other organizations. Hor more iniormation please contact the Corporate, Govern- ment, and Special Sales Department at (8(X)) 238-9682.Dedication This book is dedicated to the numerous engineers and programmers who con- tributed to this work unknowingly by asking tough questions during Mind- ‘Share seminars. ‘Ihese questions led us to a far greater understanding of ISA architecture and made this book more complete,Contents Foreword xviii Xv Acknowledgments. About This Book The MindShare Architecture Series.. Organization of This Book. Who This Book Is For. Prerequisite Knowledg Documentation Conventions. Hex Notation Binary Notation. Decimal Notation Signal Name Representation, Identiication of bit Fields (logical groups of bits or signals) fe Want Your Feedbacl Overview System Kernel Memory Subsystems.. ISA Subsystem. Origins of ISA. The IBM PC... The IBM PC/AT The ISA Concept. Part 1: The System Kernel Chapter 1: Intro to Microprocessor Communications Instruction Fetch and Execution General In-Line Code Fetching Reading and Writing. Type of Information Read from Memory Type of Information Written to Memory The Buses. the Address Bus. Control Bus Transaction Type and Synchronization The Data Bus — Data Transter PathISA System Architecture Chapter 2: Introduction to the Bus Cycle Introduction. Automatic Dishwasher ~ Classic State Machine Example. The System Clock a Metronome Microprocessors Bus Cycle State Machine Address Time Data Time The Wait State Chapter 3: Addressing /O and Memory Evolution of Memory and VO Address Space. Intel 8080 Microprocessor Adalress Space 8086 and 8088 Microprocessor Address Space 33 286 and 386SX Address Space 34 386DX, 486 and Pentium Processor Address Space 35 Memory Mapped /0 The 10 Device Chapter 4: The Address Decode Logic The Address Decoder Concept. Data Bus Contention (Address Conflicts) How Address Decoders Wark Example 1- PC and PC/XT ROM Address Decoder. 42, Background Ihe PL/X1 ROM Address Decode Lope Example 2 - System Board 1/0 Address Decoder. Chapter 5: The 80286 Microprocessor The 80286 Functional Units. The Instruction Unit The Execution Unit General Registers. The Status and Control Registers The Address L Init The Segment Registers. Segment Register Usage in Real Mode... CodeSepment(S) & instruction Pointer () Kegisters The Data Segment (DS) Register The Extra Segment (HS) Register... Stack Segment (58) & Stack Pointer (SP) Registers Little-lindian Byte-Ordering Rule... Definition of Extended Memory.. ‘Accessing Extended Memory in Keal ModeThe Bus Unit. Address | atches and Drivers Instruction Pretetcher and 6-byte Prefetch Queue Processor Fxtension Intertace Bus Control Logic Data Transceivers 80286 Hardware Interface to External Device: The Address Bus. How 811286 Addresses Fxternal | acations The Data Bus The Cardinal Rules Cardinal Rule Number One: Cardinal Rule Number Two. Cardinal Rule Number Three The Control Bus Bus Cycle Detinition Lines Bus Mastering Lines. Protecting, Access 10 Shared Resource Ready Line.. Interrupt Lines Processor Fxtension Intertace | ines The Clock Line The Reset Line. Protected Mode Intro to Protected Mode and Multitasking Operating Systems, ‘Segment Register Usage in Protected Mode. i" Chapter 6: The Reset Logic The Power Supply Reset. Reset Button. Alternate (Fast) Hot Reset Ctrl-Alt-Del Soft Reset. Chapter 7: The Power-Up Sequence The Power Supply - Primary Reset Source How RESET Affects the Microprocessor. Processor Reaction When Output Voltages Stabilize. The First Bus Cycle. Chapter 8: The 80286 System Kernel: the Engine The Bus Control Logic.ISA System Architecture The Address Latch.. Address Pipelining, The Data Bus Transceivers Data Bus Steering Logic Srenarin One ~ Read Fven-Addressed [.ocation in &-Bit Device. 18 Srenarin Two - 8-Bit Read from Ocld-Addressed | ocation in 8-Bit Device 129 Srenarin Three — 8-Bit Write to Odd-Addressed Lcation in &-Bit Nevire: 131 Scenario Four — 16-bit Write to 8-Bit Device. 132 Srenarin Five — 16-Bit Read from 8-Bit Device, 133 Scenario Six — Rit Read trom 16-Bit Device. 134 Srenarin Seven — 16-Bit Read fram 16-Bit Neviee. 134 ‘Scenario Hight - 8-Lit Write to 16-Bit Device... Scenario Nine — 16-Bit Write to 16-Bit Device, 134 The Ready Logi Access Time. Stretching the Iranster lime. The Detault Ready timer Custom Ready limers, Extending the Detault Liming Shortening the Detault Liming. Chapter 9: Detailed View of the 80286 Bus Cycle Address and Data Time Revisited. The Read Bus Cycle Bus Cycle A’ Bus Cycle B. The Write Bus Cycl The Halt or Shutdown Bus Cycle Chapter 10: The 80386 DX and SX Microprocessors Intraduction The 80386 Functional Units. General nn Code Prefetch Unit Instruction Decode Unit. Execution Uni General The Registers General Registers. Status, MSW and instruction Registers 157 Debug Registers 159Test Registers ‘Segmentation Unit... Paging Unit. Bus Unit Protected Mode Page Translation Virtual Paging Translation | ookaside Butter Virtual-8086 Mode.. Automatic Self-Test 80386DX External Interface.. The Address Bus. The Data Bus The Control Bus Bus Cycle Definition Outputs... Processor Fxtension [ines Address Status Output... Pipelining Control Input. Dynamic Bus Sizing (S168). 80386SX External Interface Intertace Signal Ditterence: AO or BLFE. Addressing Scheme, Data Bus Width Ramifications... Throughput and Compatibility Considerations, Chapter 11: The 80386 System Kernel Introduction. The 80386SX System Kernel The 80386DX System Kernel 80386DX System Kernel witl Introduction... Reading from an 8-Bit Device... One-Byte Read from an 8-Bit Device Two-Byte Read from an 8-Bit Device. Four-Byte Read from an 8-Bit Device... Writing to an 8-Bit Device One-Byte Write to an 8-Bit Device ... Iwo-byte Write to an 8-bit Device. Four-byte Write to an 8-Bit Device Reading from a 16-Bit Device . Two-Byte Read from a 16-Bit Device. Four-Byte Read from a 16-Bit Device .. Writing to a 16-bit DeviceISA System Architecture Two-Byte Write to a 16-Bit Device 207 Four-Byte Write to a 16-Bit Device. Reading trom a 32-Bit Device . Writing to a 32-Bit Device S8U386DX System Kernel without Dynamic bus Sizing. Introduction, Reading trom a 16-Bit Device . Lwo-Byte Read trom a 16-Bit Device. Four-Byte Read trom a 16-bit Device .. Writing to a 16-Bit Device Two-Byte Write to a 16-Bit Device Bit Device. Chapter 12: Detailed View of the 80386 Bus Cycles The Bus Cycle Types.. Address Pipelining Overview. Memory or /O Read Bus Cycl Memory or I/O Write Bus Cycle.. Address Pipelining Exampl Interrupt Acknowledge Bus Cycle Halt or Shutdown Bus Cyc Part 2: Memory Subsystems Chapter 13: RAM Memory: Theory of Operation Dynamic RAM (DRAM) Memory DRAM Addressing Sequence Row and Column Address Sour DRAM Addressing Logic. Detaled Descrption cf DRAM Addressing Begun How Data is Stored in DRAM, DRAM Refresh. Refresh Logicand RAS-only Retresh. CASbetore-RAS Retresh Hidden Retresh, Sel-Retresh Destructive Read: Pre-charge Delay and Cycle Time DRAM Bank DRAM Bank Width. DRAM Error Detection and Correction. DRAM Party. Etror-Checking-and-Correcting Memory Page-Mode DRAM and its VariationsContents Page Mode DRAM Enhanced Page Mode DRAM. Burst and Nibble Mode DRAM 285 Static Column RAM (SCRAM).. ‘Synchronous DRAM Interleaved Memory Architecture. Static RAM (SRAM) Chapter 14: Cache Memory Concepts The Problem .. The Solution. Principles of Locality Temporal Locality Spatial Locality Cache Performance Overall System Performance.. Cache Consistency Components of a Cache Subsystem, Cache Memory Cache Management Logic Cache Memory Directory wn Intro to Cache Architecture, Coherency, Write Policies and Organization .. Cache Architectures. Look-Through Cache Look-Aside Cache..sn First-and Second-Level Caches. A Combined (Unified) and Split (Dedicated) Caches.. Cache Consistency (Coherency).. Causes of Cache Consistency Problems. Write Policy nn Write-Through Cache Design: Buffered Write-Through Designs. Write-Back Cache Designs Bus Master /Cache Interaction. Bus Snooping /Snarfing Coherency via Cache Flushin Software-Enforced Coherene Cache Organization and Size. Fully-Associative Cache, Direct-Mapped Cache (One-Way Set-Associative). Two-Way Set-Associative Cache Four-Way Set-Associative Cache. Least-Recently Used (LRU) AlgorithmISA System Architecture Cache Line Size Cache Size First-I evel Cache Size. Second-l evel Cache Size Cache Addressing, 1/0 Information Nat Cached. Non-Cacheable Memory. Chapter 15: ROM Memory ROM Memory — Theory of Operation Introdu Fusible- Masked ROM (MROM) Eraseable Programmable Read-Only Memory (EPROM) Electrically Eraseable Programmable Read-Only Memory (EEPROM Flash EEPROM... ROMS Interface to System System Board ROM Memory . Lesting Shadow RAM vss Shadow RAM and ROM Occupying Different Address Spaces, Shadow RAM and ROM Occupy Same Address Spac Double Mapping ROM and Shadow RAM Address Space. Recovering Unused ROM Address Space. 32KB System Board ROM Configuration 6AKB System Board ROM Configuration ROMs on ISA Cards (Device ROMS) Part 3: The Industry Standard Architecture Chapter 16: ISA Bus Structure Introductior Address Bu: Data Bus. Bus Cycle Definition. Bus Cycle Timi Error Reporting Signal. Miscellaneous Signals.Chapter 17: Types of ISA Bus Cycles Introduction. Transfers with bit Device Transfers with 16-bit Devices. Standard 16-bit Memory Device ISA Bus Cyc Standard 16-bit I/O Device ISA Bus Cycle. 0- State Access to 16-bit Memory Dev Chapter 18: The Interrupt Subsystem What Is an Interrupt? Microprocessor Response to Interrupt Request. Interrupt Acknowledge Bus Cycles. Saving Pointer to Interrupted Program Clearing the Interrupt Enable Flag, Jumping to the ISR Resuming the Interrupted Program When One 8259 Interrupt Controller Isn’t Enough, Servicing Requests to Slave Interrupt Controller Interrupt Table Entry Assignment: IRQ2 Redirect. Shareable Interrupts in ISA Machines Generating the Interrupt Request Interrupt Table Initialization ~ Add-in Devices Shared Interrupt Procedure Phantom Interrupts. Programming the 825+ Introductio aN Programming the Registers Non-Maskable Interrupt Requests (NMD Software Interrupts Software Exceptions Software Interrupt Instruction Protected Mode Interrupt: Chapter 19: Direct Memory Access (DMA) DMA Concept. DMA Example. DMA Controller (DMAC) DMA Transter Iypes. DMA Transter Modes Single ‘Iranster Mod ee : Block Transter Mode. 416