VHDL Interview Question(s) 1.

What are the two key concepts in the simulation semantics of VHDL and how does each concept help VHDL simulation produce waveforms that match the behaviour that we expect? 2. What is the advantage of RTL simulation in comparison to simulation as defined by the VHDL standard? 3. What is the disadvantage of RTL simulation in comparison to simulation as defined by the VHDL standard? 4. For each of the architectures muruku 1. . . muruku 4, answer the following questions. o INSTRUCTIONS: 1. Is the code legal VHDL? 2. If the code is legal VHDL: Answer whether the behaviour of the signal z has the same behaviour as in the main architecture of sumit. Answer whether the code is synthesizable. If the code is synthesizable, answer whether it adheres to good coding practices. If the the code is not legal, not synthesizable, or does not follow good coding practices, explain why. entity sumit is port ( a, b, clk : in std_logic; z : out std_logic ); end schreyer; architecture main of sumit is signal m : std_logic; begin process ( clk ) begin if rising_edge( clk ) then m <= a or b; end if; end process; process ( clk ) begin if rising_edge( clk ) then z <= not m; end if; end process; end main; 1. Muruku 1 o architecture muruku_1 of sumit is signal m : std_logic; begin process ( clk ) begin if rising_edge( clk ) then m <= a or b; z <= not m; end if; end process; end muruku_1; 2. Muruku_X o architecture muruku_X of sumit is signal m, p : std_logic; begin process ( clk ) begin if rising_edge( clk ) then m <= a or b; end if; end process; process ( clk ) begin if rising_edge( clk ) then z <= p; end if; end process; p <= not m; end muruku_X; 3. Muruku_2 o architecture muruku_2 of sumit is signal m, p : std_logic; begin if (a or b) = 1 generate m <= 1; end generate; if (a or b) = 0 generate m <= 0; end generate; process ( clk ) begin if rising_edge( clk ) then p <= m; end if; end process; process ( clk ) begin if rising_edge( clk ) then z <= not p; end if; end process; end muruku_2; 4. Muruku_3 o architecture muruku_3 of sumit is begin

process begin wait until rising_edge(clk); wait until rising_edge(clk); z <= not (a or b); end process; end muruku_3; 5. Muruku_4 o architecture muruku_4 of sumit is signal m, p : std_logic; begin process ( clk ) begin if rising_edge( clk ) then m <= a or b; end if; end process; process ( clk ) begin if rising_edge( clk ) then p <= m; end if; end process; z <= not p; end muruku_4; QUESTIONS 1. what s difference b/w blocking and non blocking assignments? where will u use it? ans: 1.blocking stmt these stmt blocks the other stmt from being executed.ie first these stmt gets executed before it lets other stmt execute. 2.Non blocking stmt these stmt executes all parallely.withe designated delayes. 2. what s racing condition? when s=1 and r=1, then both the signals fight against each other to determine the output.if this occurs output of the FF is not determined. how to overcome? 1. we can reduce the noise. 2. (i think we can put master-slave FF) 3. if u replace latch enable signal by clock wat will be the difference? (i think if we put clock ,then power consumption will be more) 4. how latch takes less power and ff takes more power? (clock routing may take power) 5. what's diffrence b/w mealy and moore ckt? mealy it has less number of states. it more prone to noise. moore it has more number of states. it is less prone to noise. 6. how to overcome metastability? by adding another FF see our ASIC-by smith 7. if u have "case" stmt and "if" stmt, and if "case" s good for synthesis then wat s advantage of "if" stmt? inside case stmt expression cannot be used like

case (x=x*5+y-10) (x): z=5; (y): f=10; end case; 8. how will u write d ff using variables alone?(VHDL question) (i don't know) but i think using variable and signals we can write D FF 9. design a some gates using mux refer any digital book 10. draw a state diagram for sequence detector. refer any digital book 11. how to overcome racing condition? (see the previous answer) 12. for a small example draw simlation time for non blocking assignment, blocking assignment. (refer the previous link) 13. some questions on interfacing. 14. draw a simple circuit of D FF using pass gate transistor refer any CMOS book 15. which universal gate do u prefer(NAND or NOR)? ans: NAND gate 16. why? ans: it takes less power,....(i think less arear) 17. draw the schematic of NAND gate. see the book. 18. what determines drive strangth of a gate? width of the gate determines drive strength of the gate. 19. what s clock skew? when clock s routed through the chip it is subjected to parasitic capacitance,so the current is absorbed by the circuit, so clock is delayed by some amount.which is called clock skew. skew-- means delay eqn:- r1+r1*c1+r1(c1+c2)+... like that (see any CMOS book) 20. how to reduce the frequency by half?(very very important question!!!) ans i know: just put a T FF. if u put a T FF u reduce the freq by half. if u put 2 power n FF, u reduce the frequency by n times. they may ask u to code it in Verilog or VHDL. 21. how to double the frequency by two times.

14) Difference between Verilog and vhdl? Compilation VHDL. Multiple design-units (entity/architecture pairs), that reside in the same system file, may be separately compiled if so desired. However, it is good design practice to keep each design unit in it's own system file in which case separate compilation should not be an issue.

Verilog. The Verilog language is still rooted in it's native interpretative mode. Compilation is a means of speeding up simulation, but has not changed the original nature of the language. As a result care must be taken with both the compilation order of code written in a single file and the compilation order of multiple files. Simulation results can change by simply changing the order of compilation. Data types VHDL. A multitude of language or user defined data types can be used. This may mean dedicated conversion functions are needed to convert objects from one type to another. The choice of which data types to use should be considered wisely, especially enumerated (abstract) data types. This will make models easier to write, clearer to read and avoid unnecessary conversion functions that can clutter the code. VHDL may be preferred because it allows a multitude of language or user defined data types to be used. Verilog. Compared to VHDL, Verilog data types a re very simple, easy to use and very much geared towards modeling hardware structure as opposed to abstract hardware modeling. Unlike VHDL, all data types used in a Verilog model are defined by the Verilog language and not by the user. There are net data types, for example wire, and a register data type called reg. A model with a signal whose type is one of the net data types has a corresponding electrical wire in the implied modeled circuit. Objects, that is signals, of type reg hold their value over simulation delta cycles and should not be confused with the modeling of a hardware register. Verilog may be preferred because of it's simplicity. Design reusability VHDL. Procedures and functions may be placed in a package so that they are avail able to any designunit that wishes to use them. Verilog. There is no concept of packages in Verilog. Functions and procedures used within a model must be defined in the module. To make functions and procedures generally accessible from different module statements the functions and procedures must be placed in a separate system file and included using the `include compiler directive. 15) What are different styles of Verilog coding I mean gate-level,continuous level and others explain in detail? 16) Can you tell me some of system tasks and their purpose? $display, $displayb, $displayh, $displayo, $write, $writeb, $writeh, $writeo. The most useful of these is $display.This can be used for displaying strings, expression or values of variables. Here are some examples of usage. $display("Hello oni"); --- output: Hello oni $display($time) // current simulation time. --- output: 460 counter = 4'b10; $display(" The count is %b", counter); --- output: The count is 0010 $reset resets the simulation back to time 0; $stop halts the simulator and puts it in interactive mode where the user can enter commands; $finish exits the simulator back to the operating system

17) Can you list out some of enhancements in Verilog 2001? In earlier version of Verilog ,we use 'or' to specify more than one element in sensitivity list . In Verilog 2001, we can use comma as shown in the example below. // Verilog 2k example for usage of comma always @ (i1,i2,i3,i4) Verilog 2001 allows us to use star in sensitive list instead of listing all the variables in RHS of combo logics . This removes typo mistakes and thus avoids simulation and synthesis mismatches, Verilog 2001 allows port direction and data type in the port list of modules as shown in the example below module memory ( input r, input wr, input [7:0] data_in, input [3:0] addr, output [7:0] data_out );

18)Write a Verilog code for synchronous and asynchronous reset? Synchronous reset, synchronous means clock dependent so reset must not be present in sensitivity disk eg: always @ (posedge clk ) begin if (reset) . . . end Asynchronous means clock independent so reset must be present in sensitivity list. Eg Always @(posedge clock or posedge reset) begin if (reset) . . . end 19) What is pli?why is it used? Programming Language Interface (PLI) of Verilog HDL is a mechanism to interface Verilog programs with programs written in C language. It also provides mechanism to access internal databases of the simulator from the C program. PLI is used for implementing system calls which would have been hard to do otherwise (or impossible) using Verilog syntax. Or, in other words, you can take advantage of both the paradigms - parallel and hardware related features of Verilog and sequential flow of C - using PLI. 20) There is a triangle and on it there are 3 ants one on each corner and are free to move along sides of triangle what is probability that they will collide?

Ants can move only along edges of triangle in either of direction, lets say one is represented by 1 and another by 0, since there are 3 sides eight combinations are possible, when all ants are going in same direction they wont collide that is 111 or 000 so probability of not collision is 2/8=1/4 or collision probability is 6/8=3/4

Differentiate between Inter assignment Delay and Inertial Delay. What are the different State machine Styles ? Which is better ? Explain disadvantages and advantages. What is the difference between the following lines of code ?

reg1<= #10 reg2 ; reg3 = # 10 reg4 ; What is the value of Var1 after the following assignment ?

reg Var1; initial begin Var1<= "-" end In the below code, Assume that this statement models a flop with async reset. In this, how does the synthesis tool, figure out which is clock and which is reset. Is the statements within the always block is necessary to find out this or not ?
1 2 3 4 5 6 7 8 9 10 11 12 1 2 3 4 5 6 7 8 9 10 11 module which_clock (x,y,q,d); input x,y,d; output q; reg q; always @ (posedge x or posedge y) if (x) q <= 1'b0; else q <= d; endmodule

What is the output of the two codes below ?

12 13 14 15 16 17 18 19 20 21 22 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22

always @ (posedge clk) begin : FOR_OUT for (i=0; i < 8; i = i + 1) begin if (i == 5) begin disable FOR_OUT; end $display ("Current i : %g",i); end end endmodule module quest_for_in(); integer i; reg clk; initial begin clk = 0; #4 $finish; end always #1 clk = ! clk;

always @ (posedge clk) begin for (i=0; i < 8; i = i + 1) begin : FOR_IN if (i == 5) begin disable FOR_IN; end $display ("Current i : %g",i); end end endmodule

Why cannot initial statement be synthesizeable ? Consider a 2:1 mux; what will the output F be if the Select (sel) is "X" ?

What is the difference between blocking and nonblocking assignments ? What is the difference between wire and reg data type ? Write code for async reset D-Flip-Flop.

Write code for 2:1 MUX using different coding methods. Write code for a parallel encoder and a priority encoder. What is the difference between === and == ? What is defparam used for ? What is the difference between unary and logical operators ? What is the difference between tasks and functions ? What is the difference between transport and inertial delays ? What is the difference between casex and case statements ? What is the difference between $monitor and $display ? What is the difference between compiled, interpreted, event based and cycle based simulators ? What is code coverage and what are the different types of code coverage that one does ?