PIC16F627

PIC16F62X
Data Sheet
FLASH-Based
8-Bit CMOS Microcontroller
 2003 Microchip Technology Inc. Preliminary DS40300C

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The Company’s quality system processes and
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DS40300C - page ii Preliminary  2003 Microchip Technology Inc.

PIC16F62X
FLASH-Based 8-Bit CMOS Microcontrollers
Devices Included in this Data Sheet: • Universal Synchronous/Asynchronous Receiver/
Transmitter USART/SCI
• PIC16F627
• 16 Bytes of common RAM
• PIC16F628
Referred to collectively as PIC16F62X Special Microcontroller Features:
• Power-on Reset (POR)
High Performance RISC CPU:
• Power-up Timer (PWRT) and Oscillator Start-up
• Only 35 instructions to learn Timer (OST)
• All single cycle instructions (200 ns), except for • Brown-out Detect (BOD)
program branches which are two-cycle • Watchdog Timer (WDT) with its own on-chip RC
• Operating speed: oscillator for reliable operation
- DC - 20 MHz clock input • Multiplexed MCLR-pin
- DC - 200 ns instruction cycle • Programmable weak pull-ups on PORTB
Memory • Programmable code protection
• Low voltage programming
Device FLASH RAM EEPROM • Power saving SLEEP mode
Program Data Data
• Selectable oscillator options
PIC16F627 1024 x 14 224 x 8 128 x 8 - FLASH configuration bits for oscillator
PIC16F628 2048 x 14 224 x 8 128 x 8 options
• Interrupt capability - ER (External Resistor) oscillator
• 16 special function hardware registers • Reduced part count
• 8-level deep hardware stack - Dual speed INTRC
• Direct, Indirect and Relative addressing modes • Lower current consumption
- EC External Clock input
Peripheral Features: - XT Oscillator mode
• 16 I/O pins with individual direction control - HS Oscillator mode
• High current sink/source for direct LED drive - LP Oscillator mode
• Analog comparator module with: • In-circuit Serial Programming™ (via two pins)
- Two analog comparators • Four user programmable ID locations
- Programmable on-chip voltage reference CMOS Technology:
(VREF) module
- Programmable input multiplexing from device • Low power, high speed CMOS FLASH technology
inputs and internal voltage reference • Fully static design
- Comparator outputs are externally accessible • Wide operating voltage range
• Timer0: 8-bit timer/counter with 8-bit - PIC16F627 - 3.0V to 5.5V
programmable prescaler - PIC16F628 - 3.0V to 5.5V
• Timer1: 16-bit timer/counter with external crystal/ - PIC16LF627 - 2.0V to 5.5V
clock capability - PIC16LF628 - 2.0V to 5.5V
• Timer2: 8-bit timer/counter with 8-bit period • Commercial, industrial and extended temperature
register, prescaler and postscaler range
• Capture, Compare, PWM (CCP) module • Low power consumption
- Capture is 16-bit, max. resolution is 12.5 ns - < 2.0 mA @ 5.0V, 4.0 MHz
- Compare is 16-bit, max. resolution is 200 ns - 15 µA typical @ 3.0V, 32 kHz
- PWM max. resolution is 10-bit - < 1.0 µA typical standby current @ 3.0V
 2003 Microchip Technology Inc. Preliminary DS40300C-page 1

PIC16F62X
Pin Diagrams
PDIP, SOIC
RA2/AN2/VREF •1 18 RA1/AN1
RA3/AN3/CMP1 2 17 RA0/AN0
PIC16F62X
RA4/TOCKI/CMP2 3 16 RA7/OSC1/CLKIN
RA5/MCLR/VPP 4 15 RA6/OSC2/CLKOUT
VSS 5 14 VDD
RB0/INT 6 13 RB7/T1OSI/PGD
RB1/RX/DT 7 12 RB6/T1OSO/T1CKI/PGC
RB2/TX/CK 8 11 RB5
RB3/CCP1 9 10 RB4/PGM
SSOP
RA2/AN2/VREF •1 20 RA1/AN1
RA3/AN3/CMP1 2 19 RA0/AN0
PIC16F62X
RA4/TOCKI/CMP2 3 18 RA7/OSC1/CLKIN
RA5/MCLR/VPP 4 17 RA6/OSC2/CLKOUT
VSS 5 16 VDD
VSS 6 15 VDD
RB0/INT 7 14 RB7/T1OSI/PGD
RB1/RX/DT 8 13 RB6/T1OSO/T1CKI/PGC
RB2/TX/CK 9 12 RB5
RB3/CCP1 10 11 RB4/PGM
Device Differences
Process
Voltage
Device Oscillator Technology
Range
(Microns)
PIC16F627 3.0 - 5.5 (Note 1) 0.7
PIC16F628 3.0 - 5.5 (Note 1) 0.7
PIC16LF627 2.0 - 5.5 (Note 1) 0.7
PIC16LF628 2.0 - 5.5 (Note 1) 0.7
Note 1: If you change from this device to another device, please verify oscillator characteristics in your
application.
DS40300C-page 2 Preliminary  2003 Microchip Technology Inc.

PIC16F62X
Table of Contents
1.0 General Description...................................................................................................................................................................... 5
2.0 PIC16F62X Device Varieties........................................................................................................................................................ 7
3.0 Architectural Overview ................................................................................................................................................................. 9
4.0 Memory Organization ................................................................................................................................................................. 15
5.0 I/O Ports ..................................................................................................................................................................................... 29
6.0 Timer0 Module ........................................................................................................................................................................... 43
7.0 Timer1 Module ........................................................................................................................................................................... 46
8.0 Timer2 Module ........................................................................................................................................................................... 50
9.0 Comparator Module.................................................................................................................................................................... 53
10.0 Voltage Reference Module......................................................................................................................................................... 59
11.0 Capture/Compare/PWM (CCP) Module ..................................................................................................................................... 61
12.0 Universal Synchronous/ Asynchronous Receiver/ Transmitter (USART) Module...................................................................... 67
13.0 Data EEPROM Memory ............................................................................................................................................................. 87
14.0 Special Features of the CPU...................................................................................................................................................... 91
15.0 Instruction Set Summary .......................................................................................................................................................... 107
16.0 Development Support............................................................................................................................................................... 121
17.0 Electrical Specifications............................................................................................................................................................ 127
18.0 DC and AC Characteristics Graphs and Tables....................................................................................................................... 143
19.0 Packaging Information.............................................................................................................................................................. 157
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PIC16F62X
NOTES:

PIC16F62X
1.0 PIC16F62X DEVICE VARIETIES 1.2 Quick-Turnaround Production
(QTP) Devices
A variety of frequency ranges and packaging options
are available. Depending on application and production Microchip offers a QTP Programming Service for
requirements, the proper device option can be selected factory production orders. This service is made
using the information in the PIC16F62X Product available for users who chose not to program a
Identification System section (Page 167) at the end of medium-to-high quantity of units and whose code
this data sheet. When placing orders, please use this patterns have stabilized. The devices are standard
page of the data sheet to specify the correct part FLASH devices but with all program locations and con-
number. figuration options already programmed by the factory.
Certain code and prototype verification procedures
1.1 FLASH Devices apply before production shipments are available.
Please contact your Microchip Technology sales office
FLASH devices can be erased and reprogrammed
for more details.
electrically. This allows the same device to be used for
prototype development, pilot programs and production.
1.3 Serialized Quick-Turnaround
A further advantage of the electrically-erasable FLASH Production (SQTPsm) Devices
is that it can be erased and reprogrammed in-circuit, or
by device programmers, such as Microchip's Microchip offers a unique programming service where
PICSTART® Plus, or PRO MATE® II programmers. a few user-defined locations in each device are
programmed with different serial numbers. The serial
numbers may be random, pseudo-random or
sequential.
Serial programming allows each device to have a
unique number which can serve as an entry-code,
password or ID number.

PIC16F62X
NOTES:

PIC16F62X
2.0 ARCHITECTURAL OVERVIEW The ALU is 8-bit wide and capable of addition,
subtraction, shift and logical operations. Unless
The high performance of the PIC16F62X family can be otherwise mentioned, arithmetic operations are two's
attributed to a number of architectural features complement in nature. In two-operand instructions,
commonly found in RISC microprocessors. To begin typically one operand is the working register
with, the PIC16F62X uses a Harvard architecture, in (W register). The other operand is a file register or an
which, program and data are accessed from separate immediate constant. In single operand instructions, the
memories using separate buses. This improves operand is either the W register or a file register.
bandwidth over traditional Von Neumann architecture
The W register is an 8-bit working register used for ALU
where program and data are fetched from the same
operations. It is not an addressable register.
memory. Separating program and data memory further
allows instructions to be sized differently than 8-bit Depending on the instruction executed, the ALU may
wide data word. Instruction opcodes are 14-bits wide affect the values of the Carry (C), Digit Carry (DC), and
making it possible to have all single-word instructions. Zero (Z) bits in the STATUS register. The C and DC bits
A 14-bit wide program memory access bus fetches a operate as a Borrow and Digit Borrow out bit,
14-bit instruction in a single cycle. A two-stage pipeline respectively, bit in subtraction. See the SUBLW and
overlaps fetch and execution of instructions. SUBWF instructions for examples.
Consequently, all instructions (35) execute in a single A simplified block diagram is shown in Figure 2-1, and
cycle (200 ns @ 20 MHz) except for program a description of the device pins in Table 2-1.
branches.
Two types of data memory are provided on the
The Table below lists program memory (FLASH, Data PIC16F62X devices. Non-volatile EEPROM data
and EEPROM). memory is provided for long term storage of data such
as calibration values, lookup table data, and any other
TABLE 2-1: DEVICE DESCRIPTION data which may require periodic updating in the field.
This data is not lost when power is removed. The other
Memory data memory provided is regular RAM data memory.
Device FLASH RAM EEPROM
Regular RAM data memory is provided for temporary
Program Data Data storage of data during normal operation. It is lost when
power is removed.
PIC16F627 1024 x 14 224 x 8 128 x 8
PIC16F628 2048 x 14 224 x 8 128 x 8
PIC16LF627 1024 x 14 224 x 8 128 x 8
PIC16LF628 2048 x 14 224 x 8 128 x 8
The PIC16F62X can directly or indirectly address its

register files or data memory. All Special Function
registers, including the program counter, are mapped in
the data memory. The PIC16F62X have an orthogonal
(symmetrical) instruction set that makes it possible to
carry out any operation, on any register, using any
Addressing mode. This symmetrical nature, and lack of
‘special optimal situations’ make programming with the
PIC16F62X simple yet efficient. In addition, the learning
curve is reduced significantly.
The PIC16F62X devices contain an 8-bit ALU and
working register. The ALU is a general purpose
arithmetic unit. It performs arithmetic and Boolean
functions between data in the working register and any
register file.

PIC16F62X
FIGURE 2-1: BLOCK DIAGRAM
13 Data Bus 8
FLASH Program Counter
Program
Memory RAM
8-Level Stack File
(13-bit) Registers
Program 14
Bus RAM Addr (1) 9 PORTA
Addr MUX RA0/AN0

Instruction reg
RA1/AN1
Direct Addr 7 Indirect RA2/AN2/VREF
8 Addr
RA3/AN3/CMP1
FSR reg RA4/T0CK1/CMP2
RA5/MCLR/VPP
STATUS reg RA6/OSC2/CLKOUT
8 RA7/OSC1/CLKIN
3 MUX PORTB
Power-up
Timer RB0/INT
RB1/RX/DT
Instruction Oscillator
Decode & Start-up Timer RB2/TX/CK
ALU RB3/CCP1
Control
Power-on RB4/PGM
Reset 8
RB5
Timing Watchdog RB6/T1OSO/T1CKI/PGC
Generation Timer W reg
RB7/T1OSI/PGD
OSC1/CLKIN Brown-out
OSC2/CLKOUT Detect
Low-voltage
Programming
MCLR VDD, VSS
Comparator Timer0 Timer1 Timer2
VREF CCP1 USART Data EEPROM
Note 1: Higher order bits are from the STATUS register.

PIC16F62X
TABLE 2-1: PIC16F62X PINOUT DESCRIPTION

Name Function Input Type Output Type Description
RA0/AN0 RA0 ST CMOS Bi-directional I/O port
AN0 AN — Analog comparator input
RA2/AN2/VREF RA2 ST CMOS Bi-directional I/O port
VREF — AN VREF output
RA3/AN3/CMP1 RA3 ST CMOS Bi-directional I/O port
CMP1 — CMOS Comparator 1 output
RA4/T0CKI/CMP2 RA4 ST OD Bi-directional I/O port
T0CKI ST — Timer0 clock input
CMP2 — OD Comparator 2 output
RA5/MCLR/VPP RA5 ST — Input port
MCLR ST — Master clear

VPP — — Programming voltage input. When configured
as MCLR, this pin is an active low RESET to
the device. Voltage on MCLR/VPP must not
exceed VDD during normal device operation.
RA6/OSC2/CLKOUT RA6 ST CMOS Bi-directional I/O port
OSC2 XTAL — Oscillator crystal output. Connects to crystal
or resonator in Crystal Oscillator mode.
CLKOUT — CMOS In ER/INTRC mode, OSC2 pin can output
CLKOUT, which has 1/4 the frequency of
OSC1
RA7/OSC1/CLKIN RA7 ST CMOS Bi-directional I/O port
OSC1 XTAL — Oscillator crystal input
CLKIN ST — External clock source input. ER biasing pin.
RB0/INT RB0 TTL CMOS Bi-directional I/O port. Can be software
programmed for internal weak pull-up.
INT ST — External interrupt.
RB1/RX/DT RB1 TTL CMOS Bi-directional I/O port. Can be software
RX ST — USART receive pin
DT ST CMOS Synchronous data I/O.
RB2/TX/CK RB2 TTL CMOS Bi-directional I/O port.
TX — CMOS USART transmit pin
CK ST CMOS Synchronous clock I/O. Can be software
RB3/CCP1 RB3 TTL CMOS Bi-directional I/O port. Can be software
CCP1 ST CMOS Capture/Compare/PWM I/O
Legend: O = Output CMOS = CMOS Output P = Power
— = Not used I = Input ST = Schmitt Trigger Input
TTL = TTL Input OD = Open Drain Output AN = Analog

PIC16F62X
TABLE 2-1: PIC16F62X PINOUT DESCRIPTION (CONTINUED)
Name Function Input Type Output Type Description
RB4/PGM RB4 TTL CMOS Bi-directional I/O port. Can be software
PGM ST — Low voltage programming input pin. Interrupt-
on-pin change. When low voltage program-
ming is enabled, the interrupt-on-pin change
and weak pull-up resistor are disabled.
RB5 RB5 TTL CMOS Bi-directional I/O port. Interrupt-on-pin
change. Can be software programmed for
internal weak pull-up.
RB6/T1OSO/T1CKI/PGC RB6 TTL CMOS Bi-directional I/O port. Interrupt-on-pin
T1OSO — XTAL Timer1 oscillator output.
T1CKI ST — Timer1 clock input.
PGC ST — ICSP™ Programming Clock.
RB7/T1OSI/PGD RB7 TTL CMOS Bi-directional I/O port. Interrupt-on-pin
T1OSI XTAL — Timer1 oscillator input. Wake-up from SLEEP
on pin change. Can be software programmed
for internal weak pull-up.
PGD ST CMOS ICSP Data I/O
VSS VSS Power — Ground reference for logic and I/O pins
VDD VDD Power — Positive supply for logic and I/O pins

PIC16F62X
2.1 Clocking Scheme/Instruction 2.2 Instruction Flow/Pipelining
Cycle An “Instruction Cycle” consists of four Q cycles (Q1,
The clock input (OSC1/CLKIN/RA7 pin) is internally Q2, Q3 and Q4). The instruction fetch and execute are
divided by four to generate four non-overlapping pipelined such that fetch takes one instruction cycle
quadrature clocks namely Q1, Q2, Q3 and Q4. while decode and execute takes another instruction
Internally, the program counter (PC) is incremented cycle. However, due to the pipelining, each instruction
every Q1, the instruction is fetched from the program effectively executes in one cycle. If an instruction
memory and latched into the instruction register in Q4. causes the program counter to change, (e.g., GOTO)
The instruction is decoded and executed during the then two cycles are required to complete the instruction
following Q1 through Q4. The clocks and instruction (Example 2-1).
execution flow is shown in Figure 2-2. A fetch cycle begins with the program counter (PC)
incrementing in Q1.
In the execution cycle, the fetched instruction is latched
into the “Instruction Register (IR)” in cycle Q1. This
instruction is then decoded and executed during the
Q2, Q3, and Q4 cycles. Data memory is read during Q2
(operand read) and written during Q4 (destination
write).
FIGURE 2-2: CLOCK/INSTRUCTION CYCLE
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
Q1
Q2 Internal
phase
Q3 clock
Q4
PC PC PC+1 PC+2
CLKOUT
Fetch INST (PC)
Execute INST (PC-1) Fetch INST (PC+1)
Execute INST (PC) Fetch INST (PC+2)
Execute INST (PC+1)
EXAMPLE 2-1: INSTRUCTION PIPELINE FLOW
1. MOVLW 55h Fetch 1 Execute 1

2. MOVWF PORTB Fetch 2 Execute 2
3. CALL SUB_1 Fetch 3 Execute 3
4. BSF PORTA, 3 Fetch 4 Flush
Fetch SUB_1 Execute SUB_1
All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction
is “flushed” from the pipeline while the new instruction is being fetched and then executed.

PIC16F62X
NOTES:

PIC16F62X
3.0 MEMORY ORGANIZATION 3.2 Data Memory Organization
The data memory (Figure 3-2) is partitioned into four
3.1 Program Memory Organization
banks, which contain the general purpose registers and
The PIC16F62X has a 13-bit program counter capable the Special Function Registers (SFR). The SFR’s are
of addressing an 8K x 14 program memory space. Only located in the first 32 locations of each Bank. Register
the first 1K x 14 (0000h - 03FFh) for the PIC16F627 locations 20-7Fh, A0h-FFh, 120h-14Fh, 170h-17Fh
and 2K x 14 (0000h - 07FFh) for the PIC16F628 are and 1F0h-1FFh are general purpose registers
physically implemented. Accessing a location above implemented as static RAM.
these boundaries will cause a wrap-around within the The Table below lists how to access the four banks of
first 1K x 14 space (PIC16F627) or 2K x 14 space registers:
(PIC16F628). The RESET vector is at 0000h and the
interrupt vector is at 0004h (Figure 3-1). RP1 RP0
Bank0 0 0
FIGURE 3-1: PROGRAM MEMORY MAP
AND STACK Bank1 0 1
Bank2 1 0
PC<12:0>
Bank3 1 1
CALL, RETURN 13
RETFIE, RETLW Addresses F0h-FFh, 170h-17Fh and 1F0h-1FFh are
implemented as common RAM and mapped back to
Stack Level 1
addresses 70h-7Fh.
Stack Level 2
3.2.1 GENERAL PURPOSE REGISTER
Stack Level 8 FILE
The register file is organized as 224 x 8 in the
RESET Vector 000h PIC16F62X. Each is accessed either directly or
indirectly through the File Select Register FSR (See
Section 3.4).
Interrupt Vector 0004

0005
On-chip Program
Memory
PIC16F627 and
PIC16F628
03FFh
On-chip Program
Memory
PIC16F628 only
07FFh
1FFFh

PIC16F62X
FIGURE 3-2: DATA MEMORY MAP OF THE PIC16F627 AND PIC16F628
File
Address
Indirect addr.(1) 00h Indirect addr.(1) 80h Indirect addr.(1) 100h Indirect addr.(1) 180h
TMR0 01h OPTION 81h TMR0 101h OPTION 181h
PCL 02h PCL 82h PCL 102h PCL 182h
STATUS 03h STATUS 83h STATUS 103h STATUS 183h
FSR 04h FSR 84h FSR 104h FSR 184h
PORTA 05h TRISA 85h 105h 185h
PORTB 06h TRISB 86h PORTB 106h TRISB 186h
07h 87h 107h 187h
08h 88h 108h 188h
09h 89h 109h 189h
PCLATH 0Ah PCLATH 8Ah PCLATH 10Ah PCLATH 18Ah
INTCON 0Bh INTCON 8Bh INTCON 10Bh INTCON 18Bh
PIR1 0Ch PIE1 8Ch 10Ch 18Ch
0Dh 8Dh 10Dh 18Dh
TMR1L 0Eh PCON 8Eh 10Eh 18Eh
TMR1H 0Fh 8Fh 10Fh 18Fh
T1CON 10h 90h
TMR2 11h 91h
T2CON 12h PR2 92h
13h 93h
14h 94h
CCPR1L 15h 95h
CCPR1H 16h 96h
CCP1CON 17h 97h
RCSTA 18h TXSTA 98h
TXREG 19h SPBRG 99h
RCREG 1Ah EEDATA 9Ah
1Bh EEADR 9Bh
1Ch EECON1 9Ch
1Dh EECON2(1) 9Dh
1Eh 9Eh
CMCON 1Fh VRCON 9Fh 11Fh
20h General 120h
A0h Purpose
General General Register
Purpose Purpose 48 Bytes 14Fh
Register Register
150h
80 Bytes
80 Bytes
6Fh EFh 16Fh 1EFh

70h F0h 170h 1F0h
accesses accesses accesses
16 Bytes
70h-7Fh 70h-7Fh 70h - 7Fh
7Fh FFh 17Fh 1FFh
Bank 0 Bank 1 Bank 2 Bank 3
Unimplemented data memory locations, read as '0'.

Note 1: Not a physical register.

PIC16F62X
3.2.2 SPECIAL FUNCTION REGISTERS
The SFRs are registers used by the CPU and Periph-
eral functions for controlling the desired operation of
the device (Table 3-1). These registers are static RAM.
The special registers can be classified into two sets
(core and peripheral). The SFRs associated with the
“core” functions are described in this section. Those
related to the operation of the peripheral features are
described in the section of that peripheral feature.
TABLE 3-1: SPECIAL REGISTERS SUMMARY BANK 0

Value on
Details
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR
on Page
Reset(1)
Bank 0
00h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 25
01h TMR0 Timer0 Module’s Register xxxx xxxx 43
02h PCL Program Counter's (PC) Least Significant Byte 0000 0000 13
03h STATUS IRP RP1 RP0 TO PD Z DC C 0001 1xxx 19
04h FSR Indirect data memory address pointer xxxx xxxx 25
05h PORTA RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 xxxx 0000 29
06h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx 34
07h — Unimplemented — —
0Ah PCLATH — — — Write buffer for upper 5 bits of program counter ---0 0000 25
0Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 21
0Ch PIR1 EEIF CMIF RCIF TXIF — CCP1IF TMR2IF TMR1IF 0000 -000 23
0Dh — Unimplemented — —
0Eh TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 xxxx xxxx 46
0Fh TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 xxxx xxxx 46
10h T1CON — — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 46
11h TMR2 TMR2 module’s register 0000 0000 50
12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 50
15h CCPR1L Capture/Compare/PWM register (LSB) xxxx xxxx 61
16h CCPR1H Capture/Compare/PWM register (MSB) xxxx xxxx 61
17h CCP1CON — — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 61
18h RCSTA SPEN RX9 SREN CREN ADEN FERR OERR RX9D 0000 -00x 67
19h TXREG USART Transmit data register 0000 0000 74
1Ah RCREG USART Receive data register 0000 0000 77
1Bh — Unimplemented — —
1Ch — Unimplemented — —
1Eh — Unimplemented — —
1Fh CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 0000 0000 53
Legend: — = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition,
shaded = unimplemented
Note 1: For the Initialization Condition for Registers Tables, refer to Table 14-7 and Table 14-8 on page 98.

PIC16F62X
TABLE 3-2: SPECIAL FUNCTION REGISTERS SUMMARY BANK 1
Value on
Details on
Page
Reset(1)
Bank 1
80h INDF Addressing this location uses contents of FSR to address data memory (not a physical xxxx xxxx 25
register)
81h OPTION RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 20
85h TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 1111 1111 29
86h TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 34
8Ch PIE1 EEIE CMIE RCIE TXIE — CCP1IE TMR2IE TMR1IE 0000 -000 22
8Eh PCON — — — — OSCF — POR BOD ---- 1-0x 24
8Fh — Unimplemented — —
92h PR2 Timer2 Period Register 1111 1111 50
98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 69
99h SPBRG Baud Rate Generator Register 0000 0000 69
9Ah EEDATA EEPROM data register xxxx xxxx 87
9Bh EEADR — EEPROM address register xxxx xxxx 87
9Ch EECON1 — — — — WRERR WREN WR RD ---- x000 87
9Dh EECON2 EEPROM control register 2 (not a physical register) -------- 87
9Fh VRCON VREN VROE VRR — VR3 VR2 VR1 VR0 000- 0000 59
Legend: — = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unim-
plemented

PIC16F62X
Value on
Details on
Page
Reset(1)
Bank 2
100h INDF Addressing this location uses contents of FSR to address data memory (not a physical reg- xxxx xxxx 25
ister)
101h TMR0 RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 43
106h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx 34
11Ah — Unimplemented — —
plemented.

PIC16F62X
Value on
Details on
Page
Reset(1)
Bank 3
180h INDF Addressing this location uses contents of FSR to address data memory (not a physical reg- xxxx xxxx 25
ister)
181h OPTION RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 20
186h TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 34
19Ah — Unimplemented — —
plemented

PIC16F62X
3.2.2.1 STATUS Register For example, CLRF STATUS will clear the upper-three
bits and set the Z bit. This leaves the STATUS register
The STATUS register, shown in Register 3-1, contains
as 000uu1uu (where u = unchanged).
the arithmetic status of the ALU, the RESET status and
the bank select bits for data memory (SRAM). It is recommended, therefore, that only BCF, BSF,
SWAPF and MOVWF instructions are used to alter the
The STATUS register can be the destination for any
STATUS register because these instructions do not
instruction, like any other register. If the STATUS
affect any STATUS bit. For other instructions, not
register is the destination for an instruction that affects
affecting any STATUS bits, see the “Instruction Set
the Z, DC or C bits, then the write to these three bits is
Summary”.
disabled. These bits are set or cleared according to the
device logic. Furthermore, the TO and PD bits are not Note 1: The C and DC bits operate as a Borrow
writable. Therefore, the result of an instruction with the and Digit Borrow out bit, respectively, in
STATUS register as destination may be different than subtraction. See the SUBLW and SUBWF
intended. instructions for examples.
REGISTER 3-1: STATUS REGISTER (ADDRESS: 03h, 83h, 103h, 183h)

R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x
IRP RP1 RP0 TO PD Z DC C
bit 7 bit 0
bit 7 IRP: Register Bank Select bit (used for indirect addressing)
1 = Bank 2, 3 (100h - 1FFh)
0 = Bank 0, 1 (00h - FFh)
bit 6-5 RP1:RP0: Register Bank Select bits (used for direct addressing)
00 = Bank 0 (00h - 7Fh)
01 = Bank 1 (80h - FFh)
10 = Bank 2 (100h - 17Fh)
11 = Bank 3 (180h - 1FFh)
bit 4 TO: Timeout bit
1 = After power-up, CLRWDT instruction, or SLEEP instruction
0 = A WDT timeout occurred
bit 3 PD: Power-down bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
bit 2 Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1 DC: Digit carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions) (for borrow the polarity
is reversed)
1 = A carry-out from the 4th low order bit of the result occurred
0 = No carry-out from the 4th low order bit of the result
bit 0 C: Carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)
1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred
Note 1: For borrow the polarity is reversed. A subtraction is executed by adding the two’s
complement of the second operand. For rotate (RRF, RLF) instructions, this bit is
loaded with either the high or low order bit of the source register.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

PIC16F62X
3.2.2.2 OPTION Register
Note: To achieve a 1:1 prescaler assignment for
The OPTION register is a readable and writable
TMR0, assign the prescaler to the WDT
register which contains various control bits to configure
(PSA = 1). See Section 6.3.1
the TMR0/WDT prescaler, the external RB0/INT
interrupt, TMR0, and the weak pull-ups on PORTB.
REGISTER 3-2: OPTION REGISTER (ADDRESS: 81h, 181h)

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0
bit 7 bit 0
bit 7 RBPU: PORTB Pull-up Enable bit

1 = PORTB pull-ups are disabled
0 = PORTB pull-ups are enabled by individual port latch values
bit 6 INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of RB0/INT pin
0 = Interrupt on falling edge of RB0/INT pin
bit 5 T0CS: TMR0 Clock Source Select bit
1 = Transition on RA4/T0CKI pin
0 = Internal instruction cycle clock (CLKOUT)
bit 4 T0SE: TMR0 Source Edge Select bit
1 = Increment on high-to-low transition on RA4/T0CKI pin
0 = Increment on low-to-high transition on RA4/T0CKI pin
bit 3 PSA: Prescaler Assignment bit
1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module
bit 2-0 PS2:PS0: Prescaler Rate Select bits
Bit Value TMR0 Rate WDT Rate
000 1:2 1:1

001 1:4 1:2
010 1:8 1:4
011 1 : 16 1:8
100 1 : 32 1 : 16
101 1 : 64 1 : 32
110 1 : 128 1 : 64
111 1 : 256 1 : 128
Legend:

PIC16F62X
3.2.2.3 INTCON Register
Note: Interrupt flag bits get set when an interrupt
The INTCON register is a readable and writable
condition occurs regardless of the state of
register which contains the various enable and flag bits
its corresponding enable bit or the global
for all interrupt sources except the comparator module.
enable bit, GIE (INTCON<7>).
See Section 3.2.2.4 and Section 3.2.2.5 for a
description of the comparator enable and flag bits.
REGISTER 3-3: INTCON REGISTER (ADDRESS: 0Bh, 8Bh, 10Bh, 18Bh)

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x
GIE PEIE T0IE INTE RBIE T0IF INTF RBIF
bit 7 bit 0
bit 7 GIE: Global Interrupt Enable bit

1 = Enables all unmasked interrupts
0 = Disables all interrupts
bit 6 PEIE: Peripheral Interrupt Enable bit
1 = Enables all unmasked peripheral interrupts
0 = Disables all peripheral interrupts
bit 5 T0IE: TMR0 Overflow Interrupt Enable bit
1 = Enables the TMR0 interrupt
0 = Disables the TMR0 interrupt
bit 4 INTE: RB0/INT External Interrupt Enable bit
1 = Enables the RB0/INT external interrupt
0 = Disables the RB0/INT external interrupt
bit 3 RBIE: RB Port Change Interrupt Enable bit
1 = Enables the RB port change interrupt
0 = Disables the RB port change interrupt
bit 2 T0IF: TMR0 Overflow Interrupt Flag bit
1 = TMR0 register has overflowed (must be cleared in software)
0 = TMR0 register did not overflow
bit 1 INTF: RB0/INT External Interrupt Flag bit
1 = The RB0/INT external interrupt occurred (must be cleared in software)
0 = The RB0/INT external interrupt did not occur
bit 0 RBIF: RB Port Change Interrupt Flag bit
1 = When at least one of the RB7:RB4 pins changed state (must be cleared in software)
0 = None of the RB7:RB4 pins have changed state
Legend:

PIC16F62X
3.2.2.4 PIE1 Register
This register contains interrupt enable bits.
REGISTER 3-4: PIE1 REGISTER (ADDRESS: 8Ch)

R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0
EEIE CMIE RCIE TXIE — CCP1IE TMR2IE TMR1IE
bit 7 bit 0
bit 7 EEIE: EE Write Complete Interrupt Enable Bit

1 = Enables the EE write complete interrupt
0 = Disables the EE write complete interrupt
bit 6 CMIE: Comparator Interrupt Enable bit
1 = Enables the comparator interrupt
0 = Disables the comparator interrupt
bit 5 RCIE: USART Receive Interrupt Enable bit
1 = Enables the USART receive interrupt
0 = Disables the USART receive interrupt
bit 4 TXIE: USART Transmit Interrupt Enable bit
1 = Enables the USART transmit interrupt
0 = Disables the USART transmit interrupt
bit 3 Unimplemented: Read as ‘0’
bit 2 CCP1IE: CCP1 Interrupt Enable bit
1 = Enables the CCP1 interrupt
0 = Disables the CCP1 interrupt
bit 1 TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1 = Enables the TMR2 to PR2 match interrupt
0 = Disables the TMR2 to PR2 match interrupt
bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit
1 = Enables the TMR1 overflow interrupt
0 = Disables the TMR1 overflow interrupt
Legend:

PIC16F62X
3.2.2.5 PIR1 Register
Note: Interrupt flag bits get set when an interrupt
This register contains interrupt flag bits. condition occurs regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User
software should ensure the appropriate
interrupt flag bits are clear prior to enabling
an interrupt.
REGISTER 3-5: PIR1 REGISTER (ADDRESS: 0Ch)

R/W-0 R/W-0 R-0 R-0 U-0 R/W-0 R/W-0 R/W-0
EEIF CMIF RCIF TXIF — CCP1IF TMR2IF TMR1IF
bit 7 bit 0
bit 7 EEIF: EEPROM Write Operation Interrupt Flag bit

1 = The write operation completed (must be cleared in software)
0 = The write operation has not completed or has not been started
bit 6 CMIF: Comparator Interrupt Flag bit
1 = Comparator output has changed
0 = Comparator output has not changed
bit 5 RCIF: USART Receive Interrupt Flag bit
1 = The USART receive buffer is full
0 = The USART receive buffer is empty
bit 4 TXIF: USART Transmit Interrupt Flag bit
1 = The USART transmit buffer is empty
0 = The USART transmit buffer is full
bit 3 Unimplemented: Read as ‘0’
bit 2 CCP1IF: CCP1 Interrupt Flag bit
Capture Mode
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred
Compare Mode
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM Mode
Unused in this mode
bit 1 TMR2IF: TMR2 to PR2 Match Interrupt Flag bit
1 = TMR2 to PR2 match occurred (must be cleared in software)
0 = No TMR2 to PR2 match occurred
bit 0 TMR1IF: TMR1 Overflow Interrupt Flag bit
1 = TMR1 register overflowed (must be cleared in software)
0 = TMR1 register did not overflow
Legend:

PIC16F62X
3.2.2.6 PCON Register
The PCON register contains flag bits to differentiate Note: BOD is unknown on Power-on Reset. It
between a Power-on Reset, an external MCLR Reset, must then be set by the user and checked
WDT Reset or a Brown-out Detect. on subsequent RESETS to see if BOD is
cleared, indicating a brown-out has
occurred. The BOD STATUS bit is a “don't
care” and is not necessarily predictable if
the brown-out circuit is disabled (by
clearing the BODEN bit in the
Configuration word).
REGISTER 3-6: PCON REGISTER (ADDRESS: 0Ch)

U-0 U-0 U-0 U-0 R/W-1 U-0 R/W-q R/W-q
— — — — OSCF — POR BOD
bit 7 bit 0
bit 7-4 Unimplemented: Read as '0'

bit 3 OSCF: INTRC/ER oscillator frequency
1 = 4 MHz typical(1)
0 = 37 KHz typical
bit 2 Unimplemented: Read as '0'
bit 1 POR: Power-on Reset STATUS bit
1 = No Power-on Reset occurred
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
bit 0 BOD: Brown-out Detect STATUS bit
1 = No Brown-out Reset occurred
0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)
Note 1: When in ER Oscillator mode, setting OSCF = 1 will cause the oscillator frequency to
change to the frequency specified by the external resistor.
Legend:

PIC16F62X
3.3 PCL and PCLATH The stack operates as a circular buffer. This means that
after the stack has been PUSHed eight times, the ninth
The program counter (PC) is 13-bits wide. The low byte push overwrites the value that was stored from the first
comes from the PCL register, which is a readable and push. The tenth push overwrites the second push (and
writable register. The high byte (PC<12:8>) is not so on).
directly readable or writable and comes from PCLATH.
On any RESET, the PC is cleared. Figure 3-3 shows Note 1: There are no STATUS bits to indicate
the two situations for the loading of the PC. The upper stack overflow or stack underflow
example in the figure shows how the PC is loaded on a conditions.
write to PCL (PCLATH<4:0> → PCH). The lower exam- 2: There are no instructions/mnemonics
ple in the figure shows how the PC is loaded during a called PUSH or POP. These are actions
CALL or GOTO instruction (PCLATH<4:3> → PCH). that occur from the execution of the
CALL, RETURN, RETLW and RETFIE
FIGURE 3-3: LOADING OF PC IN instructions, or the vectoring to an
DIFFERENT SITUATIONS interrupt address.
PCH PCL
3.4 Indirect Addressing, INDF and
12 8 7 0
FSR Registers
Instruction with
PC PCL as The INDF register is not a physical register. Addressing
Destination
PCLATH<4:0> 8 the INDF register will cause indirect addressing.
5 ALU result
Indirect addressing is possible by using the INDF
register. Any instruction using the INDF register actu-
PCLATH
ally accesses data pointed to by the file select register
(FSR). Reading INDF itself indirectly will produce 00h.
PCH PCL
Writing to the INDF register indirectly results in a no-
12 11 10 8 7 0
operation (although STATUS bits may be affected). An
PC GOTO, CALL
effective 9-bit address is obtained by concatenating the
2
PCLATH<4:3> 11 8-bit FSR register and the IRP bit (STATUS<7>), as
Opcode <10:0>
shown in Figure 3-4.
PCLATH A simple program to clear RAM location 20h-2Fh using
indirect addressing is shown in Example 3-1.
3.3.1 COMPUTED GOTO EXAMPLE 3-1: Indirect Addressing

movlw 0x20 ;initialize pointer
A computed GOTO is accomplished by adding an offset
movwf FSR ;to RAM
to the program counter (ADDWF PCL). When doing a NEXT clrf INDF ;clear INDF register
table read using a computed GOTO method, care incf FSR ;inc pointer
should be exercised if the table location crosses a PCL btfss FSR,4 ;all done?
memory boundary (each 256 byte block). Refer to the goto NEXT ;no clear next
application note “Implementing a Table Read” (AN556). ;yes continue
3.3.2 STACK
The PIC16F62X family has an 8-level deep x 13-bit
wide hardware stack (Figure 3-1 and Figure 3-2). The
stack space is not part of either program or data space
and the stack pointer is not readable or writable. The
PC is PUSHed onto the stack when a CALL instruction
is executed or an interrupt causes a branch. The stack
is POPed in the event of a RETURN, RETLW or a
RETFIE instruction execution. PCLATH is not affected
by a PUSH or POP operation.

PIC16F62X
FIGURE 3-4: DIRECT/INDIRECT ADDRESSING PIC16F62X
Direct Addressing Indirect Addressing
RP1 RP0 6 from opcode 0 IRP 7 FSR register 0
bank select location select bank select location select

00 01 10 11
00h 180h
RAM
File
Registers
7Fh 1FFh
Bank 0 Bank 1 Bank 2 Bank 3
Note: For memory map detail see Figure 3-2.

PIC16F62X
4.0 GENERAL DESCRIPTION The SLEEP (Power-down) mode offers power savings.
The user can wake-up the chip from SLEEP through
The PIC16F62X are 18-Pin FLASH-based members of several external interrupts, internal interrupts, and
the versatile PIC16CXX family of low cost, high perfor- RESETS.
mance, CMOS, fully static, 8-bit microcontrollers.
A highly reliable Watchdog Timer with its own on-chip
All PICmicro® microcontrollers employ an advanced RC oscillator provides protection against software lock-
RISC architecture. The PIC16F62X have enhanced up.
core features, eight-level deep stack, and multiple
Table 4-1 shows the features of the PIC16F62X mid-
internal and external interrupt sources. The separate
range microcontroller families.
instruction and data buses of the Harvard architecture
allow a 14-bit wide instruction word with the separate 8- A simplified block diagram of the PIC16F62X is shown
bit wide data. The two-stage instruction pipeline allows in Figure 2.1.
all instructions to execute in a single cycle, except for The PIC16F62X series fits in applications ranging from
program branches (which require two cycles). A total of battery chargers to low power remote sensors. The
35 instructions (reduced instruction set) are available. FLASH technology makes customization of application
Additionally, a large register set gives some of the programs (detection levels, pulse generation, timers,
architectural innovations used to achieve a very high etc.) extremely fast and convenient. The small footprint
performance. packages make this microcontroller series ideal for all
PIC16F62X microcontrollers typically achieve a 2:1 applications with space limitations. Low cost, low
code compression and a 4:1 speed improvement over power, high performance, ease of use and I/O flexibility
other 8-bit microcontrollers in their class. make the PIC16F62X very versatile.
PIC16F62X devices have special features to reduce
4.1 Development Support
external components, thus reducing system cost,
enhancing system reliability and reducing power con- The PIC16F62X family is supported by a full featured
sumption. macro assembler, a software simulator, an in-circuit
The PIC16F62X has eight oscillator configurations. emulator, a low cost development programmer and a
The single pin ER oscillator provides a low cost solu- full-featured programmer. A Third Party “C” compiler
tion. The LP oscillator minimizes power consumption, support tool is also available.
XT is a standard crystal, INTRC is a self-contained
internal oscillator. The HS is for High Speed crystals.
The EC mode is for an external clock source.
TABLE 4-1: PIC16F62X FAMILY OF DEVICES

PIC16F627 PIC16F628 PIC16LF627 PIC16LF628
Clock Maximum Frequency of Operation 20 20 4 4
(MHz)
FLASH Program Memory (words) 1024 2048 1024 2048
Memory RAM Data Memory (bytes) 224 224 224 224
EEPROM Data Memory (bytes) 128 128 128 128
Timer Module(s) TMR0, TMR1, TMR2 TMR0, TMR1, TMR2 TMR0, TMR1, TMR2 TMR0, TMR1, TMR2
Comparator(s) 2 2 2 2
Peripherals Capture/Compare/PWM modules 1 1 1 1
Serial Communications USART USART USART USART
Internal Voltage Reference Yes Yes Yes Yes
Interrupt Sources 10 10 10 10
I/O Pins 16 16 16 16
Features Voltage Range (Volts) 3.0-5.5 3.0-5.5 2.0-5.5 2.0-5.5
Brown-out Detect Yes Yes Yes Yes
Packages 18-pin DIP, SOIC, 18-pin DIP, SOIC, 18-pin DIP, SOIC, 18-pin DIP, SOIC,
20-pin SSOP 20-pin SSOP 20-pin SSOP 20-pin SSOP
All PICmicro® Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O current capability. All
PIC16F62X Family devices use serial programming with clock pin RB6 and data pin RB7.

PIC16F62X
NOTES:

PIC16F62X
5.0 I/O PORTS
Note 1: On RESET, the TRISA register is set to all
The PIC16F62X have two ports, PORTA and PORTB. inputs. The digital inputs are disabled and
Some pins for these I/O ports are multiplexed with an the comparator inputs are forced to
alternate function for the peripheral features on the ground to reduce current consumption.
device. In general, when a peripheral is enabled, that
2: TRISA<6:7> is overridden by oscillator
pin may not be used as a general purpose I/O pin.
configuration. When PORTA<6:7> is
overridden, the data reads ‘0’ and the
5.1 PORTA and TRISA Registers
TRISA<6:7> bits are ignored.
PORTA is an 8-bit wide latch. RA4 is a Schmitt Trigger TRISA controls the direction of the RA pins, even when
input and an open drain output. Port RA4 is multiplexed they are being used as comparator inputs. The user
with the T0CKI clock input. RA5 is a Schmitt Trigger must make sure to keep the pins configured as inputs
input only and has no output drivers. All other RA port when using them as comparator inputs.
pins have Schmitt Trigger input levels and full CMOS
output drivers. All pins have data direction bits (TRIS The RA2 pin will also function as the output for the
registers) which can configure these pins as input or voltage reference. When in this mode, the VREF pin is a
output. very high impedance output. The user must configure
TRISA<2> bit as an input and use high impedance
A '1' in the TRISA register puts the corresponding out- loads.
put driver in a Hi-impedance mode. A '0' in the TRISA
register puts the contents of the output latch on the In one of the Comparator modes defined by the
selected pin(s). CMCON register, pins RA3 and RA4 become outputs
of the comparators. The TRISA<4:3> bits must be
Reading the PORTA register reads the status of the cleared to enable outputs to use this function.
pins whereas writing to it will write to the port latch. All
write operations are read-modify-write operations. So a
EXAMPLE 5-1: Initializing PORTA
write to a port implies that the port pins are first read,
then this value is modified and written to the port data CLRF PORTA ;Initialize PORTA by
latch. ;setting output data latches
MOVLW 0x07 ;Turn comparators off and
The PORTA pins are multiplexed with comparator and MOVWF CMCON ;enable pins for I/O
voltage reference functions. The operation of these ;functions
pins are selected by control bits in the CMCON BCF STATUS, RP1
(comparator control register) register and the VRCON BSF STATUS, RP0;Select Bank1
(voltage reference control register) register. When MOVLW 0x1F ;Value used to initialize
selected as a comparator input, these pins will read ;data direction
as '0's. MOVWF TRISA ;Set RA<4:0> as inputs
;TRISA<5> always
;read as ‘1’.
Note: RA5 shares function with VPP. When VPP ;TRISA<7:6>
;depend on oscillator mode
voltage levels are applied to RA5, the
device will enter Programming mode.

PIC16F62X
FIGURE 5-1: BLOCK DIAGRAM OF FIGURE 5-2: BLOCK DIAGRAM OF
RA0/AN0:RA1/AN1 PINS RA2/VREF PIN
Data Data
Bus Bus
D Q D Q
VDD VDD
WR WR
PORTA PORTA
CK Q CK Q
Data Latch Data Latch
D Q D Q
I/O Pin RA2 Pin
WR WR
TRISA TRISA
CK Q CK Q
VSS
TRIS Latch VSS TRIS Latch Analog
Input Mode
Analog
Input Mode RD
TRISA Schmitt Trigger
RD Schmitt Trigger Input Buffer
TRISA Input Buffer
Q D
Q D
EN
EN
RD PORTA
RD PORTA
To Comparator
To Comparator VROE
VREF
FIGURE 5-3: BLOCK DIAGRAM OF THE RA3/AN3 PIN

Data Comparator Mode = 110
Bus VDD
D Q
Comparator Output
WR 1
PORTA
CK Q
Data Latch 0
D Q
RA3 Pin
WR
TRISA
CK Q
VSS
TRIS Latch
Analog
Input Mode
RD
TRISA Schmitt Trigger
Input Buffer
Q D
EN
RD PORTA
To Comparator

PIC16F62X
FIGURE 5-4: BLOCK DIAGRAM OF RA4/T0CKI PIN
Data Comparator Mode = 110
Bus
D Q
Comparator Output VDD
WR
PORTA 1
CK Q
0
Data Latch
D Q
RA4 Pin
WR N
TRISA
CK Q
TRIS Latch Vss Vss
Schmitt Trigger
Input Buffer
RD TRISA
Q D
EN
RD PORTA
TMR0 Clock Input
FIGURE 5-5: BLOCK DIAGRAM OF THE FIGURE 5-6: BLOCK DIAGRAM OF

RA5/MCLR/VPP PIN RA6/OSC2/CLKOUT PIN
From OSC1 OSC

Circuit VDD
CLKOUT(FOSC/4)
1
MCLRE
MCLR
circuit D Q 0
WR
MCLR Filter PORTA
CK Q
Program Schmitt Trigger (FOSC = VSS
(2) Data Latch
mode Input Buffer 101, 111)
HV Detect
RA5/MCLR/VPP
D Q
WR
Data TRISA
CK Q
Bus
VSS TRIS Latch
RD
TRISA Schmitt
Trigger
Input Buffer
FOSC =
RD (1)
100, 110
TRISA VSS
Q D
Q D
EN
EN RD PORTA
RD
PORTA Note 1: INTRC with RA6 = I/O or ER with RA6 = I/O.
2: INTRC with RA6 = CLKOUT or ER with RA6 = CLK-
OUT.

PIC16F62X
FIGURE 5-7: BLOCK DIAGRAM OF RA7/OSC1/CLKIN PIN
To OSC2 Oscillator
Circuit
CLKIN to core VDD
Data Bus
D Q
RA7/OSC1/CLKIN Pin
WR PORTA
CK Q
Data Latch
D VSS
Q
WR TRISA
CK Q
TRIS Latch
RD TRISA
FOSC = 100, 101(1)
Q D
Schmitt Trigger
Input Buffer
EN
RD PORTA
Note 1: INTRC with CLKOUT, and INTRC with I/O.

PIC16F62X
TABLE 5-1: PORTA FUNCTIONS
Functio Input Output
Name Description
n Type Type
RA2/AN2/VREF RA2 ST CMOS Bi-directional I/O port
VREF — AN VREF output
RA3/AN3/CMP1 RA3 ST CMOS Bi-directional I/O port
CMP1 — CMOS Comparator 1 output
RA4/T0CKI/CMP2 RA4 ST OD Bi-directional I/O port
T0CKI ST — External clock input for TMR0 or comparator output. Output
is open drain type
CMP2 — OD Comparator 2 output
RA5/MCLR/VPP RA5 ST — Input port
MCLR ST — Master clear
VPP HV — Programming voltage input. When configured as MCLR,
this pin is an active low RESET to the device. Voltage on
MCLR/VPP must not exceed VDD during normal device
operation
RA6/OSC2/CLKOUT RA6 ST CMOS Bi-directional I/O port.
OSC2 XTAL — Oscillator crystal output. Connects to crystal resonator in
Crystal Oscillator mode.
CLKOUT — CMOS In ER/INTRC mode, OSC2 pin can output CLKOUT, which
has 1/4 the frequency of OSC1
RA7/OSC1/CLKIN RA7 ST CMOS Bi-directional I/O port
OSC1 XTAL — Oscillator crystal input
CLKIN ST — External clock source input. ER biasing pin.
Legend: ST = Schmitt Trigger input HV = High Voltage OD = Open Drain AN = Analog

PIC16F62X
TABLE 5-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA(1)
Value on
Value on
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Other
POR
RESETS
05h PORTA RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 xxxx 0000 xxxu 0000
85h TRISA TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 1111 1111 1111 1111
1Fh CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 0000 0000 0000 0000
9Fh VRCON VREN VROE VRR — VR3 VR2 VR1 VR0 000- 0000 000- 0000
Legend: — = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown
Note 1: Shaded bits are not used by PORTA.
5.2 PORTB and TRISB Registers This interrupt on mismatch feature, together with
software configurable pull-ups on these four pins allow
PORTB is an 8-bit wide bi-directional port. The easy interface to a key pad and make it possible for
corresponding data direction register is TRISB. A '1' in wake-up on key-depression. (See AN552)
the TRISB register puts the corresponding output driver
in a Hi-impedance mode. A '0' in the TRISB register Note: If a change on the I/O pin should occur
puts the contents of the output latch on the selected when a read operation is being executed
pin(s). (start of the Q2 cycle), then the RBIF inter-
rupt flag may not get set.
PORTB is multiplexed with the external interrupt,
USART, CCP module and the TMR1 clock input/output. The interrupt-on-change feature is recommended for
The standard port functions and the alternate port wake-up on key depression operation and operations
functions are shown in Table 5-3. Alternate port where PORTB is only used for the interrupt-on-change
functions override TRIS setting when enabled. feature. Polling of PORTB is not recommended while
using the interrupt-on-change feature.
Reading PORTB register reads the status of the pins,
whereas writing to it will write to the port latch. All write
operations are read-modify-write operations. So a write
to a port implies that the port pins are first read, then
this value is modified and written to the port data latch.
Each of the PORTB pins has a weak internal pull-up
(≈200 µA typical). A single control bit can turn on all the
pull-ups. This is done by clearing the RBPU
(OPTION<7>) bit. The weak pull-up is automatically
turned off when the port pin is configured as an output.
The pull-ups are disabled on Power-on Reset.
Four of PORTB’s pins, RB<7:4>, have an interrupt-on-
change feature. Only pins configured as inputs can
cause this interrupt to occur (i.e., any RB<7:4> pin con-
figured as an output is excluded from the interrupt-on-
change comparison). The input pins (of RB7:RB4) are
compared with the old value latched on the last read of
PORTB. The “mismatch” outputs of RB7:RB4 are
OR’ed together to generate the RBIF interrupt (flag
latched in INTCON<0>).
This interrupt can wake the device from SLEEP. The
user, in the interrupt service routine, can clear the
interrupt in the following manner:
a) Any read or write of PORTB. This will end the
mismatch condition.
b) Clear flag bit RBIF.
A mismatch condition will continue to set flag bit RBIF.
Reading PORTB will end the mismatch condition and
allow flag bit RBIF to be cleared.

PIC16F62X
RB0/INT PIN RB1/RX/DT PIN
VDD VDD
RBPU RBPU Weak
P Weak Pull-up
PORT/PERIPHERAL Select(1) P Pull-up
VDD
VDD
USART Data Output

0
Data Bus D
Data Bus Q 1 RB1/
D Q
RX/DT
RB0/INT WR PORTB
WR PORTB CK Q
CK Q
Data Latch VSS
Data Latch VSS
D Q
D Q WR TRISB
CK Q
WR TRISB
CK Q TRIS Latch
Peripheral OE(2)
TRIS Latch
TTL
RD TRISB Input
TTL Buffer
RD TRISB
Input Q D
Buffer
Q D EN
RD PORTB
EN
EN
USART Receive Input

RD PORTB Schmitt
Trigger
INT Note 1: Port/Peripheral select signal selects between port
Schmitt data and peripheral output.
Trigger 2: Peripheral OE (output enable) is only active if
peripheral select is active.

PIC16F62X
RB2/TX/CK PIN RB3/CCP1 PIN
VDD VDD
RBPU Weak RBPU Weak
PORT/PERIPHERAL Select(1) P Pull-up PORT/PERIPHERAL Select(1) P Pull-up
VDD VDD
USART TX/CK Output USART TX/CK output

0 0
Data Bus D RB2/ Data Bus D RB3/

Q 1 Q 1
TX/CK CCP1
WR PORTB WR PORTB
CK Q CK Q
Data Latch VSS Data Latch VSS
D Q D Q
WR TRISB WR TRISB
CK Q CK Q
TRIS Latch TRIS Latch

Peripheral OE(2) Peripheral OE(2)
TTL TTL
RD TRISB Input RD TRISB Input
Buffer Buffer
Q D Q D
EN EN
RD PORTB RD PORTB
USART Slave Clock In USART Slave Clock In

Schmitt Schmitt
Trigger Trigger
Note 1: Port/Peripheral select signal selects between port Note 1: Port/Peripheral select signal selects between port
data and peripheral output. data and peripheral output.
2: Peripheral OE (output enable) is only active if 2: Peripheral OE (output enable) is only active if
peripheral select is active. peripheral select is active.

PIC16F62X
FIGURE 5-12: BLOCK DIAGRAM OF RB4/PGM PIN
VDD
RBPU
P weak pull-up
Data Bus
D Q VDD
WR PORTB
CK Q
Data Latch
RB4/PGM
D Q
WR TRISB
CK Q
VSS
TRIS Latch
RD TRISB
LVP
RD PORTB
PGM input
TTL
Schmitt
input
Trigger
buffer
Q D
EN Q1
Set RBIF
From other Q D
RB<7:4> pins
Q3
EN
Note 1: The low voltage programming disables the interrupt-on-change and the weak pull-ups on RB4.

PIC16F62X
FIGURE 5-13: BLOCK DIAGRAM OF RB5 PIN
VDD
RBPU
weak VDD
P pull-up
Data Bus
D Q
RB5 pin
WR PORTB
CK Q
Data Latch
VSS
D Q
WR TRISB
CK Q
TRIS Latch
TTL
input
buffer
RD TRISB
Q D
RD PORTB
EN Q1
Set RBIF
From other Q D
RB<7:4> pins
Q3
EN

PIC16F62X
FIGURE 5-14: BLOCK DIAGRAM OF RB6/T1OSO/T1CKI PIN
VDD
RBPU
P weak pull-up
Data Bus
D Q
VDD
WR PORTB
CK Q
Data Latch
RB6/
D Q T1OSO/
T1CKI
WR TRISB pin
CK Q
VSS
TRIS Latch
RD TRISB
T1OSCEN
TTL
input
buffer
RD PORTB
TMR1 Clock
Schmitt
From RB7 Trigger
Serial programming clock TMR1 oscillator
Q D
EN
Set RBIF
From other Q D
RB<7:4> pins
Q3
EN

PIC16F62X
FIGURE 5-15: BLOCK DIAGRAM OF THE RB7/T1OSI PIN
VDD
RBPU
P weak pull-up
To RB6 TMR1 oscillator
VDD
Data Bus
D Q
WR PORTB RB7/T1OSI
CK Q
pin
Data Latch
D Q VSS
WR TRISB
CK Q
TRIS Latch
RD TRISB
T10SCEN
TTL
RD PORTB input
buffer
Serial programming input
Schmitt
Trigger
Q D
EN
Set RBIF
From other Q D
RB<7:4> pins
EN

PIC16F62X
TABLE 5-3: PORTB FUNCTIONS
Output
Name Function Input Type Description
Type
RB0/INT RB0 TTL CMOS Bi-directional I/O port. Can be software programmed for
INT ST — External interrupt.
RB1/RX/DT RB1 TTL CMOS Bi-directional I/O port. Can be software programmed for
RX ST — USART Receive Pin
DT ST CMOS Synchronous data I/O
RB2/TX/CK RB2 TTL CMOS Bi-directional I/O port
TX — CMOS USART Transmit Pin
CK ST CMOS Synchronous Clock I/O. Can be software programmed
for internal weak pull-up.
RB3/CCP1 RB3 TTL CMOS Bi-directional I/O port. Can be software programmed for
CCP1 ST CMOS Capture/Compare/PWM/I/O
RB4/PGM RB4 TTL CMOS Bi-directional I/O port. Can be software programmed for
PGM ST — Low voltage programming input pin. Interrupt-on-pin
change. When low voltage programming is enabled, the
interrupt-on-pin change and weak pull-up resistor are
disabled.
RB5 RB5 TTL CMOS Bi-directional I/O port. Interrupt-on-pin change. Can be
software programmed for internal weak pull-up.
RB6/T1OSO/T1CKI/ RB6 TTL CMOS Bi-directional I/O port. Interrupt-on-pin change. Can be
PGC software programmed for internal weak pull-up.
T1OSO — XTAL Timer1 Oscillator Output
T1CKI ST — Timer1 Clock Input
PGC ST — ICSP Programming Clock
RB7/T1OSI/PGD RB7 TTL CMOS Bi-directional I/O port. Interrupt-on-pin change. Can be
software programmed for internal weak pull-up.
T1OSI XTAL — Timer1 Oscillator Input
PGD ST CMOS ICSP Data I/O
TABLE 5-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB(1)

Value on
Value on
POR
RESETS
06h, 106h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx uuuu uuuu
86h, 186h TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 1111 1111
81h, 181h OPTION RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
Legend: u = unchanged, x = unknown
Note 1: Shaded bits are not used by PORTB.

PIC16F62X
5.3 I/O Programming Considerations EXAMPLE 5-2: READ-MODIFY-WRITE
INSTRUCTIONS ON AN
5.3.1 BI-DIRECTIONAL I/O PORTS I/O PORT
Any instruction which writes, operates internally as a ;Initial PORT settings:PORTB<7:4> Inputs
read followed by a write operation. The BCF and BSF ;
instructions, for example, read the register into the ; PORTB<3:0> Outputs
CPU, execute the bit operation and write the result ;PORTB<7:6> have external pull-up and are not
back to the register. Caution must be used when these ;connected to other circuitry
instructions are applied to a port with both inputs and ;
; PORT latchPORT Pins
outputs defined. For example, a BSF operation on Bit 5
---------- ----------
of PORTB will cause all eight bits of PORTB to be read BCF STATUS, RP0 ;
into the CPU. Then the BSF operation takes place on BCF PORTB, 7 ;01pp pppp 11pp pppp
Bit 5 and PORTB is written to the output latches. If BSF STATUS, RP0 ;
another bit of PORTB is used as a bi-directional I/O pin BCF TRISB, 7 ;10pp pppp 11pp pppp
(e.g., Bit 0) and it is defined as an input at this time, the BCF TRISB, 6 ;10pp pppp 10pp pppp
input signal present on the pin itself would be read into ;
the CPU and rewritten to the data latch of this particular ;Note that the user may have expected the pin
pin, overwriting the previous content. As long as the pin ;values to be 00pp pppp. The 2nd BCF caused
stays in the Input mode, no problem occurs. However, ;RB7 to be latched as the pin value (High).
if Bit 0 is switched into Output mode later on, the
5.3.2 SUCCESSIVE OPERATIONS ON I/O
content of the data latch may now be unknown.
PORTS
Reading a port register, reads the values of the port
pins. Writing to the port register writes the value to the The actual write to an I/O port happens at the end of an
port latch. When using read-modify-write instructions instruction cycle, whereas for reading, the data must be
(ex. BCF, BSF, etc.) on a port, the value of the port pins valid at the beginning of the instruction cycle (Figure 5-
is read, the desired operation is done to this value, and 16). Therefore, care must be exercised if a write
this value is then written to the port latch. followed by a read operation is carried out on the same
I/O port. The sequence of instructions should be such
Example 5-2 shows the effect of two sequential read-
to allow the pin voltage to stabilize (load dependent)
modify-write instructions (ex., BCF, BSF, etc.) on an
before the next instruction which causes that file to be
I/O port.
read into the CPU is executed. Otherwise, the previous
A pin actively outputting a Low or High should not be state of that pin may be read into the CPU rather than
driven from external devices at the same time in order the new state. When in doubt, it is better to separate
to change the level on this pin (“wired-or”, “wired-and”). these instructions with a NOP or another instruction not
The resulting high output currents may damage accessing this I/O port.
the chip.
FIGURE 5-16: SUCCESSIVE I/O OPERATION
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC PC PC + 1 PC + 2 PC + 3
Instruction MOWF PORTB MOWF PORTB, W NOP NOP
fetched Write to PORTB Read to PORTB
Port pin
sampled here
TPD
Execute Execute Execute
MOVWF MOVWF NOP
PORTB PORTB
Note 1: This example shows write to PORTB followed by a read from PORTB.
2: Data setup time = (0.25 TCY - TPD) where TCY = instruction cycle and TPD = propagation delay of Q1 cycle to output valid.
Therefore, at higher clock frequencies, a write followed by a read may be problematic.

PIC16F62X
6.0 TIMER0 MODULE 6.2 Using Timer0 with External Clock
The Timer0 module timer/counter has the following When an external clock input is used for Timer0, it must
features: meet certain requirements. The external clock
requirement is due to internal phase clock (TOSC)
• 8-bit timer/counter
synchronization. Also, there is a delay in the actual
• Readable and writable incrementing of Timer0 after synchronization.
• 8-bit software programmable prescaler
• Internal or external clock select 6.2.1 EXTERNAL CLOCK
• Interrupt on overflow from FFh to 00h SYNCHRONIZATION
• Edge select for external clock When no prescaler is used, the external clock input is
Figure 6-1 is a simplified block diagram of the Timer0 the same as the prescaler output. The synchronization
module. Additional information available in the of T0CKI with the internal phase clocks is
PICmicro™ Mid-Range MCU Family Reference accomplished by sampling the prescaler output on the
Manual, DS31010A. Q2 and Q4 cycles of the internal phase clocks
(Figure 6-1). Therefore, it is necessary for T0CKI to be
Timer mode is selected by clearing the T0CS bit
high for at least 2TOSC (and a small RC delay of 20 ns)
(OPTION<5>). In Timer mode, the TMR0 will increment
and low for at least 2TOSC (and a small RC delay of
every instruction cycle (without prescaler). If Timer0 is
20 ns). Refer to the electrical specification of the
written, the increment is inhibited for the following two
desired device.
cycles. The user can work around this by writing an
adjusted value to TMR0. When a prescaler is used, the external clock input is
divided by the asynchronous ripple-counter type
Counter mode is selected by setting the T0CS bit. In
prescaler so that the prescaler output is symmetrical.
this mode Timer0 will increment either on every rising
For the external clock to meet the sampling
or falling edge of pin RA4/T0CKI. The incrementing
requirement, the ripple-counter must be taken into
edge is determined by the source edge (T0SE) control
account. Therefore, it is necessary for T0CKI to have a
bit (OPTION<4>). Clearing the T0SE bit selects the
period of at least 4TOSC (and a small RC delay of 40 ns)
rising edge. Restrictions on the external clock input are
divided by the prescaler value. The only requirement
discussed in detail in Section 6.2.
on T0CKI high and low time is that they do not violate
The prescaler is shared between the Timer0 module the minimum pulse width requirement of 10 ns. Refer to
and the Watchdog Timer. The prescaler assignment is parameters 40, 41 and 42 in the electrical specification
controlled in software by the control bit PSA of the desired device. See Table 17-7.
(OPTION<3>). Clearing the PSA bit will assign the
prescaler to Timer0. The prescaler is not readable or
writable. When the prescaler is assigned to the Timer0
module, prescale value of 1:2, 1:4,..., 1:256 are
selectable. Section 6.3 details the operation of the
prescaler.
6.1 TIMER0 Interrupt

Timer0 interrupt is generated when the TMR0 register
timer/counter overflows from FFh to 00h. This overflow
sets the T0IF bit. The interrupt can be masked by
clearing the T0IE bit (INTCON<5>). The T0IF bit
(INTCON<2>) must be cleared in software by the
Timer0 module interrupt service routine before re-
enabling this interrupt. The Timer0 interrupt cannot
wake the processor from SLEEP since the timer is shut
off during SLEEP.

PIC16F62X
6.3 Timer0 Prescaler The PSA and PS2:PS0 bits (OPTION<3:0>) determine
the prescaler assignment and prescale ratio.
An 8-bit counter is available as a prescaler for the
Timer0 module, or as a postscaler for the Watchdog When assigned to the Timer0 module, all instructions
Timer. A prescaler assignment for the Timer0 module writing to the TMR0 register (e.g., CLRF 1,
means that there is no postscaler for the Watchdog MOVWF 1, BSF 1, x....etc.) will clear the pres-
Timer, and vice-versa. caler. When assigned to WDT, a CLRWDT instruction
will clear the prescaler along with the Watchdog Timer.
The prescaler is not readable or writable.
FIGURE 6-1: BLOCK DIAGRAM OF THE TIMER0/WDT
FOSC/4 Data Bus
0 8
1
T0CKI SYNC
Pin 1 2 TMR0 reg
Cycles
0
T0SE
T0CS
Set Flag Bit T0IF
PSA on Overflow
WDT Postscaler/
0 TMR0 Prescaler
Watchdog 1 8
Timer
PSA 8-to-1MUX PS0 - PS2
WDT Enable bit

0 1
PSA
WDT
Timeout
Note 1: T0SE, T0CS, PSA, .PS0-PS2 are bits in the Option Register.

PIC16F62X
6.3.1 SWITCHING PRESCALER To change prescaler from the WDT to the TMR0
ASSIGNMENT module use the sequence shown in Example 6-2. This
precaution must be taken even if the WDT is disabled.
The prescaler assignment is fully under software
control (i.e., it can be changed “on the fly” during
EXAMPLE 6-2: CHANGING PRESCALER
program execution). Use the instruction sequences,
(WDT→TIMER0)
shown in Example 6-1, when changing the prescaler
assignment from Timer0 to WDT, to avoid an
unintended device RESET. CLRWDT ;Clear WDT and
;prescaler
BSF STATUS, RP0
EXAMPLE 6-1: CHANGING PRESCALER
MOVLW b'xxxx0xxx' ;Select TMR0, new
(TIMER0→WDT) ;prescale value and
BCF STATUS, RP0 ;Skip if already in ;clock source
;Bank 0 MOVWF OPTION_REG
CLRWDT ;Clear WDT BCF STATUS, RP0
CLRF TMR0 ;Clear TMR0 & Prescaler
BSF STATUS, RP0 ;Bank 1
MOVLW '00101111’b ;These 3 lines
;(5, 6, 7)
MOVWF OPTION_REG ;are required only
;if desired PS<2:0>
;are
CLRWDT ;000 or 001
MOVLW '00101xxx’b ;Set Postscaler to
MOVWF OPTION_REG ;desired WDT rate
BCF STATUS, RP0 ;Return to Bank 0
TABLE 6-1: REGISTERS ASSOCIATED WITH TIMER0

Value on
Value on
POR
RESETS
01h TMR0 Timer0 module register xxxx xxxx uuuu uuuu
0Bh/8Bh/
INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
10Bh/18Bh
81h, 181h OPTION(2) RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
Legend: — = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown
Note 1: Shaded bits are not used by TMR0 module.
2: Option is referred by OPTION_REG in MPLAB.

PIC16F62X
7.0 TIMER1 MODULE The Operating mode is determined by the clock select
bit, TMR1CS (T1CON<1>).
The Timer1 module is a 16-bit timer/counter consisting
In Timer mode, Timer1 increments every instruction
of two 8-bit registers (TMR1H and TMR1L) which are
cycle. In Counter mode, it increments on every rising
readable and writable. The TMR1 Register pair
edge of the external clock input.
(TMR1H:TMR1L) increments from 0000h to FFFFh
and rolls over to 0000h. The TMR1 Interrupt, if enabled, Timer1 can be enabled/disabled by setting/clearing
is generated on overflow which is latched in interrupt control bit TMR1ON (T1CON<0>).
flag bit TMR1IF (PIR1<0>). This interrupt can be Timer1 also has an internal “RESET input”. This
enabled/disabled by setting/clearing TMR1 interrupt RESET can be generated by the CCP module
enable bit TMR1IE (PIE1<0>). (Section 11.0). Register 7-1 shows the Timer1 Control
Timer1 can operate in one of two modes: register.
• As a timer For the PIC16F627 and PIC16F628, when the Timer1
• As a counter oscillator is enabled (T1OSCEN is set), the RB7/T1OSI
and RB6/T1OSO/T1CKI pins become inputs. That is,
the TRISB<7:6> value is ignored.
REGISTER 7-1: T1CON: TIMER1 CONTROL REGISTER (ADDRESS: 10h)

U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
bit 7 bit 0

bit 5-4 T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits
11 = 1:8 Prescale value
bit 3 T1OSCEN: Timer1 Oscillator Enable Control bit
1 = Oscillator is enabled
0 = Oscillator is shut off(1)
bit 2 T1SYNC: Timer1 External Clock Input Synchronization Control bit
TMR1CS = 1
1 = Do not synchronize external clock input
0 = Synchronize external clock input
TMR1CS = 0
This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0.
bit 1 TMR1CS: Timer1 Clock Source Select bit
1 = External clock from pin RB6/T1OSO/T1CKI (on the rising edge)
0 = Internal clock (FOSC/4)
bit 0 TMR1ON: Timer1 On bit
1 = Disables Timer1
0 = Stops Timer1
Note 1: The oscillator inverter and feedback resistor are turned off to eliminate power drain.
Legend:

PIC16F62X
7.1 Timer1 Operation in Timer Mode 7.2.1 EXTERNAL CLOCK INPUT TIMING
FOR SYNCHRONIZED COUNTER
Timer mode is selected by clearing the TMR1CS
MODE
(T1CON<1>) bit. In this mode, the input clock to the
timer is FOSC/4. The synchronize control bit T1SYNC When an external clock input is used for Timer1 in
(T1CON<2>) has no effect since the internal clock is Synchronized Counter mode, it must meet certain
always in sync. requirements. The external clock requirement is due to
internal phase clock (Tosc) synchronization. Also, there
7.2 Timer1 Operation in Synchronized is a delay in the actual incrementing of TMR1 after
Counter Mode synchronization.
Counter mode is selected by setting bit TMR1CS. In When the prescaler is 1:1, the external clock input is
this mode the timer increments on every rising edge of the same as the prescaler output. The synchronization
clock input on pin RB7/T1OSI when bit T1OSCEN is of T1CKI with the internal phase clocks is accom-
set or pin RB6/T1OSO/T1CKI when bit T1OSCEN is plished by sampling the prescaler output on the Q2 and
cleared. Q4 cycles of the internal phase clocks. Therefore, it is
necessary for T1CKI to be high for at least 2Tosc (and
If T1SYNC is cleared, then the external clock input is a small RC delay of 20 ns) and low for at least 2Tosc
synchronized with internal phase clocks. The synchro- (and a small RC delay of 20 ns). Refer to the appropri-
nization is done after the prescaler stage. The ate electrical specifications, parameters 45, 46, and 47.
prescaler stage is an asynchronous ripple-counter.
When a prescaler other than 1:1 is used, the external
In this configuration, during SLEEP mode, Timer1 will clock input is divided by the asynchronous ripple-
not increment even if the external clock is present, counter type prescaler so that the prescaler output is
since the synchronization circuit is shut off. The symmetrical. In order for the external clock to meet the
prescaler however will continue to increment. sampling requirement, the ripple-counter must be
taken into account. Therefore, it is necessary for T1CKI
to have a period of at least 4Tosc (and a small RC delay
of 40 ns) divided by the prescaler value. The only
requirement on T1CKI high and low time is that they do
not violate the minimum pulse width requirements of 10
ns). Refer to the appropriate electrical specifications,
parameters 40, 42, 45, 46, and 47.
FIGURE 7-1: TIMER1 BLOCK DIAGRAM

Set flag bit
TMR1IF on
Overflow Synchronized
TMR1 0
Clock Input
TMR1H TMR1L
1
TMR1ON
T1SYNC
T1OSC
RB6/T1OSO/T1CKI 1
Synchronize
Prescaler
T1OSCEN FOSC/4 1, 2, 4, 8 det
Enable Internal 0
RB7/T1OSI Oscillator(1) Clock 2
SLEEP Input
T1CKPS1:T1CKPS0
TMR1CS
Note 1: When the T1OSCEN bit is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.

PIC16F62X
7.3 Timer1 Operation in EXAMPLE 7-1: READING A 16-BIT FREE-
Asynchronous Counter Mode RUNNING TIMER
If control bit T1SYNC (T1CON<2>) is set, the external
clock input is not synchronized. The timer continues to ; All interrupts are disabled
MOVF TMR1H, W ;Read high byte
increment asynchronous to the internal phase clocks.
MOVWF TMPH ;
The timer will continue to run during SLEEP and can MOVF TMR1L, W ;Read low byte
generate an interrupt on overflow which will wake-up MOVWF TMPL ;
the processor. However, special precautions in soft- MOVF TMR1H, W ;Read high byte
ware are needed to read/write the timer (Section 7.3.2). SUBWF TMPH, W ;Sub 1st read
In Asynchronous Counter mode, Timer1 can not be ; with 2nd read
BTFSC STATUS,Z ;Is result = 0
used as a time-base for capture or compare
GOTO CONTINUE ;Good 16-bit read
operations. ;
; TMR1L may have rolled over between the read
7.3.1 EXTERNAL CLOCK INPUT TIMING ; of the high and low bytes. Reading the high
WITH UNSYNCHRONIZED CLOCK ; and low bytes now will read a good value.
;
If control bit T1SYNC is set, the timer will increment MOVF TMR1H, W ;Read high byte
completely asynchronously. The input clock must meet MOVWF TMPH ;
certain minimum high-time and low-time requirements. MOVF TMR1L, W ;Read low byte
Refer to the appropriate Electrical Specifications MOVWF TMPL ;
section, Timing Parameters 45, 46, and 47. ; Re-enable the Interrupts (if required)
CONTINUE ;Continue with your code
7.3.2 READING AND WRITING TIMER1 IN
ASYNCHRONOUS COUNTER
MODE
Reading TMR1H or TMR1L while the timer is running,
from an external asynchronous clock, will ensure a
valid read (taken care of in hardware). However, the
user should keep in mind that reading the 16-bit timer
in two 8-bit values itself poses certain problems since
the timer may overflow between the reads.
For writes, it is recommended that the user simply stop
the timer and write the desired values. A write
contention may occur by writing to the timer registers
while the register is incrementing. This may produce an
unpredictable value in the timer register.
Reading the 16-bit value requires some care.
Example 7-1 is an example routine to read the 16-bit
timer value. This is useful if the timer cannot be
stopped.

PIC16F62X
7.4 Timer1 Oscillator 7.5 Resetting Timer1 Using a CCP
A crystal oscillator circuit is built in between pins T1OSI
Trigger Output
(input) and T1OSO (amplifier output). It is enabled by If the CCP1 module is configured in Compare mode to
setting control bit T1OSCEN (T1CON<3>). The oscilla- generate a “special event trigger” (CCP1M3:CCP1M0
tor is a low power oscillator rated up to 200 kHz. It will = 1011), this signal will reset Timer1.
continue to run during SLEEP. It is primarily intended
for a 32 kHz crystal. Table 7-1 shows the capacitor Note: The special event triggers from the CCP1
selection for the Timer1 oscillator. module will not set interrupt flag bit
TMR1IF (PIR1<0>).
The Timer1 oscillator is identical to the LP oscillator.
The user must provide a software time delay to ensure Timer1 must be configured for either Timer or Synchro-
proper oscillator start-up. nized Counter mode to take advantage of this feature.
If Timer1 is running in Asynchronous Counter mode,
this RESET operation may not work.
TABLE 7-1: CAPACITOR SELECTION FOR
THE TIMER1 OSCILLATOR In the event that a write to Timer1 coincides with a
special event trigger from CCP1, the write will take
Osc Type Freq C1 C2 precedence.
LP 32 kHz 33 pF 33 pF In this mode of operation, the CCPRxH:CCPRxL
100 kHz 15 pF 15 pF registers pair effectively becomes the period register
for Timer1.
200 kHz 15 pF 15 pF
Note 1: These values are for design guidance only. 7.6 Resetting of Timer1 Register Pair
Consult AN826 (DS00826A) for further
(TMR1H, TMR1L)
information on Crystal/Capacitor Selection.
TMR1H and TMR1L registers are not reset to 00h on a
POR or any other RESET except by the CCP1 special
event triggers.
T1CON register is reset to 00h on a Power-on Reset or
a Brown-out Reset, which shuts off the timer and
leaves a 1:1 prescale. In all other RESETS, the register
is unaffected.
7.7 Timer1 Prescaler

The prescaler counter is cleared on writes to the
TMR1H or TMR1L registers.
TABLE 7-2: REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER

Value on
Value on
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 all other
POR
RESETS
0Bh/8Bh/ INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
10Bh/18Bh
0Ch PIR1 EEIF CMIF RCIF TXIF — CCP1IF TMR2IF TMR1IF 0000 -000 0000 -000
8Ch PIE1 EEIE CMIE RCIE TXIE — CCP1IE TMR2IE TMR1IE 0000 -000 0000 -000
0Eh TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu
0Fh TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu
10h T1CON — — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the Timer1 module.

PIC16F62X
8.0 TIMER2 MODULE 8.1 Timer2 Prescaler and Postscaler
Timer2 is an 8-bit timer with a prescaler and a The prescaler and postscaler counters are cleared
postscaler. It can be used as the PWM time-base for when any of the following occurs:
PWM mode of the CCP module. The TMR2 register is • A write to the TMR2 register
readable and writable, and is cleared on any device
• A write to the T2CON register
RESET.
• Any device RESET (Power-on Reset, MCLR
The input clock (FOSC/4) has a prescale option of 1:1, Reset, Watchdog Timer Reset, or Brown-out
1:4 or 1:16, selected by control bits Reset)
T2CKPS1:T2CKPS0 (T2CON<1:0>).
TMR2 is not cleared when T2CON is written.
The Timer2 module has an 8-bit Period Register PR2.
Timer2 increments from 00h until it matches PR2 and 8.2 Output of TMR2
then resets to 00h on the next increment cycle. PR2 is
a readable and writable register. The PR2 register is The output of TMR2 (before the postscaler) is fed to the
initialized to FFh upon RESET. Synchronous Serial Port module which optionally uses
it to generate shift clock.
The match output of TMR2 goes through a 4-bit
postscaler (which gives a 1:1 to 1:16 scaling inclusive)
to generate a TMR2 interrupt (latched in flag bit FIGURE 8-1: TIMER2 BLOCK DIAGRAM
TMR2IF, (PIR1<1>)). Sets flag
TMR2
bit TMR2IF output (1)
Timer2 can be shut off by clearing control bit TMR2ON
(T2CON<2>) to minimize power consumption.
RESET Prescaler
Register 8-1 shows the Timer2 Control register. TMR2 reg
1:1, 1:4, 1:16
FOSC/4
Postscaler 2
Comparator
1:1 to 1:16 EQ
T2CKPS<1:0>
4 PR2 reg
TOUTPS<3:0>
Note 1: TMR2 register output can be software selected by the

SSP Module as a baud clock.

PIC16F62X
REGISTER 8-1: T2CON: TIMER CONTROL REGISTER (ADDRESS: 12h)
U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0
bit 7 bit 0

bit 6-3 TOUTPS3:TOUTPS0: Timer2 Output Postscale Select bits
0000 = 1:1 Postscale Value
0001 = 1:2 Postscale Value
•
•
•
1111 = 1:16 Postscale
bit 2 TMR2ON: Timer2 On bit

1 = Timer2 is on
0 = Timer2 is off
bit 1-0 T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits
00 = 1:1 Prescaler Value
01 = 1:4 Prescaler Value
1x = 1:16 Prescaler Value
Legend:
TABLE 8-1: REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER

Value on
Value on
POR
RESETS
10Bh/18Bh
11h TMR2 Timer2 module’s register 0000 0000 0000 0000
12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
92h PR2 Timer2 Period Register 1111 1111 1111 1111
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the Timer2 module.

PIC16F62X
NOTES:

PIC16F62X
9.0 COMPARATOR MODULE The CMCON register, shown in Register 9-1, controls
the comparator input and output multiplexers. A block
The Comparator module contains two analog diagram of the comparator is shown in Figure 9-1.
comparators. The inputs to the comparators are
multiplexed with the RA0 through RA3 pins. The On-
chip Voltage Reference (Section 10.0) can also be an
input to the comparators.
REGISTER 9-1: CMCON REGISTER (ADDRESS: 01Fh)

R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0
bit 7 bit 0
bit 7 C2OUT: Comparator 2 Output

When C2INV = 0:
1 = C2 VIN+ > C2 VIN-
0 = C2 VIN+ < C2 VIN-
When C2INV = 1:
1 = C2 VIN+ < C2 VIN-
0 = C2 VIN+ > C2 VIN-
bit 6 C1OUT: Comparator 1 Output
When C1INV = 0:
1 = C1 VIN+ > C1 VIN-
0 = C1 VIN+ < C1 VIN-
When C1INV = 1:
1 = C1 VIN+ < C1 VIN-
0 = C1 VIN+ > C1 VIN-
bit 5 C2INV: Comparator 2 Output Inversion
1 = C2 Output inverted
0 = C2 Output not inverted
bit 4 C1INV: Comparator 1 Output Inversion
1 = C1 Output inverted
0 = C1 Output not inverted
bit 3 CIS: Comparator Input Switch
When CM2:CM0: = 001
Then:
1 = C1 VIN- connects to RA3
When CM2:CM0 = 010

Then:
C2 VIN- connects to RA2
C2 VIN- connects to RA1
bit 2-0 CM2:CM0: Comparator Mode
Figure 9-1 shows the Comparator modes and CM2:CM0 bit settings
Legend:

PIC16F62X
9.1 Comparator Configuration mode is changed, the comparator output level may not
be valid for the specified mode change delay shown
There are eight modes of operation for the in Table 17-1.
comparators. The CMCON register is used to select
the mode. Figure 9-1 shows the eight possible modes. Note: Comparator interrupts should be disabled
The TRISA register controls the data direction of the during a Comparator mode change other-
comparator pins for each mode. If the Comparator wise a false interrupt may occur.
FIGURE 9-1: COMPARATOR I/O OPERATING MODES

Comparators Reset (POR Default Value) Comparators Off
CM2:CM0 = 000 CM2:CM0 = 111
RA0/AN0 D VIN-
RA0/AN0 A VIN-
D VIN+ C1 Off (Read as '0')
C1 Off (Read as '0') RA3/AN3/CMP1
RA3/AN3/CMP1 A VIN+
D VIN-
RA1/AN1 A VIN- RA1/AN1
Off (Read as '0') D VIN+ C2 Off (Read as '0')
RA2/AN2 A VIN+ C2 RA2/AN2
VSS
Four Inputs Multiplexed to Two Comparators
Two Independent Comparators CM2:CM0 = 010
CM2:CM0 = 100
RA0/AN0 A
A VIN- CIS = 0 VIN-
RA0/AN0
C1 C1VOUT RA3/AN3/CMP1 A CIS = 1
C1 C1VOUT
A VIN+ VIN+
RA3/AN3/CMP1
RA1/AN1 A
CIS = 0 VIN-
RA1/AN1 A VIN- RA2/AN2 A CIS = 1 C2VOUT
VIN+ C2
C2 C2VOUT
RA2/AN2 A VIN+
From VREF
Module
Two Common Reference Comparators Two Common Reference Comparators with Outputs
CM2:CM0 = 011 CM2:CM0 = 110
A VIN-
A VIN- RA0/AN0
RA0/AN0 C1VOUT
D VIN+ C1
D VIN+ C1 C1VOUT RA3/AN3/CMP1
RA3/AN3/CMP1
RA1/AN1 A VIN-
RA1/AN1 A VIN-
C2VOUT A VIN+ C2 C2VOUT
RA2/AN2 A VIN+ C2 RA2/AN2/CMP2
RA4/T0CKI/C20 Open Drain
One Independent Comparator Three Inputs Multiplexed to Two Comparators

CM2:CM0 = 101 CM2:CM0 = 001
This mode is disfunctional and has been corrected in the ‘A’
RA0/AN0 D VIN- Revision Devices.
A
VIN+ C1 Off (Read as '0') RA0/AN0
RA3/AN3/CMP1 D CIS = 0 VIN-
RA3/AN3/CMP1 A CIS = 1
VIN+ C1 C1VOUT
VSS +
RA1/AN1 A VIN-
C2VOUT RA1/AN1 A VIN-
A VIN+ C2
RA2/AN2 C2VOUT
A VIN+ C2
RA2/AN2 +
A = Analog Input, port reads zeros always.

D = Digital Input.
CIS (CMCON<3>) is the Comparator Input Switch.

PIC16F62X
The code example in Example 9-1 depicts the steps FIGURE 9-2: SINGLE COMPARATOR
required to configure the Comparator module. RA3 and
RA4 are configured as digital output. RA0 and RA1 are ViN+ +
configured as the V- inputs and RA2 as the V+ input to Result
both comparators. VIN- –
EXAMPLE 9-1: INITIALIZING

COMPARATOR MODULE
FLAG_REG EQU 0X20
CLRF FLAG_REG ;Init flag register
VIN-
CLRF PORTA ;Init PORTA
MOVF CMCON, W ;Load comparator bits
ANDLW 0xC0 ;Mask comparator bits
VIN+
IORWF FLAG_REG,F ;Store bits in flag register
MOVLW 0x03 ;Init comparator mode
MOVWF CMCON ;CM<2:0> = 011
BSF STATUS,RP0 ;Select Bank1
MOVLW 0x07 ;Initialize data direction Result
MOVWF TRISA ;Set RA<2:0> as inputs
;RA<4:3> as outputs
;TRISA<7:5> always read ‘0’ 9.3.1 EXTERNAL REFERENCE SIGNAL
BCF STATUS,RP0 ;Select Bank 0
CALL DELAY10 ;10µs delay When external voltage references are used, the
MOVF CMCON,F ;Read CMCON to end change condition comparator module can be configured to have the
BCF PIR1,CMIF ;Clear pending interrupts
BSF STATUS,RP0 ;Select Bank 1
comparators operate from the same or different
BSF PIE1,CMIE ;Enable comparator interrupts reference sources. However, threshold detector
BCF STATUS,RP0 ;Select Bank 0 applications may require the same reference. The
BSF INTCON,PEIE ;Enable peripheral interrupts reference signal must be between VSS and VDD, and
BSF INTCON,GIE ;Global interrupt enable
can be applied to either pin of the comparator(s).
9.2 Comparator Operation 9.3.2 INTERNAL REFERENCE SIGNAL
A single comparator is shown in Figure 9-2 along with The Comparator module also allows the selection of an
the relationship between the analog input levels and internally generated voltage reference for the
the digital output. When the analog input at VIN+ is less comparators. Section 10.0, Voltage Reference Manual,
than the analog input VIN-, the output of the comparator contains a detailed description of the Voltage Refer-
is a digital low level. When the analog input at VIN+ is ence module that provides this signal. The internal
greater than the analog input VIN-, the output of the reference signal is used when the comparators are in
comparator is a digital high level. The shaded areas of mode CM<2:0>=010 (Figure 9-1). In this mode, the
the output of the comparator in Figure 9-2 represent internal voltage reference is applied to the VIN+ pin of
the uncertainty due to input offsets and response time. both comparators.
9.3 Comparator Reference 9.4 Comparator Response Time

An external or internal reference signal may be used Response time is the minimum time, after selecting a
depending on the Comparator Operating mode. The new reference voltage or input source, before the
analog signal that is present at VIN- is compared to the comparator output is ensured to have a valid level. If
signal at VIN+, and the digital output of the comparator the internal reference is changed, the maximum delay
is adjusted accordingly (Figure 9-2). of the internal voltage reference must be considered
when using the comparator outputs. Otherwise the
maximum delay of the comparators should be used
(Table 17-1).

PIC16F62X
9.5 Comparator Outputs
The comparator outputs are read through the CMCON
register. These bits are read only. The comparator
outputs may also be directly output to the RA3 and RA4
I/O pins. When the CM<2:0> = 110, multiplexors in the
output path of the RA3 and RA4/T0CK1 pins will switch
and the output of each pin will be the unsynchronized
output of the comparator. The uncertainty of each of the
comparators is related to the input offset voltage and
the response time given in the specifications. Figure 9-
3 shows the comparator output block diagram.
The TRISA bits will still function as an output enable/
disable for the RA3 and RA4/T0CK1 pins while in this
mode.
Note 1: When reading the PORT register, all pins
configured as analog inputs will read as a
‘0’. Pins configured as digital inputs will
convert an analog input according to the
Schmitt Trigger input specification.
2: Analog levels on any pin that is defined as
a digital input may cause the input buffer
to consume more current than is
specified.
FIGURE 9-3: COMPARATOR OUTPUT BLOCK DIAGRAM
CnINV
To RA3 or RA4/T0CK1 pin

CnVOUT
To Data Bus Q D
CMCON<7:6>
EN
RD CMCON
Set CMIF bit Q D
EN Q1
CL
From other Comparator
RESET

PIC16F62X
9.6 Comparator Interrupts 9.7 Comparator Operation During
The Comparator Interrupt flag is set whenever there is
SLEEP
a change in the output value of either comparator. When a comparator is active and the device is placed
Software will need to maintain information about the in SLEEP mode, the comparator remains active and
status of the output bits, as read from CMCON<7:6>, to the interrupt is functional if enabled. This interrupt will
determine the actual change that has occurred. The wake-up the device from SLEEP mode when enabled.
CMIF bit, PIR1<6>, is the Comparator Interrupt Flag. While the comparator is powered-up, higher SLEEP
The CMIF bit must be RESET by clearing ‘0’. Since it is currents than shown in the power-down current
also possible to write a '1' to this register, a simulated specification will occur. Each comparator that is
interrupt may be initiated. operational will consume additional current as shown in
The CMIE bit (PIE1<6>) and the PEIE bit the comparator specifications. To minimize power
(INTCON<6>) must be set to enable the interrupt. In consumption while in SLEEP mode, turn off the
addition, the GIE bit must also be set. If any of these comparators, CM<2:0> = 111, before entering SLEEP.
bits are clear, the interrupt is not enabled, though the If the device wakes-up from SLEEP, the contents of the
CMIF bit will still be set if an interrupt condition occurs. CMCON register are not affected.
Note: If a change in the CMCON register 9.8 Effects of a RESET

(C1OUT or C2OUT) should occur when a
read operation is being executed (start of A device RESET forces the CMCON register to its
the Q2 cycle), then the CMIF (PIR1<6>) RESET state. This forces the Comparator module to be
interrupt flag may not get set. in the comparator RESET mode, CM2:CM0 = 000.
This ensures that all potential inputs are analog inputs.
The user, in the interrupt service routine, can clear the
Device current is minimized when analog inputs are
interrupt in the following manner:
present at RESET time. The comparators will be
a) Any write or read of CMCON. This will end the powered-down during the RESET interval.
mismatch condition.
b) Clear flag bit CMIF. 9.9 Analog Input Connection
A mismatch condition will continue to set flag bit CMIF. Considerations
Reading CMCON will end the mismatch condition, and A simplified circuit for an analog input is shown in
allow flag bit CMIF to be cleared. Figure 9-4. Since the analog pins are connected to a
digital output, they have reverse biased diodes to VDD
and VSS. The analog input therefore, must be between
VSS and VDD. If the input voltage deviates from this
range by more than 0.6V in either direction, one of the
diodes is forward biased and a latchup may occur. A
maximum source impedance of 10 kΩ is
recommended for the analog sources. Any external
component connected to an analog input pin, such as
a capacitor or a Zener diode, should have very little
leakage current.

PIC16F62X
FIGURE 9-4: ANALOG INPUT MODE
VDD
VT = 0.6V RIC
RS < 10K
AIN
CPIN ILEAKAGE
VA VT = 0.6V ±500 nA
5 pF
VSS
Legend CPIN = Input Capacitance
VT = Threshold Voltage
ILEAKAGE = Leakage Current At The Pin
RIC = Interconnect Resistance
RS = Source Impedance
VA = Analog Voltage
TABLE 9-1: REGISTERS ASSOCIATED WITH COMPARATOR MODULE

Value on
Value on
POR
RESETS
1Fh CMCON C2OUT C1OUT C2INV C1NV CIS CM2 CM1 CM0 0000 0000 0000 0000
0Bh/8Bh/
INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
10Bh/18Bh
Legend: x = Unknown, u = Unchanged, - = Unimplemented, read as ‘0’

PIC16F62X
10.0 VOLTAGE REFERENCE 10.1 Configuring the Voltage Reference
MODULE The Voltage Reference can output 16 distinct voltage
The Voltage Reference is a 16-tap resistor ladder levels for each range.
network that provides a selectable voltage reference. The equations used to calculate the output of the
The resistor ladder is segmented to provide two ranges Voltage Reference are as follows:
of VREF values and has a power-down function to if VRR = 1: VREF = (VR<3:0>/24) x VDD
conserve power when the reference is not being used.
The VRCON register controls the operation of the if VRR = 0: VREF = (VDD x 1/4) + (VR<3:0>/32) x
reference as shown in Figure 10-1. The block diagram VDD
is given in Figure 10-1. The setting time of the Voltage Reference must be
considered when changing the VREF output
(Table 17-2). Example 10-1 shows an example of how
to configure the Voltage Reference for an output
voltage of 1.25V with VDD = 5.0V.
REGISTER 10-1: VRCON REGISTER (ADDRESS: 9Fh)

R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
VREN VROE VRR — VR3 VR2 VR1 VR0
bit 7 bit 0
bit 7 VREN: VREF Enable

1 = VREF circuit powered on
0 = VREF circuit powered down, no IDD drain
bit 6 VROE: VREF Output Enable
1 = VREF is output on RA2 pin
0 = VREF is disconnected from RA2 pin
bit 5 VRR: VREF Range selection
1 = Low Range
0 = High Range
bit 3-0 VR<3:0>: VREF value selection 0 ≤ VR [3:0] ≤ 15
When VRR = 1: VREF = (VR<3:0>/ 24) * VDD
When VRR = 0: VREF = 1/4 * VDD + (VR<3:0>/ 32) * VDD
Legend:
FIGURE 10-1: VOLTAGE REFERENCE BLOCK DIAGRAM

VDD 16 Stages
VREN
8R R R R R
8R Vrr
VSS VSS
Vr3
Vref 16-1 Analog Mux (From VRCON<3:0>)
Vr0
Note 1: R is defined in Table 17-2.

PIC16F62X
EXAMPLE 10-1: VOLTAGE REFERENCE 10.4 Effects of a RESET
CONFIGURATION
A device RESET disables the Voltage Reference by
MOVLW 0x02 ; 4 Inputs Muxed clearing bit VREN (VRCON<7>). This RESET also
MOVWF CMCON ; to 2 comps. disconnects the reference from the RA2 pin by clearing
BSF STATUS,RP0 ; go to Bank 1 bit VROE (VRCON<6>) and selects the high voltage
MOVLW 0x07 ; RA3-RA0 are
range by clearing bit VRR (VRCON<5>). The VREF
value select bits, VRCON<3:0>, are also cleared.
MOVWF TRISA ; outputs
MOVLW 0xA6 ; enable VREF
10.5 Connection Considerations
MOVWF VRCON ; low range
; set VR<3:0>=6 The Voltage Reference module operates
BCF STATUS,RP0 ; go to Bank 0 independently of the Comparator module. The output
CALL DELAY10 ; 10µs delay
of the reference generator may be connected to the
RA2 pin if the TRISA<2> bit is set and the VROE bit,
10.2 Voltage Reference Accuracy/Error VRCON<6>, is set. Enabling the Voltage Reference
output onto the RA2 pin with an input signal present will
The full range of VSS to VDD cannot be realized due to increase current consumption. Connecting RA2 as a
the construction of the module. The transistors on the digital output with VREF enabled will also increase
top and bottom of the resistor ladder network current consumption.
(Figure 10-1) keep VREF from approaching VSS or VDD.
The RA2 pin can be used as a simple D/A output with
The Voltage Reference is VDD derived and therefore,
limited drive capability. Due to the limited drive
the VREF output changes with fluctuations in VDD. The
capability, a buffer must be used in conjunction with the
tested absolute accuracy of the Voltage Reference can
Voltage Reference output for external connections to
be found in Table 17-2.
VREF. Figure 10-2 shows an example buffering
technique.
10.3 Operation During SLEEP
When the device wakes-up from SLEEP through an
interrupt or a Watchdog Timer timeout, the contents of
the VRCON register are not affected. To minimize
current consumption in SLEEP mode, the Voltage
Reference should be disabled.
FIGURE 10-2: VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE
Op Amp
R(1) RA2
VREF +
Module VREF Output
Voltage
Reference
Output
Impedance
Note 1: R is dependent upon the Voltage Reference Configuration VRCON<3:0> and VRCON<5>.
TABLE 10-1: REGISTERS ASSOCIATED WITH VOLTAGE REFERENCE

Value On
Value On
POR
RESETS
9Fh VRCON VREN VROE VRR — VR3 VR2 VR1 VR0 000- 0000 000- 0000
1Fh CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 0000 0000 0000 0000
Note 1: — = Unimplemented, read as ‘0’.

PIC16F62X
11.0 CAPTURE/COMPARE/PWM TABLE 11-1: CCP MODE - TIMER
(CCP) MODULE RESOURCE
The CCP (Capture/Compare/PWM) module contains a CCP Mode Timer Resource

16-bit register which can operate as a 16-bit capture Capture Timer1
register, as a 16-bit compare register or as a PWM Compare Timer1
master/slave Duty Cycle register. Table 11-1 shows the PWM Timer2
timer resources of the CCP Module modes.
CCP1 Module
Capture/Compare/PWM Register1 (CCPR1) is com-
prised of two 8-bit registers: CCPR1L (low byte) and
CCPR1H (high byte). The CCP1CON register controls
the operation of CCP1. All are readable and writable.
Additional information on the CCP module is available
in the PICmicro™ Mid-Range Reference Manual,
(DS33023).
REGISTER 11-1: CCP1CON REGISTER (ADDRESS: 17h)

U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0
bit 7 bit 0

bit 5-4 CCP1X:CCP1Y: PWM Least Significant bits
Capture Mode: Unused
Compare Mode: Unused
PWM Mode: These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in
CCPRxL.
bit 3-0 CCP1M3:CCP1M0: CCPx Mode Select bits
0000 = Capture/Compare/PWM off (resets CCP1 module)
0100 = Capture mode, every falling edge
0101 = Capture mode, every rising edge
0110 = Capture mode, every 4th rising edge
0111 = Capture mode, every 16th rising edge
1000 = Compare mode, set output on match (CCP1IF bit is set)
1001 = Compare mode, clear output on match (CCP1IF bit is set)
1010 = Compare mode, generate software interrupt on match (CCP1IF bit is set, CCP1 pin is
unaffected)
1011 = Compare mode, trigger special event (CCP1IF bit is set; CCP1 resets TMR1
11xx = PWM mode
Legend:

PIC16F62X
11.1 Capture Mode Switching from one capture prescaler to another may
generate an interrupt. Also, the prescaler counter will
In Capture mode, CCPR1H:CCPR1L captures the not be cleared, therefore the first capture may be from
16-bit value of the TMR1 register when an event occurs a non-zero prescaler. Example 11-1 shows the
on pin RB3/CCP1. An event is defined as: recommended method for switching between capture
• Every falling edge prescalers. This example also clears the prescaler
• Every rising edge counter and will not generate the “false” interrupt.
• Every 4th rising edge
EXAMPLE 11-1: CHANGING BETWEEN
• Every 16th rising edge
CAPTURE PRESCALERS
An event is selected by control bits CCP1M3:CCP1M0
(CCP1CON<3:0>). When a capture is made, the Inter- CLRF CCP1CON ;Turn CCP module off
rupt Request Flag bit CCP1IF (PIR1<2>) is set. It must MOVLW NEW_CAPT_PS ;Load the W reg with
; the new prescaler
be cleared in software. If another capture occurs before
; mode value and CCP ON
the value in register CCPR1 is read, the old captured MOVWF CCP1CON ;Load CCP1CON with this
value will be lost. ; value
11.1.1 CCP PIN CONFIGURATION 11.2 Compare Mode

In Capture mode, the RB3/CCP1 pin should be In Compare mode, the 16-bit CCPR1 register value is
configured as an input by setting the TRISB<3> bit. constantly compared against the TMR1 register pair
Note: If the RB3/CCP1 is configured as an out- value. When a match occurs, the RB3/CCP1 pin is:
put, a write to the port can cause a capture • Driven High
condition. • Driven Low
• Remains Unchanged
TABLE 11-2: CAPTURE MODE OPERATION
BLOCK DIAGRAM The action on the pin is based on the value of control
bits CCP1M3:CCP1M0 (CCP1CON<3:0>). At the
Set flag bit CCP1IF same time, interrupt flag bit CCP1IF is set.
Prescaler (PIR1<2>)
³ 1, 4, 16
FIGURE 11-1: COMPARE MODE
RB3/CCP1 CCPR1H CCPR1L
Pin OPERATION BLOCK
and Capture DIAGRAM
edge detect Enable
Special Event Trigger will reset Timer1, but not set
TMR1H TMR1L interrupt flag bit TMR1IF (PIR1<0>)
CCP1CON<3:0>
Q’s Set flag bit CCP1IF
(PIR1<2>)
CCPR1H CCPR1L
11.1.2 TIMER1 MODE SELECTION
Q S Output
Timer1 must be running in Timer mode or Synchro- Logic Comparator
RB3/CCP1 R match
nized Counter mode for the CCP module to use the Pin
TRISB<3> TMR1H TMR1L
capture feature. In Asynchronous Counter mode, the Output Enable CCP1CON<3:0>
capture operation may not work. Mode Select
11.1.3 SOFTWARE INTERRUPT

11.2.1 CCP PIN CONFIGURATION
When the Capture mode is changed, a false capture
interrupt may be generated. The user should keep bit The user must configure the RB3/CCP1 pin as an
CCP1IE (PIE1<2>) clear to avoid false interrupts and output by clearing the TRISB<3> bit.
should clear the flag bit CCP1IF following any such
Note: Clearing the CCP1CON register will force
change in Operating mode.
the RB3/CCP1 compare output latch to the
11.1.4 CCP PRESCALER default low level. This is not the data latch.
There are four prescaler settings, specified by bits

CCP1M3:CCP1M0. Whenever the CCP module is
turned off, or the CCP module is not in Capture mode,
the prescaler counter is cleared. This means that any
RESET will clear the prescaler counter.

PIC16F62X
11.2.2 TIMER1 MODE SELECTION 11.2.4 SPECIAL EVENT TRIGGER
Timer1 must be running in Timer mode or Synchro- In this mode, an internal hardware trigger is generated
nized Counter mode if the CCP module is using the which may be used to initiate an action.
compare feature. In Asynchronous Counter mode, the The special event trigger output of CCP1 resets the
compare operation may not work. TMR1 register pair. This allows the CCPR1 register to
effectively be a 16-bit programmable period register for
11.2.3 SOFTWARE INTERRUPT MODE
Timer1.
When generate software interrupt is chosen, the CCP1
pin is not affected. Only a CCP interrupt is generated (if
enabled).
TABLE 11-3: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, AND TIMER1

Value on
Value on
POR
RESETS
10Bh/
18Bh
8Ch PIE1 EEIE CMIF RCIE TXIE — CCP1IE TMR2IE TMR1IE 0000 -000 0000 -000
87h TRISB PORTB Data Direction Register 1111 1111 1111 1111
0Eh TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu
0Fh TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1register xxxx xxxx uuuu uuuu
10h T1CON — — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
15h CCPR1L Capture/Compare/PWM register1 (LSB) xxxx xxxx uuuu uuuu
16h CCPR1H Capture/Compare/PWM register1 (MSB) xxxx xxxx uuuu uuuu
17h CCP1CON — — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by Capture and Timer1.

PIC16F62X
11.3 PWM Mode A PWM output (Figure 11-3) has a time-base (period)
and a time that the output stays high (duty cycle). The
In Pulse Width Modulation (PWM) mode, the CCP1 pin frequency of the PWM is the inverse of the period
produces up to a 10-bit resolution PWM output. Since (1/period).
the CCP1 pin is multiplexed with the PORTB data latch,
the TRISB<3> bit must be cleared to make the CCP1
FIGURE 11-3: PWM OUTPUT
pin an output.
Note: Clearing the CCP1CON register will force Period
the CCP1 PWM output latch to the default
low level. This is not the PORTB I/O data
latch.
Figure 11-2 shows a simplified block diagram of the Duty Cycle
CCP module in PWM mode.
TMR2 = PR2
For a step-by-step procedure on how to set up the CCP
TMR2 = Duty Cycle
module for PWM operation, see Section 11.3.3.
TMR2 = PR2
FIGURE 11-2: SIMPLIFIED PWM BLOCK
DIAGRAM
11.3.1 PWM PERIOD
CCP1CON<5:4>
Duty cycle registers The PWM period is specified by writing to the
CCPR1L PR2register. The PWM period can be calculated using
the following formula:
PWM period = [(PR2) + 1] • 4 • TOSC •
(TMR2 prescale value)
CCPR1H (Slave)
PWM frequency is defined as 1 / [PWM period].
When TMR2 is equal to PR2, the following three events
Comparator R Q
occur on the next increment cycle:
RB3/CCP1 • TMR2 is cleared
TMR2 (Note 1)
S • The CCP1 pin is set (exception: if PWM duty
cycle = 0%, the CCP1 pin will not be set)
Comparator TRISB<3> • The PWM duty cycle is latched from CCPR1L into
Clear Timer,
CCP1 pin and CCPR1H
latch D.C.
PR2
Note: The Timer2 postscaler (see Section 8.0) is
Note 1: 8-bit timer is concatenated with the 2-bit internal not used in the determination of the PWM
Q clock, or 2 bits of the prescaler to create 10-bit
time-base.
frequency. The postscaler could be used to
have an interrupt occur at a different fre-
quency than the PWM output.

PIC16F62X
11.3.2 PWM DUTY CYCLE EQUATION 11-2: MAXIMUM PWM
RESOLUTION
The PWM duty cycle is specified by writing to the
CCPR1L register and to the CCP1CON<5:4> bits. Up Fosc
to 10-bit resolution is available: the CCPR1L contains log (Fpwm x TMR2 Prescaler )
PWM
the eight MSbs and the CCP1CON<5:4> contains the Resolution = bits
two LSbs. This 10-bit value is represented by log (2)
CCPR1L:CCP1CON<5:4>. The following equation is
used to calculate the PWM duty cycle in time:
Note: If the PWM duty cycle value is longer than
EQUATION 11-1: PWM DUTY CYCLE the PWM period, the CCP1 pin will not be
cleared.
PWM duty cycle = (CCPR1L:CCP1CON<5:4>) •
Tosc • (TMR2 prescale value) For an example on the PWM period and duty cycle
calculation, see the PICmicro™ Mid-Range Reference
Manual (DS33023).
CCPR1L and CCP1CON<5:4> can be written to at any
time, but the duty cycle value is not latched into 11.3.3 SET-UP FOR PWM OPERATION
CCPR1H until after a match between PR2 and TMR2
The following steps should be taken when configuring
occurs (i.e., the period is complete). In PWM mode,
the CCP module for PWM operation:
CCPR1H is a read-only register.
1. Set the PWM period by writing to the PR2
The CCPR1H register and a 2-bit internal latch are
register.
used to double buffer the PWM duty cycle. This double
buffering is essential for glitchless PWM operation. 2. Set the PWM duty cycle by writing to the
CCPR1L register and CCP1CON<5:4> bits.
When the CCPR1H and 2-bit latch match TMR2
3. Make the CCP1 pin an output by clearing the
concatenated with an internal 2-bit Q clock or 2 bits of
TRISB<3> bit.
the TMR2 prescaler, the CCP1 pin is cleared.
4. Set the TMR2 prescale value and enable Timer2
Maximum PWM resolution (bits) for a given PWM by writing to T2CON.
frequency:
TABLE 11-4: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 20 MHz

PWM Frequency 1.22 kHz 4.88 kHz 19.53 kHz 78.12 kHz 156.3 kHz 208.3 kHz
Timer Prescaler (1, 4, 16) 16 4 1 1 1 1
PR2 Value 0xFF 0xFF 0xFF 0x3F 0x1F 0x17
Maximum Resolution (bits) 10 10 10 8 7 6.5
TABLE 11-5: REGISTERS ASSOCIATED WITH PWM AND TIMER2

Value on
Value on
POR
RESETS
10Bh/18Bh
87h TRISB PORTB Data Direction Register 1111 1111 1111 1111
11h TMR2 Timer2 module’s register 0000 0000 0000 0000
92h PR2 Timer2 module’s period register 1111 1111 1111 1111
12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 uuuu
15h CCPR1L Capture/Compare/PWM register1 (LSB) xxxx xxxx uuuu uuuu
16h CCPR1H Capture/Compare/PWM register1 (MSB) xxxx xxxx uuuu uuuu
17h CCP1CON — — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by PWM and Timer2.

PIC16F62X
NOTES:

PIC16F62X
12.0 UNIVERSAL SYNCHRONOUS/ The USART can be configured in the following modes:
ASYNCHRONOUS RECEIVER/ • Asynchronous (full duplex)
TRANSMITTER (USART) • Synchronous - Master (half duplex)
MODULE • Synchronous - Slave (half duplex)
Bit SPEN (RCSTA<7>), and bits TRISB<2:1>, have to
The Universal Synchronous Asynchronous Receiver
be set in order to configure pins RB2/TX/CK and RB1/
Transmitter (USART) module is one of the two serial
RX/DT as the Universal Synchronous Asynchronous
I/O modules. (USART is also known as a Serial
Receiver Transmitter.
Communications Interface or SCI). The USART can be
configured as a full duplex asynchronous system that
can communicate with peripheral devices such as CRT
terminals and personal computers, or it can be config-
ured as a half duplex synchronous system that can
communicate with peripheral devices such as A/D or D/
A integrated circuits, Serial EEPROMs etc.
REGISTER 12-1: TXSTA: TRANSMIT STATUS AND CONTROL REGISTER (ADDRESS: 98h)
R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R-1 R/W-0
CSRC TX9 TXEN SYNC — BRGH TRMT TX9D
bit 7 bit 0
bit 7 CSRC: Clock Source Select bit

Asynchronous mode
Don’t care
Synchronous mode
1 = Master mode (Clock generated internally from BRG)
0 = Slave mode (Clock from external source)
bit 6 TX9: 9-bit Transmit Enable bit
1 = Selects 9-bit transmission
0 = Selects 8-bit transmission
bit 5 TXEN: Transmit Enable bit(1)
1 = Transmit enabled
0 = Transmit disabled
bit 4 SYNC: USART Mode Select bit
1 = Synchronous mode
0 = Asynchronous mode
bit 2 BRGH: High Baud Rate Select bit
Asynchronous mode
1 = High speed
0 = Low speed
Synchronous mode
Unused in this mode
bit 1 TRMT: Transmit Shift Register STATUS bit
1 = TSR empty
0 = TSR full
bit 0 TX9D: 9th bit of transmit data. Can be PARITY bit.
Note 1: SREN/CREN overrides TXEN in SYNC mode.
Legend:

PIC16F62X
REGISTER 12-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER (ADDRESS: 18h)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-x
SPEN RX9 SREN CREN ADEN FERR OERR RX9D
bit 7 bit 0
bit 7 SPEN: Serial Port Enable bit

(Configures RB1/RX/DT and RB2/TX/CK pins as serial port pins when bits TRISB<2:17> are set)
1 = Serial port enabled
0 = Serial port disabled
bit 6 RX9: 9-bit Receive Enable bit
1 = Selects 9-bit reception
0 = Selects 8-bit reception
bit 5 SREN: Single Receive Enable bit
Asynchronous mode:
Don’t care
Synchronous mode - master:
1 = Enables single receive
0 = Disables single receive
This bit is cleared after reception is complete.
Synchronous mode - slave:
Unused in this mode
bit 4 CREN: Continuous Receive Enable bit
Asynchronous mode:
1 = Enables continuous receive
0 = Disables continuous receive
Synchronous mode:
1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN)
0 = Disables continuous receive
bit 3 ADEN: Address Detect Enable bit
Asynchronous mode 9-bit (RX9 = 1):
1 = Enables address detection, enable interrupt and load of the receive buffer when RSR<8> is set
0 = Disables address detection, all bytes are received, and ninth bit can be used as PARITY bit
Asynchronous mode 8-bit (RX9=0):
Unused in this mode
Synchronous mode
Unused in this mode
bit 2 FERR: Framing Error bit
1 = Framing error (Can be updated by reading RCREG register and receive next valid byte)
0 = No framing error
bit 1 OERR: Overrun Error bit
1 = Overrun error (Can be cleared by clearing bit CREN)
0 = No overrun error
bit 0 RX9D: 9th bit of received data (Can be PARITY bit)
Legend:

PIC16F62X
12.1 USART Baud Rate Generator EXAMPLE 12-1: CALCULATING BAUD
(BRG) RATE ERROR
The BRG supports both the Asynchronous and
Synchronous modes of the USART. It is a dedicated Desired Baud rate = FOSC / (64(X + 1))
8-bit baud rate generator. The SPBRG register controls 9600 = 16000000 / (64( +1 ))X
the period of a free running 8-bit timer. In Asynchro- X = î25.042°
nous mode bit BRGH (TXSTA<2>) also controls the
baud rate. In Synchronous mode bit BRGH is ignored. Calculated Baud Rate = 16000000 / (64(25 + 1))
Table 12-1 shows the formula for computation of the = 9615
baud rate for different USART modes which only apply
in Master mode (internal clock). Error = (Calculated Baud Rate = Desired Baud Rate)
Desired Baud Rate
Given the desired baud rate and Fosc, the nearest
integer value for the SPBRG register can be calculated = (9615 - 9600)/ 9600
using the formula in Table 12-1. From this, the error in = 0.16%
baud rate can be determined.
Example 12-1 shows the calculation of the baud rate It may be advantageous to use the high baud rate
error for the following conditions: (BRGH = 1) even for slower baud clocks. This is
because the FOSC/(16(X + 1)) equation can reduce the
FOSC = 16 MHz baud rate error in some cases.
Desired Baud Rate = 9600 Writing a new value to the SPBRG register, causes the
BRGH = 0 BRG timer to be RESET (or cleared), this ensures the
BRG does not wait for a timer overflow before
SYNC = 0
outputting the new baud rate.
TABLE 12-1: BAUD RATE FORMULA

SYNC BRGH = 0 (Low Speed) BRGH = 1 (High Speed)
0 (Asynchronous) Baud Rate = FOSC/(64(X+1)) Baud Rate= FOSC/(16(X+1))
1 (Synchronous) Baud Rate = FOSC/(4(X+1)) NA
Legend: X = value in SPBRG (0 to 255)
TABLE 12-2: REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR

Value on all
Value on
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 other
POR
RESETS
98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010
18h RCSTA SPEN RX9 SREN CREN ADEN FERR OERR RX9D 0000 -00x 0000 -00x
99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000
Legend: x = unknown, - = unimplemented read as '0'.
Shaded cells are not used by the BRG.

PIC16F62X
TABLE 12-3: BAUD RATES FOR SYNCHRONOUS MODE
FOSC = 20 MHz SPBRG 16 MHz SPBRG 10 MHz SPBRG
BAUD
value value value
RATE (K) KBAUD ERROR KBAUD ERROR KBAUD ERROR
(decimal) (decimal) (decimal)
0.3 NA — — NA — — NA — —
1.2 NA — — NA — — NA — —
2.4 NA — — NA — — NA — —
9.6 NA — — NA — — 9.766 +1.73% 255
19.2 19.53 +1.73% 255 19.23 +0.16% 207 19.23 +0.16% 129
76.8 76.92 +0.16% 64 76.92 +0.16% 51 75.76 -1.36% 32
96 96.15 +0.16% 51 95.24 -0.79% 41 96.15 +0.16% 25
300 294.1 -1.96 16 307.69 +2.56% 12 312.5 +4.17% 7
500 500 0 9 500 0 7 500 0 4
HIGH 5000 — 0 4000 — 0 2500 — 0
LOW 19.53 — 255 15.625 — 255 9.766 — 255
FOSC = 7.15909 MHz SPBRG 5.0688 MHz SPBRG 4 MHz SPBRG

BAUD
value value value
0.3 NA — — NA — — NA — —
1.2 NA — — NA — — NA — —
2.4 NA — — NA — — NA — —
9.6 9.622 +0.23% 185 9.6 0 131 9.615 +0.16% 103
19.2 19.24 +0.23% 92 19.2 0 65 19.231 +0.16% 51
76.8 77.82 +1.32 22 79.2 +3.13% 15 75.923 +0.16% 12
96 94.20 -1.88 18 97.48 +1.54% 12 1000 +4.17% 9
300 298.3 -0.57 5 316.8 5.60% 3 NA — —
500 NA — — NA — — NA — —
HIGH 1789.8 — 0 1267 — 0 100 — 0
LOW 6.991 — 255 4.950 — 255 3.906 — 255
BAUD FOSC = 3.579545 MHz SPBRG 1 MHz SPBRG 32.768 MHz SPBRG
RATE value value value
(K) KBAUD ERROR (decimal) KBAUD ERROR (decimal) KBAUD ERROR (decimal)
0.3 NA — — NA — — 0.303 +1.14% 26
1.2 NA — — 1.202 +0.16% 207 1.170 -2.48% 6
2.4 NA — — 2.404 +0.16% 103 NA — —
9.6 9.622 +0.23% 92 9.615 +0.16% 25 NA — —
19.2 19.04 -0.83% 46 19.24 +0.16% 12 NA — —
76.8 74.57 -2.90% 11 83.34 +8.51% 2 NA — —
96 99.43 +3.57% 8 NA — — NA — —
300 298.3 0.57% 2 NA — — NA — —
500 NA — — NA — — — —
HIGH 894.9 — 0 250 — 0 8.192 — 0
LOW 3.496 — 255 0.9766 — 255 0.032 — 255

PIC16F62X
TABLE 12-4: BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 0)
BAUD
value value value
0.3 NA — — NA — — NA — —
1.2 1.221 +1.73% 255 1.202 +0.16% 207 1.202 +0.16% 129
2.4 2.404 +0.16% 129 2.404 +0.16% 103 2.404 +0.16% 64
9.6 9.469 -1.36% 32 9.615 +0.16% 25 9.766 +1.73% 15
19.2 19.53 +1.73% 15 19.23 +0.16% 12 19.53 +1.73V 7
76.8 78.13 +1.73% 3 83.33 +8.51% 2 78.13 +1.73% 1
96 104.2 +8.51% 2 NA — — NA — —
300 312.5 +4.17% 0 NA — — NA — —
500 NA — — NA — — NA — —
HIGH 312.5 — 0 250 — 0 156.3 — 0
LOW 1.221 — 255 0.977 — 255 0.6104 — 255

BAUD
value value value
0.3 NA — — 0.31 +3.13% 255 0.3005 -0.17% 207
1.2 1.203 +0.23% 92 1.2 0 65 1.202 +1.67% 51
2.4 2.380 -0.83% 46 2.4 0 32 2.404 +1.67% 25
9.6 9.322 -2.90% 11 9.9 +3.13% 7 NA — —
19.2 18.64 -2.90% 5 19.8 +3.13% 3 NA — —
76.8 NA — — 79.2 +3.13% 0 NA — —
96 NA — — NA — — NA — —
300 NA — — NA — — NA — —
500 NA — — NA — — NA — —
HIGH 111.9 — 0 79.2 — 0 62.500 — 0
LOW 0.437 — 255 0.3094 — 255 3.906 — 255
0.3 0.301 +0.23% 185 0.300 +0.16% 51 0.256 -14.67% 1
1.2 1.190 -0.83% 46 1.202 +0.16% 12 NA — —
2.4 2.432 +1.32% 22 2.232 -6.99% 6 NA — —
9.6 9.322 -2.90% 5 NA — — NA — —
19.2 18.64 -2.90% 2 NA — — NA — —
76.8 NA — — NA — — NA — —
96 NA — — NA — — NA — —
300 NA — — NA — — NA — —
500 NA — — NA — — NA — —
HIGH 55.93 — 0 15.63 — 0 0.512 — 0
LOW 0.2185 — 255 0.0610 — 255 0.0020 — 255

PIC16F62X
TABLE 12-5: BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 1)
BAUD
value value value
9600 9.615 +0.16% 129 9.615 +0.16% 103 9.615 +0.16% 64
19200 19.230 +0.16% 64 19.230 +0.16% 51 18.939 -1.36% 32
38400 37.878 -1.36% 32 38.461 +0.16% 25 39.062 +1.7% 15
57600 56.818 -1.36% 21 58.823 +2.12% 16 56.818 -1.36% 10
115200 113.636 -1.36% 10 111.111 -3.55% 8 125 +8.51% 4
250000 250 0 4 250 0 3 NA — —
625000 625 0 1 NA — — 625 0 0
1250000 1250 0 0 NA — — NA — —

BAUD
value value value
9600 9.520 -0.83% 46 9598.485 0.016% 32 9615.385 0.160% 25
19200 19.454 +1.32% 22 18632.35 -2.956% 16 19230.77 0.160% 12
38400 37.286 -2.90% 11 39593.75 3.109% 7 35714.29 -6.994% 6
57600 55.930 -2.90% 7 52791.67 -8.348% 5 62500 8.507% 3
115200 111.860 -2.90% 3 105583.3 -8.348% 2 125000 8.507% 1
250000 NA — — 316750 26.700% 0 250000 0.000% 0
625000 NA — — NA — — NA — —
1250000 NA — — NA — — NA — —
9600 9725.543 1.308% 22 8.928 -6.994% 6 NA NA NA
19200 18640.63 -2.913% 11 20833.3 8.507% 2 NA NA NA
38400 37281.25 -2.913% 5 31250 -18.620% 1 NA NA NA
57600 55921.88 -2.913% 3 62500 +8.507 0 NA NA NA
115200 111243.8 -2.913% 1 NA — — NA NA NA
250000 223687.5 -10.525% 0 NA — — NA NA NA
625000 NA — — NA — — NA NA NA
1250000 NA — — NA — — NA NA NA

PIC16F62X
The data on the RB1/RX/DT pin is sampled three times
by a majority detect circuit to determine if a high or a
low level is present at the RX pin. If bit BRGH
(TXSTA<2>) is clear (i.e., at the low baud rates), the
sampling is done on the seventh, eighth and ninth
falling edges of a x16 clock (Figure 12-3). If bit BRGH
is set (i.e., at the high baud rates), the sampling is done
on the 3 clock edges preceding the second rising edge
after the first falling edge of a x4 clock (Figure 12-4 and
Figure 12-5).
FIGURE 12-1: RX PIN SAMPLING SCHEME. BRGH = 0
START bit Bit0

RX
(RB1/RX/DT pin)
Baud CLK for all but START bit
baud CLK
x16 CLK
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3
Samples
FIGURE 12-2: RX PIN SAMPLING SCHEME, BRGH = 1

RX pin
START Bit Bit0 Bit1
baud clk
First falling edge after RX pin goes low
Second rising edge
x4 clk
1 2 3 4 1 2 3 4 1 2
Q2, Q4 clk
Samples Samples Samples
FIGURE 12-3: RX PIN SAMPLING SCHEME, BRGH = 1

RX pin
START Bit Bit0

Baud CLK
First falling edge after RX pin goes low
Second rising edge
x4 CLK
1 2 3 4
Q2, Q4 CLK
Samples

PIC16F62X
FIGURE 12-4: RX PIN SAMPLING SCHEME, BRGH = 0 OR BRGH = 1
START bit Bit0

RX
(RB1/RX/DT pin)
Baud CLK
x16 CLK
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3
Samples
12.2 USART Asynchronous Mode software. It will RESET only when new data is loaded
into the TXREG register. While flag bit TXIF indicated
In this mode, the USART uses standard non-return to the status of the TXREG register, another bit TRMT
zero (NRZ) format (one START bit, eight or nine data (TXSTA<1>) shows the status of the TSR register.
bits and one STOP bit). The most common data format STATUS bit TRMT is a read only bit which is set when
is 8 bits. A dedicated 8-bit baud rate generator is used the TSR register is empty. No interrupt logic is tied to
to derive baud rate frequencies from the oscillator. The this bit, so the user has to poll this bit in order to
USART transmits and receives the LSb first. The determine if the TSR register is empty.
USART’s transmitter and receiver are functionally
independent but use the same data format and baud Note 1: The TSR register is not mapped in data
rate. The baud rate generator produces a clock either memory so it is not available to the user.
x16 or x64 of the bit shift rate, depending on bit BRGH 2: Flag bit TXIF is set when enable bit TXEN
(TXSTA<2>). Parity is not supported by the hardware, is set.
but can be implemented in software (and stored as the
Transmission is enabled by setting enable bit TXEN
ninth data bit). Asynchronous mode is stopped during
(TXSTA<5>). The actual transmission will not occur
SLEEP.
until the TXREG register has been loaded with data
Asynchronous mode is selected by clearing bit SYNC and the baud rate generator (BRG) has produced a
(TXSTA<4>). shift clock (Figure 12-5). The transmission can also be
The USART Asynchronous module consists of the started by first loading the TXREG register and then
following important elements: setting enable bit TXEN. Normally when transmission
is first started, the TSR register is empty, so a transfer
• Baud Rate Generator
to the TXREG register will result in an immediate
• Sampling Circuit transfer to TSR resulting in an empty TXREG. A back-
• Asynchronous Transmitter to-back transfer is thus possible (Figure 12-7). Clearing
• Asynchronous Receiver enable bit TXEN during a transmission will cause the
transmission to be aborted and will RESET the
12.2.1 USART ASYNCHRONOUS transmitter. As a result the RB2/TX/CK pin will revert to
TRANSMITTER hi-impedance.
The USART transmitter block diagram is shown in In order to select 9-bit transmission, transmit bit TX9
Figure 12-5. The heart of the transmitter is the transmit (TXSTA<6>) should be set and the ninth bit should be
(serial) shift register (TSR). The shift register obtains its written to TX9D (TXSTA<0>). The ninth bit must be
data from the read/write transmit buffer, TXREG. The written before writing the 8-bit data to the TXREG
TXREG register is loaded with data in software. The register. This is because a data write to the TXREG
TSR register is not loaded until the STOP bit has been register can result in an immediate transfer of the data
transmitted from the previous load. As soon as the to the TSR register (if the TSR is empty). In such a
STOP bit is transmitted, the TSR is loaded with new case, an incorrect ninth data bit may be loaded in the
data from the TXREG register (if available). Once the TSR register.
TXREG register transfers the data to the TSR register
(occurs in one TCY), the TXREG register is empty and
flag bit TXIF (PIR1<4>) is set. This interrupt can be
enabled/disabled by setting/clearing enable bit TXIE
( PIE1<4>). Flag bit TXIF will be set regardless of the
state of enable bit TXIE and cannot be cleared in

PIC16F62X
FIGURE 12-5: USART TRANSMIT BLOCK DIAGRAM
Data Bus
TXIF TXREG register
TXIE
8
MSb LSb
(8) 2 2 2 0 Pin Buffer
and Control
TSR register RB2/TX/CK pin
Interrupt
TXEN Baud Rate CLK

TRMT SPEN
SPBRG
Baud Rate Generator TX9

TX9D
Steps to follow when setting up an Asynchronous

Transmission:
1. Initialize the SPBRG register for the appropriate
baud rate. If a high speed baud rate is desired,
set bit BRGH. (Section 12.1)
2. Enable the asynchronous serial port by clearing
bit SYNC and setting bit SPEN.
3. If interrupts are desired, then set enable bit
TXIE.
4. If 9-bit transmission is desired, then set transmit
bit TX9.
5. Enable the transmission by setting bit TXEN,
which will also set bit TXIF.
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
7. Load data to the TXREG register (starts
transmission).
FIGURE 12-6: ASYNCHRONOUS TRANSMISSION
Write to TXREG
Word 1
BRG output
(shift clock)
RB2/TX/CK (pin)
START Bit Bit 0 Bit 1 Bit 7/8 STOP Bit
WORD 1
TXIF bit
(Transmit buffer
reg. empty flag)
TRMT bit WORD 1

Transmit Shift Reg
(Transmit shift
reg. empty flag)

PIC16F62X
FIGURE 12-7: ASYNCHRONOUS TRANSMISSION (BACK TO BACK)
Write to TXREG
WORD 1 WORD 2
BRG output
(shift clock)
RB2/TX/CK (pin)
START Bit Bit 0 Bit 1 Bit 7/8 STOP Bit START Bit Bit 0
TXIF bit
(interrupt reg. flag) WORD 1 WORD 2
TRMT bit WORD 1 WORD 2

(Transmit shift Transmit Shift Reg.
reg. empty flag) Transmit Shift Reg.
Note 1: This.timing diagram shows two consecutive transmissions.
TABLE 12-6: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION

Value on
Value on
POR
RESETS
19h TXREG USART Transmit Register 0000 0000 0000 0000
Legend: x = unknown, - = unimplemented locations read as '0'.
Shaded cells are not used for Asynchronous Transmission.

PIC16F62X
12.2.2 ADEN USART ASYNCHRONOUS It is possible for two bytes of data to be received and
RECEIVER transferred to the RCREG FIFO, and a third byte begin
shifting to the RSR register. On the detection of the
The receiver block diagram is shown in Figure 12-8. STOP bit of the third byte, if the RCREG register is still
The data is received on the RB1/RX/DT pin and drives full, then overrun error bit OERR (RCSTA<1>) will be
the data recovery block. The data recovery block is set. The word in the RSR will be lost. The RCREG
actually a high speed shifter operating at x16 times the register can be read twice to retrieve the two bytes in
baud rate, whereas the main receive serial shifter the FIFO. Overrun bit OERR has to be cleared in soft-
operates at the bit rate or at FOSC. ware. This is done by resetting the receive logic (CREN
Once Asynchronous mode is selected, reception is is cleared and then set). If bit OERR is set, transfers
enabled by setting bit CREN (RCSTA<4>). from the RSR register to the RCREG register are inhib-
ited, so it is essential to clear error bit OERR if it is set.
The heart of the receiver is the Receive (serial) Shift
Framing error bit FERR (RCSTA<2>) is set if a STOP
register (RSR). After sampling the STOP bit, the
bit is detected as clear. Bit FERR and the 9th receive
received data in the RSR is transferred to the RCREG
bit are buffered the same way as the receive data.
register (if it is empty). If the transfer is complete, flag
Reading the RCREG will load bits RX9D and FERR
bit RCIF (PIR1<5>) is set. The actual interrupt can be
with new values, therefore it is essential for the user to
enabled/disabled by setting/clearing enable bit RCIE
read the RCSTA register before reading the RCREG
(PIE1<5>). Flag bit RCIF is a read only bit which is
register in order not to lose the old FERR and RX9D
cleared by the hardware. It is cleared when the RCREG
information.
register has been read and is empty. The RCREG is a
double buffered register ( i.e., it is a two-deep FIFO).
FIGURE 12-8: USART RECEIVE BLOCK DIAGRAM

x64 Baud Rate CLK
OERR FERR
CREN
SPBRG
³ 64 MSb RSR register LSb
or
³ 16 0 Start
Baud Rate Generator Stop (8) 7 ² ² ² 1
RB1/RX/DT
Pin Buffer Data
and Control Recovery RX9
SPEN
RX9 Enable
ADEN Load of
RX9 Receive
Buffer
ADEN
RSR<8> 8
RX9D RCREG register

FIFO
RX9D RCREG register
Interrupt RCIF
Data Bus
RCIE

PIC16F62X
FIGURE 12-9: ASYNCHRONOUS RECEPTION WITH ADDRESS DETECT
RB1/RX/DT (PIN) START START
BIT BIT0 BIT1 BIT8 STOP BIT BIT0 BIT8 STOP
BIT BIT
RCV SHIFT REG
RCV BUFFER REG
BIT8 = 0, DATA BYTE BIT8 = 1, ADDRESS BYTE WORD 1
RCREG
READ RCV
BUFFER REG
RCREG
RCIF
(INTERRUPT FLAG)
'1' '1'
ADEN = 1
(ADDRESS MATCH
ENABLE)
Note 1: This timing diagram shows a data byte followed by an address byte. The data byte is not read into the RCREG
(Receive Buffer) because ADEN = 1 and Bit 8 = 0.
FIGURE 12-10: ASYNCHRONOUS RECEPTION WITH ADDRESS BYTE FIRST

BIT BIT
RCV SHIFT
REG
RCV BUFFER REG
BIT8 = 1, ADDRESS BYTE WORD 1 BIT8 = 0, DATA BYTE
RCREG
READ RCV
BUFFER REG
RCREG
RCIF
(INTERRUPT FLAG)
'1' '1'
ADEN = 1
(ADDRESS MATCH
ENABLE)
Note 1: This timing diagram shows an address byte followed by an data byte. The data byte is not read into the RCREG
(receive buffer) because ADEN was not updated (still = 1) and Bit 8 = 0.
FIGURE 12-11: ASYNCHRONOUS RECEPTION WITH ADDRESS BYTE FIRST FOLLOWED BY

VALID DATA BYTE
BIT BIT
RCV SHIFT
REG
RCV BUFFER REG
BIT8 = 1, ADDRESS BYTE WORD 1 BIT8 = 0, DATA BYTE WORD 2
RCREG RCREG
READ RCV
BUFFER REG
RCREG
RCIF
(INTERRUPT FLAG)
ADEN
(ADDRESS MATCH
ENABLE)
Note 1: This timing diagram shows an address byte followed by an data byte. The data byte is read into the RCREG
(Receive Buffer) because ADEN was updated after an address match, and was cleared to a ‘0’, so the contents of
the Receive Shift Register (RSR) are read into the Receive Buffer regardless of the value of Bit 8.

PIC16F62X
Steps to follow when setting up an Asynchronous
Reception:
1. Initialize the SPBRG register for the appropriate
baud rate. If a high speed baud rate is desired,
set bit BRGH. (Section 12.1).
2. Enable the asynchronous serial port by clearing
bit SYNC, and setting bit SPEN.
RCIE.
4. If 9-bit reception is desired, then set bit RX9.
5. Enable the reception by setting bit CREN.
6. Flag bit RCIF will be set when reception is
complete and an interrupt will be generated if
enable bit RCIE was set.
7. Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
8. Read the 8-bit received data by reading the
RCREG register.
9. If any error occurred, clear the error by clearing
enable bit CREN.
TABLE 12-7: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION

Value on
Value on
POR
RESETS
1Ah RCREG USART Receive Register 0000 0000 0000 0000
Legend: x = unknown, - = unimplemented locations read as '0'. Shaded cells are not used for Asynchronous Reception.

PIC16F62X
12.3 USART Function The ADEN bit will only take effect when the receiver is
configured in 9-bit mode (RX9 = '1'). When ADEN is
The USART function is similar to that on the disabled (='0'), all data bytes are received and the 9th
PIC16C74B, which includes the BRGH = 1 fix. bit can be used as the PARITY bit.
12.3.1 USART 9-BIT RECEIVER WITH The USART Receive Block Diagram is shown in
ADDRESS DETECT Figure 12-8.
Reception is enabled by setting bit CREN
When the RX9 bit is set in the RCSTA register, 9 bits
(RCSTA<4>).
are received and the ninth bit is placed in the RX9D bit
of the RCSTA register. The USART module has a 12.3.1.1 Setting up 9-bit mode with Address
special provision for multiprocessor communication. Detect
Multiprocessor communication is enabled by setting
the ADEN bit (RCSTA<3>) along with the RX9 bit. The Steps to follow when setting up an Asynchronous or
port is now programmed so when the last bit is Synchronous Reception with Address Detect Enabled:
received, the contents of the Receive Shift Register 1. Initialize the SPBRG register for the appropriate
(RSR) are transferred to the receive buffer. The ninth baud rate. If a high speed baud rate is desired,
bit of the RSR (RSR<8>) is transferred to RX9D, and set bit BRGH.
the receive interrupt is set if, and only, if RSR<8> = 1. 2. Enable asynchronous or synchronous commu-
This feature can be used in a multiprocessor system as nication by setting or clearing bit SYNC and
follows: setting bit SPEN.
A master processor intends to transmit a block of data 3. If interrupts are desired, then set enable bit
to one of many slaves. It must first send out an address RCIE.
byte that identifies the target slave. An address byte is 4. Set bit RX9 to enable 9-bit reception.
identified by setting the ninth bit (RSR<8>) to a '1'
5. Set ADEN to enable address detect.
(instead of a '0' for a data byte). If the ADEN and RX9
bits are set in the slave’s RCSTA register, enabling mul- 6. Enable the reception by setting enable bit CREN
tiprocessor communication, all data bytes will be or SREN.
ignored. However, if the ninth received bit is equal to a 7. Flag bit RCIF will be set when reception is
‘1’, indicating that the received byte is an address, the complete, and an interrupt will be generated if
slave will be interrupted and the contents of the RSR enable bit RCIE was set.
register will be transferred into the receive buffer. This 8. Read the 8-bit received data by reading the
allows the slave to be interrupted only by addresses, so RCREG register to determine if the device is
that the slave can examine the received byte to see if it being addressed.
is being addressed. The addressed slave will then clear 9. If any error occurred, clear the error by clearing
its ADEN bit and prepare to receive data bytes from the enable bit CREN if it was already set.
master. 10. If the device has been addressed (RSR<8> = 1
When ADEN is enabled (='1'), all data bytes are with address match enabled), clear the ADEN
ignored. Following the STOP bit, the data will not be and RCIF bits to allow data bytes and address
loaded into the receive buffer, and no interrupt will bytes to be read into the receive buffer and
occur. If another byte is shifted into the RSR register, interrupt the CPU.
the previous data byte will be lost.
TABLE 12-8: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION

Value on
Value on
POR
RESETS
1Ah RCREG RX7 RX6 RX5 RX4 RX3 RX2 RX1 RX0 0000 0000 0000 0000
Legend: x = unknown, - = unimplemented locations read as '0'. Shaded cells are not used for Asynchronous Reception.

PIC16F62X
12.4 USART Synchronous Master Clearing enable bit TXEN, during a transmission, will
Mode cause the transmission to be aborted and will RESET
the transmitter. The DT and CK pins will revert to hi-
In Synchronous Master mode, the data is transmitted in impedance. If either bit CREN or bit SREN is set,
a half-duplex manner (i.e., transmission and reception during a transmission, the transmission is aborted and
do not occur at the same time). When transmitting data, the DT pin reverts to a hi-impedance state (for a recep-
the reception is inhibited and vice versa. Synchronous tion). The CK pin will remain an output if bit CSRC is set
mode is entered by setting bit SYNC (TXSTA<4>). In (internal clock). The transmitter logic however is not
addition, enable bit SPEN (RCSTA<7>) is set in order RESET although it is disconnected from the pins. In
to configure the RB2/TX/CK and RB1/RX/DT I/O pins order to RESET the transmitter, the user has to clear bit
to CK (clock) and DT (data) lines respectively. The TXEN. If bit SREN is set (to interrupt an on-going
Master mode indicates that the processor transmits the transmission and receive a single word), then after the
master clock on the CK line. The Master mode is single word is received, bit SREN will be cleared and
entered by setting bit CSRC (TXSTA<7>). the serial port will revert back to transmitting since bit
TXEN is still set. The DT line will immediately switch
12.4.1 USART SYNCHRONOUS MASTER from Hi-impedance Receive mode to transmit and start
TRANSMISSION driving. To avoid this, bit TXEN should be cleared.
The USART Transmitter Block Diagram is shown in In order to select 9-bit transmission, the TX9
Figure 12-5. The heart of the transmitter is the Transmit (TXSTA<6>) bit should be set and the ninth bit should
(serial) Shift register (TSR). The Shift register obtains be written to bit TX9D (TXSTA<0>). The ninth bit must
its data from the read/write transmit buffer register be written before writing the 8-bit data to the TXREG
TXREG. The TXREG register is loaded with data in register. This is because a data write to the TXREG can
software. The TSR register is not loaded until the last result in an immediate transfer of the data to the TSR
bit has been transmitted from the previous load. As register (if the TSR is empty). If the TSR was empty and
soon as the last bit is transmitted, the TSR is loaded the TXREG was written before writing the “new” TX9D,
with new data from the TXREG (if available). Once the the “present” value of bit TX9D is loaded.
TXREG register transfers the data to the TSR register Steps to follow when setting up a Synchronous Master
(occurs in one Tcycle), the TXREG is empty and Transmission:
interrupt bit, TXIF (PIR1<4>) is set. The interrupt can
be enabled/disabled by setting/clearing enable bit TXIE 1. Initialize the SPBRG register for the appropriate
(PIE1<4>). Flag bit TXIF will be set regardless of the baud rate (Section 12.1).
state of enable bit TXIE and cannot be cleared in soft- 2. Enable the synchronous master serial port by
ware. It will RESET only when new data is loaded into setting bits SYNC, SPEN, and CSRC.
the TXREG register. While flag bit TXIF indicates the 3. If interrupts are desired, then set enable bit
status of the TXREG register, another bit TRMT TXIE.
(TXSTA<1>) shows the status of the TSR register. 4. If 9-bit transmission is desired, then set bit TX9.
TRMT is a read only bit which is set when the TSR is 5. Enable the transmission by setting bit TXEN.
empty. No interrupt logic is tied to this bit, so the user
6. If 9-bit transmission is selected, the ninth bit
has to poll this bit in order to determine if the TSR reg-
should be loaded in bit TX9D.
ister is empty. The TSR is not mapped in data memory
so it is not available to the user. 7. Start transmission by loading data to the TXREG
register.
Transmission is enabled by setting enable bit TXEN
(TXSTA<5>). The actual transmission will not occur
until the TXREG register has been loaded with data.
The first data bit will be shifted out on the next available
rising edge of the clock on the CK line. Data out is sta-
ble around the falling edge of the synchronous clock
(Figure 12-12). The transmission can also be started
by first loading the TXREG register and then setting bit
TXEN (Figure 12-13). This is advantageous when slow
baud rates are selected, since the BRG is kept in
RESET when bits TXEN, CREN, and SREN are clear.
Setting enable bit TXEN will start the BRG, creating a
shift clock immediately. Normally when transmission is
first started, the TSR register is empty, so a transfer to
the TXREG register will result in an immediate transfer
to TSR resulting in an empty TXREG. Back-to-back
transfers are possible.

PIC16F62X
TABLE 12-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION
Value on all
Value on
POR
RESETS
Legend: x = unknown, - = unimplemented, read as '0'. Shaded cells are not used for Synchronous Master Transmission.
FIGURE 12-12: SYNCHRONOUS TRANSMISSION
Q1Q2 Q3Q4 Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2 Q3Q4 Q3Q4 Q1Q2 Q3Q4 Q1Q2 Q3Q4 Q1Q2 Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4
RB1/RX/DT Pin Bit 0 Bit 1 Bit 2 Bit 7 Bit 0 Bit 1 Bit 7

WORD 1 WORD 2
RB2/TX/CK Pin
WRITE to
TXREG REG
Write WORD1 Write WORD2
TXIF Bit
(Interrupt Flag)
TRMTTRMT
Bit
'1' '1'
TXEN Bit
Note 1: Sync Master mode; SPBRG = ‘0’. Continuous transmission of two 8-bit words.
FIGURE 12-13: SYNCHRONOUS TRANSMISSION (THROUGH TXEN)
RB1/RX/DT pin Bit0 Bit1 Bit2 Bit6 Bit7
RB2/TX/CK pin
Write to
TXREG reg
TXIF bit
TRMT bit
TXEN bit

PIC16F62X
12.4.2 USART SYNCHRONOUS MASTER receive bit is buffered the same way as the receive
RECEPTION data. Reading the RCREG register, will load bit RX9D
with a new value, therefore it is essential for the user to
Once Synchronous mode is selected, reception is read the RCSTA register before reading RCREG in
enabled by setting either enable bit SREN order not to lose the old RX9D information.
(RCSTA<5>) or enable bit CREN (RCSTA<4>). Data is
sampled on the RB1/RX/DT pin on the falling edge of Steps to follow when setting up a Synchronous Master
the clock. If enable bit SREN is set, then only a single Reception:
word is received. If enable bit CREN is set, the recep- 1. Initialize the SPBRG register for the appropriate
tion is continuous until CREN is cleared. If both bits are baud rate. (Section 12.1)
set, then CREN takes precedence. After clocking the 2. Enable the synchronous master serial port by
last bit, the received data in the Receive Shift Register setting bits SYNC, SPEN, and CSRC.
(RSR) is transferred to the RCREG register (if it is 3. Ensure bits CREN and SREN are clear.
empty). When the transfer is complete, interrupt flag bit
RCIF (PIR1<5>) is set. The actual interrupt can be
RCIE.
enabled/disabled by setting/clearing enable bit RCIE
(PIE1<5>). Flag bit RCIF is a read only bit which is 5. If 9-bit reception is desired, then set bit RX9.
RESET by the hardware. In this case, it is RESET 6. If a single reception is required, set bit SREN.
when the RCREG register has been read and is empty. For continuous reception set bit CREN.
The RCREG is a double buffered register (i.e., it is a 7. Interrupt flag bit RCIF will be set when reception
two-deep FIFO). It is possible for two bytes of data to is complete and an interrupt will be generated if
be received and transferred to the RCREG FIFO and a enable bit RCIE was set.
third byte to begin shifting into the RSR register. On the 8. Read the RCSTA register to get the ninth bit (if
clocking of the last bit of the third byte, if the RCREG enabled) and determine if any error occurred
register is still full then overrun error bit OERR during reception.
(RCSTA<1>) is set. The word in the RSR will be lost.
9. Read the 8-bit received data by reading the
The RCREG register can be read twice to retrieve the
RCREG register.
two bytes in the FIFO. Bit OERR has to be cleared in
software (by clearing bit CREN). If bit OERR is set, 10. If any error occurred, clear the error by clearing
transfers from the RSR to the RCREG are inhibited, so bit CREN.
it is essential to clear bit OERR if it is set. The 9th
TABLE 12-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION

Value on all
Value on:
POR
RESETS
8Ch PIE1 EEPIE CMIE RCIE TXIE — CCP1IE TMR2IE TMR1IE -000 0000 -000 -000
Legend: x = unknown, - = unimplemented read as '0'. Shaded cells are not used for Synchronous Master Reception.

PIC16F62X
FIGURE 12-14: SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
RB1/RX/DT PIN BIT0 BIT1 BIT2 BIT3 BIT4 BIT5 BIT6 BIT7
RB2/TX/CK PIN
WRITE TO
BIT SREN
SREN BIT
CREN BIT '0' '0'
RCIF BIT
(INTERRUPT)
READ
RXREG
Note 1: Timing diagram demonstrates Sync Master mode with bit SREN = ‘1’ and bit BRG = ‘0’.
12.5 USART Synchronous Slave Mode Steps to follow when setting up a Synchronous Slave
Transmission:
Synchronous Slave mode differs from the Master mode
in the fact that the shift clock is supplied externally at 1. Enable the synchronous slave serial port by
the RB2/TX/CK pin (instead of being supplied internally setting bits SYNC and SPEN and clearing bit
in Master mode). This allows the device to transfer or CSRC.
receive data while in SLEEP mode. Slave mode is 2. Clear bits CREN and SREN.
entered by clearing bit CSRC (TXSTA<7>). 3. If interrupts are desired, then set enable bit
TXIE.
12.5.1 USART SYNCHRONOUS SLAVE 4. If 9-bit transmission is desired, then set bit TX9.
TRANSMIT 5. Enable the transmission by setting enable bit
The operation of the Synchronous Master and Slave TXEN.
modes are identical except in the case of the SLEEP 6. If 9-bit transmission is selected, the ninth bit
mode. should be loaded in bit TX9D.
If two words are written to the TXREG and then the 7. Start transmission by loading data to the TXREG
SLEEP instruction is executed, the following will occur: register.
a) The first word will immediately transfer to the
TSR register and transmit.
b) The second word will remain in TXREG register.
c) Flag bit TXIF will not be set.
d) When the first word has been shifted out of TSR,
the TXREG register will transfer the second
word to the TSR and flag bit TXIF will now be
set.
e) If enable bit TXIE is set, the interrupt will wake
the chip from SLEEP and if the global interrupt
is enabled, the program will branch to the
interrupt vector (0004h).

PIC16F62X
12.5.2 USART SYNCHRONOUS SLAVE setting bits SYNC and SPEN and clearing bit
RECEPTION CSRC.
The operation of the Synchronous Master and Slave
RCIE.
modes is identical except in the case of the SLEEP
mode. Also, bit SREN is a don't care in Slave mode. 3. If 9-bit reception is desired, then set bit RX9.
4. To enable reception, set enable bit CREN.
If receive is enabled, by setting bit CREN, prior to the
SLEEP instruction, then a word may be received during 5. Flag bit RCIF will be set when reception is
SLEEP. On completely receiving the word, the RSR complete and an interrupt will be generated, if
register will transfer the data to the RCREG register enable bit RCIE was set.
and if enable bit RCIE bit is set, the interrupt generated 6. Read the RCSTA register to get the ninth bit (if
will wake the chip from SLEEP. If the global interrupt is enabled) and determine if any error occurred
enabled, the program will branch to the interrupt vector during reception.
(0004h). 7. Read the 8-bit received data by reading the
Steps to follow when setting up a Synchronous Slave RCREG register.
Reception: 8. If any error occurred, clear the error by clearing
bit CREN.
1. Enable the synchronous master serial port by
TABLE 12-11: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION

Value on all
Value on
POR
RESETS
Legend: x = unknown, - = unimplemented read as '0'. Shaded cells are not used for Synchronous Slave Transmission.
TABLE 12-12: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION

Value on all
Value on
POR
RESETS
Legend: x = unknown, - = unimplemented read as '0'. Shaded cells are not used for Synchronous Slave Reception.

PIC16F62X
NOTES:

PIC16F62X
13.0 DATA EEPROM MEMORY The EEPROM data memory allows byte read and write.
A byte write automatically erases the location and
The EEPROM data memory is readable and writable writes the new data (erase before write). The EEPROM
during normal operation (full VDD range). This memory data memory is rated for high erase/write cycles. The
is not directly mapped in the register file space. Instead write time is controlled by an on-chip timer. The write-
it is indirectly addressed through the Special Function time will vary with voltage and temperature as well as
Registers (SFRs). There are four SFRs used to read from chip to chip. Please refer to AC specifications for
and write this memory. These registers are: exact limits.
• EECON1 When the device is code protected, the CPU may
• EECON2 (Not a physically implemented register) continue to read and write the data EEPROM memory.
• EEDATA The device programmer can no longer access
• EEADR this memory.
EEDATA holds the 8-bit data for read/write, and Additional information on the Data EEPROM is
EEADR holds the address of the EEPROM location available in the PICmicro™ Mid-Range Reference
being accessed. PIC16F62X devices have 128 bytes of Manual, (DS33023).
data EEPROM with an address range from 0h to 7Fh.
REGISTER 13-1: EEADR REGISTER (ADDRESS: 9Bh)

R/W R/W R/W R/W R/W R/W R/W R/W
Reserved EADR6 EADR5 EADR4 EADR3 EADR2 EADR1 EADR0
bit 7 bit 0
bit 7 Unimplemented Address: Must be set to ‘0’

bit 6-0 EEADR: Specifies one of 128 locations of EEPROM Read/Write Operation
Legend:
13.1 EEADR The WREN bit, when set, will allow a write operation.
On power-up, the WREN bit is clear. The WRERR bit is
The EEADR register can address up to a maximum of set when a write operation is interrupted by a MCLR
256 bytes of data EEPROM. Only the first 128 bytes of Reset or a WDT Timeout Reset during normal
data EEPROM are implemented and only seven of the operation. In these situations, following RESET, the
eight bits in the register (EEADR<6:0>) are required. user can check the WRERR bit and rewrite the
The upper bit is address decoded. This means that this location. The data and address will be unchanged in
bit should always be '0' to ensure that the address is in the EEDATA and EEADR registers.
the 128 byte memory space. Interrupt flag bit EEIF in the PIR1 register is set when
write is complete. This bit must be cleared in software.
13.2 EECON1 AND EECON2
EECON2 is not a physical register. Reading EECON2
REGISTERS
will read all '0's. The EECON2 register is used
EECON1 is the control register with five low order bits exclusively in the Data EEPROM write sequence.
physically implemented. The upper-three bits are non-
existent and read as '0's.
Control bits RD and WR initiate read and write,
respectively. These bits cannot be cleared, only set, in
software. They are cleared in hardware at completion
of the read or write operation. The inability to clear the
WR bit in software prevents the accidental, premature
termination of a write operation.

PIC16F62X
REGISTER 13-2: EECON1 REGISTER (ADDRESS: 9Ch)
U-0 U-0 U-0 U-0 R/W-x R/W-0 R/S-0 R/S-x
— — — — WRERR WREN WR RD
bit 7 bit 0

bit 3 WRERR: EEPROM Error Flag bit
1 = A write operation is prematurely terminated (any MCLR Reset, any WDT Reset during
normal operation or BOD Reset)
0 = The write operation completed
bit 2 WREN: EEPROM Write Enable bit
1 = Allows write cycles
0 = Inhibits write to the data EEPROM
bit 1 WR: Write Control bit
1 = Initiates a write cycle. (The bit is cleared by hardware once write is complete. The WR bit
can only be set (not cleared) in software.
0 = Write cycle to the data EEPROM is complete
bit 0 RD: Read Control bit
1 = Initiates an EEPROM read (read takes one cycle. RD is cleared in hardware. The RD bit
can only be set (not cleared) in software).
0 = Does not initiate an EEPROM read
Legend:

PIC16F62X
13.3 READING THE EEPROM DATA At the completion of the write cycle, the WR bit is
MEMORY cleared in hardware and the EE Write Complete
Interrupt Flag bit (EEIF) is set. The user can either
To read a data memory location, the user must write the enable this interrupt or poll this bit. The EEIF bit in the
address to the EEADR register and then set control bit PIR1 registers must be cleared by software.
RD (EECON1<0>). The data is available, in the very
next cycle, in the EEDATA register; therefore it can be 13.5 WRITE VERIFY
read in the next instruction. EEDATA will hold this value
until another read or until it is written to by the user Depending on the application, good programming
(during a write operation). practice may dictate that the value written to the Data
EEPROM should be verified (Example 13-3) to the
desired value to be written. This should be used in
EXAMPLE 13-1: DATA EEPROM READ
applications where an EEPROM bit will be stressed
BSF STATUS, RP0 ; Bank 1 near the specification limit.
MOVLW CONFIG_ADDR ;
MOVWF EEADR ; Address to read EXAMPLE 13-3: WRITE VERIFY
BSF EECON1, RD ; EE Read
MOVF EEDATA, W ; W = EEDATA BSF STATUS, RP0 ; Bank 1
BCF STATUS, RP0 ; Bank 0 MOVF EEDATA, W
BSF EECON1, RD ; Read the
; value written
;
13.4 WRITING TO THE EEPROM DATA ; Is the value written (in W reg) and
MEMORY ; read (in EEDATA) the same?
;
To write an EEPROM data location, the user must first SUBWF EEDATA, W ;
write the address to the EEADR register and the data BCF STATUS, RP0 ; Bank0
to the EEDATA register. Then the user must follow a BTFSS STATUS, Z ; Is difference 0?
specific sequence to initiate the write for each byte. GOTO WRITE_ERR ; NO, Write error
: ; YES, Good write
: ; Continue program
EXAMPLE 13-2: DATA EEPROM WRITE 13.6 PROTECTION AGAINST

BSF STATUS, RP0 ; Bank 1 SPURIOUS WRITE
BSF EECON1, WREN ; Enable write
BCF INTCON, GIE ; Disable INTs. There are conditions when the device may not want to
Sequence
MOVLW 55h ;
write to the data EEPROM memory. To protect against
Required
MOVWF EECON2 ; Write 55h

MOVLW AAh ; spurious EEPROM writes, various mechanisms have
MOVWF EECON2 ; Write AAh been built in. On power-up, WREN is cleared. Also, the
BSF EECON1,WR ; Set WR bit
; begin write Power-up Timer (72 ms duration) prevents
BSF INTCON, GIE ; Enable INTs. EEPROM write.
The write initiate sequence, and the WREN bit together
The write will not initiate if the above sequence is not help prevent an accidental write during brown-out,
exactly followed (write 55h to EECON2, write AAh to power glitch, or software malfunction.
EECON2, then set WR bit) for each byte. We strongly
recommend that interrupts be disabled during this 13.7 DATA EEPROM OPERATION
code segment. A cycle count is executed during the DURING CODE PROTECT
required sequence. Any number that is not equal to the
required cycles to execute the required sequence will When the device is code protected, the CPU is able to
cause the data not to be written into the EEPROM. read and write unscrambled data to the Data
EEPROM.
Additionally, the WREN bit in EECON1 must be set to
enable write. This mechanism prevents accidental
writes to data EEPROM due to errant (unexpected)
code execution (i.e., lost programs). The user should
keep the WREN bit clear at all times, except when
updating EEPROM. The WREN bit is not cleared
by hardware.
After a write sequence has been initiated, clearing the
WREN bit will not affect this write cycle. The WR bit will
be inhibited from being set unless the WREN bit is set.

PIC16F62X
TABLE 13-1: REGISTERS/BITS ASSOCIATED WITH DATA EEPROM
Value on Value on all
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Power-on other
Reset RESETS
9Ah EEDATA EEPROM data register xxxx xxxx uuuu uuuu
9Bh EEADR EEPROM address register xxxx xxxx uuuu uuuu
9Ch EECON1 — — — — WRERR WREN WR RD ---- x000 ---- q000
9Dh EECON2(1) EEPROM control register 2 ---- ---- ---- ----
Legend: x = unknown, u = unchanged, - = unimplemented read as '0', q = value depends upon condition.
Shaded cells are not used by data EEPROM.
Note 1: EECON2 is not a physical register

PIC16F62X
14.0 SPECIAL FEATURES OF THE 14.1 Configuration Bits
CPU The configuration bits can be programmed (read as '0')
Special circuits to deal with the needs of real-time or left unprogrammed (read as '1') to select various
applications are what sets a microcontroller apart from device configurations. These bits are mapped in
other processors. The PIC16F62X family has a host of program memory location 2007h.
such features intended to maximize system reliability, The user will note that address 2007h is beyond
minimize cost through elimination of external the user program memory space. In fact, it belongs
components, provide power saving Operating modes to the special configuration memory space (2000h –
and offer code protection. 3FFFh), which can be accessed only during
These are: programming. See Programming Specification.
1. OSC selection
2. RESET
3. Power-on Reset (POR)
4. Power-up Timer (PWRT)
5. Oscillator Start-Up Timer (OST)
6. Brown-out Reset (BOD)
7. Interrupts
8. Watchdog Timer (WDT)
9. SLEEP
10. Code protection
11. ID Locations
12. In-circuit Serial Programming
The PIC16F62X has a Watchdog Timer which is
controlled by configuration bits. It runs off its own RC
oscillator for added reliability. There are two timers that
offer necessary delays on power-up. One is the
Oscillator Start-up Timer (OST), intended to keep the
chip in RESET until the crystal oscillator is stable. The
other is the Power-up Timer (PWRT), which provides a
fixed delay of 72 ms (nominal) on power-up only,
designed to keep the part in RESET while the power
supply stabilizes. There is also circuitry to RESET the
device if a Brown-out occurs, which provides at least a
72 ms RESET. With these three functions on-chip,
most applications need no external RESET circuitry.
The SLEEP mode is designed to offer a very low
current Power-down mode. The user can wake-up from
SLEEP through external RESET, Watchdog Timer
wake-up or through an interrupt. Several oscillator
options are also made available to allow the part to fit
the application. The ER oscillator option saves system
cost while the LP crystal option saves power. A set of
configuration bits are used to select various options.

PIC16F62X
REGISTER 14-1: CONFIGURATION WORD
CP1 CP0 CP1 CP0 — CPD LVP BODEN MCLRE FOSC2 PWRTE WDTE F0SC1 F0SC0
bit 13 bit 0
bit 13-10: CP1:CP0: Code Protection bits (2)

Code protection for 2K program memory
11 = Program memory code protection off
10 = 0400h-07FFh code protected
00 = 0000h-07FFhcode protected
Code protection for 1K program memory

bit 9: Unimplemented: Read as ‘0’
bit 8: CPD: Data Code Protection bit(3)
1 = Data memory code protection off
0 = Data memory code protected
bit 7: LVP: Low Voltage Programming Enable
1 = RB4/PGM pin has PGM function, low voltage programming enabled
0 = RB4/PGM is digital I/O, HV on MCLR must be used for programming
bit 6: BODEN: Brown-out Detect Reset Enable bit (1)
1 = BOD Reset enabled
0 = BOD Reset disabled
bit 5: MCLRE: RA5/MCLR pin function select
1 = RA5/MCLR pin function is MCLR
0 = RA5/MCLR pin function is digital Input, MCLR internally tied to VDD
bit 3: PWRTEN: Power-up Timer Enable bit (1)
1 = PWRT disabled
0 = PWRT enabled
bit 2: WDTEN: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled
bit 4, 1-0: FOSC2:FOSC0: Oscillator Selection bits(4)
111 = ER oscillator: CLKOUT function on RA6/OSC2/CLKOUT pin, Resistor on RA7/OSC1/CLKIN
110 = ER oscillator: I/O function on RA6/OSC2/CLKOUT pin, Resistor on RA7/OSC1/CLKIN
101 = INTRC oscillator: CLKOUT function on RA6/OSC2/CLKOUT pin, I/O function on RA7/OSC1/CLKIN
100 = INTRC oscillator: I/O function on RA6/OSC2/CLKOUT pin, I/O function on RA7/OSC1/CLKIN
011 = EC: I/O function on RA6/OSC2/CLKOUT pin, CLKIN on RA7/OSC1/CLKIN
010 = HS oscillator: High speed crystal/resonator on RA6/OSC2/CLKOUT and RA7/OSC1/CLKIN
001 = XT oscillator: Crystal/resonator on RA6/OSC2/CLKOUT and RA7/OSC1/CLKIN
000 = LP oscillator: Low power crystal on RA6/OSC2/CLKOUT and RA7/OSC1/CLKIN
Note 1: Enabling Brown-out Detect Reset automatically enables Power-up Timer (PWRT) regardless of the value of bit PWRTE.
Ensure the Power-up Timer is enabled anytime Brown-out Detect Reset is enabled.
2: All of the CP1:CP0 pairs have to be given the same value to enable the code protection scheme listed.
3: The entire data EEPROM will be erased when the code protection is turned off.
4: When MCLR is asserted in INTRC or ER mode, the internal clock oscillator is disabled.
Legend
-n = Value at POR 1 = bit is set 0 = bit is cleared x = bit is unknown

PIC16F62X
14.2 Oscillator Configurations TABLE 14-1: CAPACITOR SELECTION FOR
CERAMIC RESONATORS
14.2.1 OSCILLATOR TYPES Ranges Characterized:
The PIC16F62X can be operated in eight different
Mode Freq OSC1(C1) OSC2(C2)
oscillator options. The user can program three
configuration bits (FOSC2 thru FOSC0) to select one of XT 455 kHz 22 - 100 pF 22 - 100 pF
2.0 MHz 15 - 68 pF 15 - 68 pF
these eight modes: 4.0 MHz 15 - 68 pF 15 - 68 pF
• LP Low Power Crystal HS 8.0 MHz 10 - 68 pF 10 - 68 pF
16.0 MHz 10 - 22 pF 10 - 22 pF
• XT Crystal/Resonator
Note 1: Higher capacitance increases the stability of the oscilla-
• HS High Speed Crystal/Resonator tor but also increases the start-up time. These values
• ER External Resistor (2 modes) are for design guidance only. Since each resonator has
its own characteristics, the user should consult the res-
• INTRC Internal Resistor/Capacitor (2 modes) onator manufacturer for appropriate values of external
• EC External Clock In components.
14.2.2 CRYSTAL OSCILLATOR / CERAMIC TABLE 14-2: CAPACITOR SELECTION FOR

RESONATORS CRYSTAL OSCILLATOR
In XT, LP or HS modes a crystal or ceramic resonator Mode Freq OSC1(C1) OSC2(C2)
is connected to the OSC1 and OSC2 pins to establish LP 32 kHz 68 - 100 pF 68 - 100 pF
oscillation (Figure 14-1). The PIC16F62X oscillator 200 kHz 15 - 30 pF 15 - 30 pF
design requires the use of a parallel cut crystal. Use of XT 100 kHz 68 - 150 pF 150 - 200 pF
a series cut crystal may give a frequency out of the 2 MHz 15 - 30 pF 15 - 30 pF
4 MHz 15 - 30 pF 15 - 30 pF
crystal manufacturers specifications. When in XT, LP or
HS modes, the device can have an external clock HS 8 MHz 15 - 30 pF 15 - 30 pF
10 MHz 15 - 30 pF 15 - 30 pF
source to drive the OSC1 pin (Figure 14-4). 20 MHz 15 - 30 pF 15 - 30 pF
Note 1: Higher capacitance increases the stability of the oscilla-
FIGURE 14-1: CRYSTAL OPERATION tor but also increases the start-up time. These values
are for design guidance only. Rs may be required in HS
(OR CERAMIC mode as well as XT mode to avoid overdriving crystals
RESONATOR) (HS, XT OR with low drive level specification. Since each crystal
has its own characteristics, the user should consult the
LP OSC crystal manufacturer for appropriate values of external
CONFIGURATION) components.
OSC1 14.2.3 EXTERNAL CRYSTAL OSCILLATOR

C1 CIRCUIT
XTAL SLEEP Either a prepackaged oscillator can be used, or a
RF
simple oscillator circuit with TTL gates can be built.
OSC2
Prepackaged oscillators provide a wide operating
RS FOSC
NOTE 1
range and better stability. A well-designed crystal
C2
PIC16F62X oscillator will provide good performance with TTL
gates. Two types of crystal oscillator circuits can be
Note 1: A series resistor may be required for some crys-
tals. used; one with series resonance, or one with parallel
2: See Table 14-1 and Table 14-2 for recommended resonance.
values of C1 and C2.
Figure 14-2 shows implementation of a parallel
resonant oscillator circuit. The circuit is designed to use
the fundamental frequency of the crystal. The 74AS04
inverter performs the 180° phase shift that a parallel
oscillator requires. The 4.7 kΩ resistor provides the
negative feedback for stability. The 10 kΩ
potentiometers bias the 74AS04 in the linear region.
This could be used for external oscillator designs.

PIC16F62X
FIGURE 14-2: EXTERNAL PARALLEL 14.2.5 ER OSCILLATOR
RESONANT CRYSTAL
For timing insensitive applications, the ER (External
OSCILLATOR CIRCUIT Resistor) Clock mode offers additional cost savings.
+5V Only one external component, a resistor to VSS, is
TO OTHER needed to set the operating frequency of the internal
DEVICES
10K oscillator. The resistor draws a DC bias current which
4.7K 74AS04 PIC16F62X controls the oscillation frequency. In addition to the
CLKIN resistance value, the oscillator frequency will vary from
74AS04
unit to unit, and as a function of supply voltage and
temperature. Since the controlling parameter is a DC
10K
current and not a capacitance, the particular package
XTAL
type and lead frame will not have a significant effect on
the resultant frequency.
10K Figure 14-5 shows how the controlling resistor is
connected to the PIC16F62X. For REXT values below
C1 C2 10k, the oscillator operation becomes sensitive to
temperature. For very high REXT values (e.g., 1M), the
oscillator becomes sensitive to leakage and may stop
Figure 14-3 shows a series resonant oscillator circuit.
completely. Thus, we recommend keeping REXT
This circuit is also designed to use the fundamental
between 10k and 1M.
frequency of the crystal. The inverter performs a 180°
phase shift in a series resonant oscillator circuit. The
330 kΩ resistors provide the negative feedback to bias FIGURE 14-5: EXTERNAL RESISTOR
the inverters in their linear region.
FIGURE 14-3: EXTERNAL SERIES RA7/OSC1/CLKIN

RESONANT CRYSTAL
OSCILLATOR CIRCUIT
RA6/OSC2/CLKOUT
TO OTHER
330 KΩ 330 KΩ DEVICES
PIC16F62X
74AS04 74AS04 74AS04
Table 14-3 shows the relationship between the
CLKIN resistance value and the operating frequency.
0.1 PF
TABLE 14-3: RESISTANCE AND

FREQUENCY RELATIONSHIP
XTAL
Resistance Frequency
14.2.4 EXTERNAL CLOCK IN 0 10.4 MHz
For applications, where a clock is already available 1K 10 MHz
elsewhere, users may directly drive the PIC16F62X
10K 7.4 MHz
provided that this external clock source meets the
AC/DC timing requirements listed in Section 17.4. 20K 5.3 MHz
Figure 14-4 shows how an external clock circuit should 47K 3 MHz
be configured. 100K 1.6 MHz
220K 800 kHz
FIGURE 14-4: EXTERNAL CLOCK INPUT
470K 300 kHz
OPERATION (EC, HS, XT
OR LP OSC 1M 200 kHz
CONFIGURATION) The ER Oscillator mode has two options that control
the unused OSC2 pin. The first allows it to be used as
Clock From
OSC1/RA7 a general purpose I/O port. The other configures the
ext. system
PIC16F62X
pin as an output providing the FOSC signal (internal
clock divided by 4) for test or external synchronization
RA6 OSC2/RA6
purposes.

PIC16F62X
14.2.6 INTERNAL 4 MHZ OSCILLATOR 14.4 RESET
The internal RC oscillator provides a fixed 4 MHz The PIC16F62X differentiates between various kinds of
(nominal) system clock at VDD = 5V and 25°C, see RESET:
“Electrical Specifications” section for information on
a) Power-on Reset (POR)
variation over voltage and temperature.
b) MCLR Reset during normal operation
14.2.7 CLKOUT c) MCLR Reset during SLEEP
d) WDT Reset (normal operation)
The PIC16F62X can be configured to provide a clock
out signal by programming the configuration word. The e) WDT Wake-up (SLEEP)
oscillator frequency, divided by 4 can be used for test f) Brown-out Detect (BOD)
purposes or to synchronize other logic. Some registers are not affected in any RESET condi-
tion; their status is unknown on POR and unchanged in
14.3 Special Feature: Dual Speed any other RESET. Most other registers are reset to a
Oscillator Modes “RESET state” on Power-on Reset, MCLR Reset, WDT
Reset and MCLR Reset during SLEEP. They are not
A software programmable Dual Speed Oscillator mode
affected by a WDT Wake-up, since this is viewed as the
is provided when the PIC16F62X is configured in either
resumption of normal operation. TO and PD bits are set
ER or INTRC Oscillator modes. This feature allows
or cleared differently in different RESET situations as
users to dynamically toggle the oscillator speed
indicated in Table 14-5. These bits are used in software
between 4 MHz and 37 kHz. In ER mode, the 4 MHz
to determine the nature of the RESET. See Table 14-8
setting will vary depending on the value of the external
for a full description of RESET states of all registers.
resistor. Also in ER mode, the 37 kHz operation is fixed
and does not vary with resistor value. Applications that A simplified block diagram of the on-chip RESET circuit
require low current power savings, but cannot tolerate is shown in Figure 14-6.
putting the part into SLEEP, may use this mode. The MCLR Reset path has a noise filter to detect and
The OSCF bit in the PCON register is used to control ignore small pulses. See Table 17-6 for pulse width
Dual Speed mode. See Section 3.2.2.6, Register 3-4. specification.
FIGURE 14-6: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT

External
RESET
Schmitt Trigger Input

MCLR/
VPP Pin SLEEP
WDT WDT
Module Timeout
Reset
VDD rise
detect Power-on Reset
VDD
Brown-out
Detect Reset S Q
BODEN
OST/PWRT
OST
Chip_Reset
10-bit Ripple-counter
R Q
OSC1/
CLKIN
Pin
PWRT
On-chip(1)
OSC 10-bit Ripple-counter
Enable PWRT See Table 14-4 for timeout situations.
Enable OST
Note 1: This is a separate oscillator from the INTRC/ER oscillator.

PIC16F62X
14.5 Power-on Reset (POR), Power-up The Power-Up Time delay will vary from chip to chip
Timer (PWRT), Oscillator Start-up and due to VDD, temperature and process variation.
See DC parameters for details.
Timer (OST) and Brown-out Detect
(BOD) 14.5.3 OSCILLATOR START-UP TIMER
(OST)
14.5.1 POWER-ON RESET (POR)
The OST provides a 1024 oscillator cycle (from OSC1
The on-chip POR circuit holds the chip in RESET until input) delay after the PWRT delay is over. This ensures
VDD has reached a high enough level for proper that the crystal oscillator or resonator has started and
operation. To take advantage of the POR, just tie the stabilized.
MCLR pin through a resistor to VDD. This will eliminate
external RC components usually needed to create The OST timeout is invoked only for XT, LP and HS
Power-on Reset. A maximum rise time for VDD is modes and only on Power-on Reset or wake-up from
required. See Electrical Specifications for details. SLEEP.
The POR circuit does not produce an internal RESET 14.5.4 BROWN-OUT DETECT (BOD)
when VDD declines. RESET
When the device starts normal operation (exits the
The PIC16F62X members have on-chip BOD circuitry.
RESET condition), device operating parameters (volt-
A configuration bit, BODEN, can disable (if clear/
age, frequency, temperature, etc.) must be met to
programmed) or enable (if set) the BOD Reset circuitry.
ensure operation. If these conditions are not met, the
If VDD falls below VBOD for longer than TBOD, the
device must be held in RESET until the operating
brown-out situation will RESET the chip. A RESET is
conditions are met.
not guaranteed to occur if VDD falls below VBOD for
For additional information, refer to Application Note shorter than TBOD. VBOD and TBOD are defined in
AN607, “Power-up Trouble Shooting”. Table 17-1 and Table 17-6, respectively.
14.5.2 POWER-UP TIMER (PWRT) On any RESET (Power-on, Brown-out, Watchdog, etc.)
the chip will remain in RESET until VDD rises above
The PWRT provides a fixed 72 ms (nominal) timeout VBOD. The Power-up Timer will now be invoked and will
on power-up only, from POR or Brown-out Detect keep the chip in RESET an additional 72 ms.
Reset. The PWRT operates on an internal RC oscilla-
If VDD drops below VBOD while the Power-up Timer is
tor. The chip is kept in RESET as long as PWRT is
running, the chip will go back into a Brown-out Detect
active. The PWRT delay allows the VDD to rise to an
Reset and the Power-up Timer will be re-initialized.
acceptable level. A configuration bit, PWRTE can
Once VDD rises above VBOD, the Power-Up Timer will
disable (if set) or enable (if cleared or programmed) the
execute a 72 ms RESET. The Power-up Timer should
PWRT. The PWRT should always be enabled when
always be enabled when Brown-out Detect is enabled.
Brown-out Detect Reset is enabled.
Figure 14-7 shows typical Brown-out situations.
FIGURE 14-7: BROWN-OUT SITUATIONS

VDD
VBOD
≥ TBOD
INTERNAL
72 MS
RESET
VDD
VBOD
INTERNAL <72 MS
RESET 72 MS
VDD
VBOD
INTERNAL
72 MS
RESET

PIC16F62X
14.5.5 TIMEOUT SEQUENCE 14.5.6 POWER CONTROL (PCON) STATUS
REGISTER
On power-up the timeout sequence is as follows: First
PWRT timeout is invoked after POR has expired. Then The Power Control/STATUS register, PCON (address
OST is activated. The total timeout will vary based on 8Eh) has two bits.
oscillator configuration and PWRTE bit status. For
Bit0 is BOD (Brown-out). BOD is unknown on Power-
example, in ER mode with PWRTE bit erased (PWRT
on Reset. It must then be set by the user and checked
disabled), there will be no timeout at all. Figure 14-8,
on subsequent RESETS to see if BOD = 0 indicating
Figure 14-9 and Figure 14-10 depict timeout
that a brown-out has occurred. The BOD STATUS bit is
sequences.
a don’t care and is not necessarily predictable if the
Since the timeouts occur from the POR pulse, if MCLR brown-out circuit is disabled (by setting BODEN bit = 0
is kept low long enough, the timeouts will expire. Then in the Configuration word).
bringing MCLR high will begin execution immediately
Bit1 is POR (Power-on Reset). It is a ‘0’ on Power-on
(see Figure 14-9). This is useful for testing purposes or
Reset and unaffected otherwise. The user must write a
to synchronize more than one PIC16F62X device
‘1’ to this bit following a Power-on Reset. On a
operating in parallel.
subsequent RESET if POR is ‘0’, it will indicate that a
Table 14-7 shows the RESET conditions for some Power-on Reset must have occurred (VDD may have
special registers, while Table 14-8 shows the RESET gone too low).
conditions for all the registers.
TABLE 14-4: TIMEOUT IN VARIOUS SITUATIONS

Power-up Brown-out Detect Wake-up
Oscillator Configuration
PWRTE = 0 PWRTE = 1 Reset from SLEEP
XT, HS, LP 72 ms + 1024 TOSC 1024 TOSC 72 ms + 1024 TOSC 1024 TOSC
ER, INTRC, EC 72 ms — 72 ms —
TABLE 14-5: STATUS/PCON BITS AND THEIR SIGNIFICANCE

POR BOD TO PD
0 X 1 1 Power-on Reset
0 X 0 X Illegal, TO is set on POR
0 X X 0 Illegal, PD is set on POR

1 0 X X Brown-out Detect Reset
1 1 0 u WDT Reset
1 1 0 0 WDT Wake-up
1 1 u u MCLR Reset during normal operation
1 1 1 0 MCLR Reset during SLEEP

Legend: u = unchanged, x = unknown.
TABLE 14-6: SUMMARY OF REGISTERS ASSOCIATED WITH BROWN-OUT

Value on all
Value on
POR Reset
RESETS(1)
03h STATUS IRP RP1 RPO TO PD Z DC C 0001 1xxx 000q quuu

8Eh PCON — — — — OSCF Reset POR BOD ---- 1-0x ---- u-uq
Note 1: Other (non Power-up) Resets include MCLR Reset, Brown-out Detect Reset and Watchdog Timer Reset during normal opera-
tion.

PIC16F62X
TABLE 14-7: INITIALIZATION CONDITION FOR SPECIAL REGISTERS
Program STATUS PCON
Condition
Counter Register Register
Power-on Reset 000h 0001 1xxx ---- 1-0x
MCLR Reset during normal operation 000h 000u uuuu ---- 1-uu
MCLR Reset during SLEEP 000h 0001 0uuu ---- 1-uu

WDT Reset 000h 0000 uuuu ---- 1-uu
WDT Wake-up PC + 1 uuu0 0uuu ---- u-uu
Brown-out Detect Reset 000h 000x xuuu ---- 1-u0
(1)
Interrupt Wake-up from SLEEP PC + 1 uuu1 0uuu ---- u-uu
Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ‘0’.
Note 1: When the wake-up is due to an interrupt and global enable bit, GIE is set, the PC is loaded with the interrupt vector
(0004h) after execution of PC+1.
TABLE 14-8: INITIALIZATION CONDITION FOR REGISTERS

• MCLR Reset during normal • Wake-up from SLEEP through
operation interrupt
Power-on
Register Address • MCLR Reset during SLEEP • Wake-up from SLEEP through
Reset
• WDT Reset WDT timeout
• Brown-out Detect Reset (1)
W — xxxx xxxx uuuu uuuu uuuu uuuu
INDF 00h — — —
TMR0 01h xxxx xxxx uuuu uuuu uuuu uuuu
PCL 02h 0000 0000 0000 0000 PC + 1(3)
(4)
STATUS 03h 0001 1xxx 000q quuu uuuq quuu(4)
FSR 04h xxxx xxxx uuuu uuuu uuuu uuuu
PORTA 05h xxxx 0000 xxxx u000 xxxx 0000
PORTB 06h xxxx xxxx uuuu uuuu uuuu uuuu
T1CON 10h --00 0000 --uu uuuu --uu uuuu
T2CON 12h -000 0000 -000 0000 -uuu uuuu
CCP1CON 17h --00 0000 --00 0000 --uu uuuu
RCSTA 18h 0000 -00x 0000 -00x uuuu -uuu
CMCON 1Fh 0000 0000 0000 0000 uu-- uuuu
PCLATH 0Ah ---0 0000 ---0 0000 ---u uuuu
INTCON 0Bh 0000 000x 0000 000u uuuu uqqq(2)
PIR1 0Ch 0000 -000 0000 -000 -q-- ----(2,5)
OPTION 81h 1111 1111 1111 1111 uuuu uuuu
TRISA 85h 11-1 1111 11-- 1111 uu-u uuuu
TRISB 86h 1111 1111 1111 1111 uuuu uuuu
PIE1 8Ch 0000 -000 0000 -000 uuuu -uuu
PCON 8Eh ---- 1-0x ---- 1-uq(1,6) ---- --uu
TXSTA 98h 0000 -010 0000 -010 uuuu -uuu
EECON1 9Ch ---- x000 ---- q000 ---- uuuu
VRCON 9Fh 000- 0000 000- 0000 uuu- uuuu
Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ‘0’, q = value depends on condition.
Note 1: If VDD goes too low, Power-on Reset will be activated and registers will be affected differently.
2: One or more bits in INTCON, PIR1 and/or PIR2 will be affected (to cause wake-up).
3: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h).
4: See Table 14-7 for RESET value for specific condition.
5: If wake-up was due to comparator input changing, then Bit 6 = 1. All other interrupts generating a wake-up will cause Bit 6 = u.
6: If RESET was due to brown-out, then Bit 0 = 0. All other RESETS will cause Bit 0 = u.

PIC16F62X
FIGURE 14-8: TIMEOUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE
VDD
MCLR
INTERNAL POR
Tpwrt
PWRT TIMEOUT Tost
OST TIMEOUT
INTERNAL RESET
FIGURE 14-9: TIMEOUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
VDD
MCLR
INTERNAL POR
Tpwrt
PWRT TIMEOUT Tost
OST TIMEOUT
INTERNAL RESET
FIGURE 14-10: TIMEOUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD)
VDD
MCLR
INTERNAL POR
Tpwrt
PWRT TIMEOUT Tost
OST TIMEOUT
INTERNAL RESET

PIC16F62X
FIGURE 14-11: EXTERNAL POWER-ON FIGURE 14-13: EXTERNAL BROWN-OUT
RESET CIRCUIT (FOR PROTECTION CIRCUIT 2
SLOW VDD POWER-UP) VDD VDD
VDD VDD R1
Q1
D MCLR
R
R2 40k
R1 PIC16F62X
MCLR
PIC16F62X
C
Note 1: This Brown-out Circuit is less expensive, albeit
less accurate. Transistor Q1 turns off when VDD is
Note 1: External Power-on Reset circuit is required below a certain level such that:
only if VDD power-up slope is too slow. The R1
VDD x = 0.7V
diode D helps discharge the capacitor R1 + R2
quickly when VDD powers down. 2: Internal Brown-out R1Detect Reset should be
2: R < 40 kΩ is recommended to make sure disabled
Vdd when
x using this circuit.
= 0.7 V
that voltage drop across R does not violate 3: Resistors shouldR1 be+adjusted
R2 for the
characteristics of the transistor.
the device’s electrical specification.
3: R1 = 100Ω to 1 kΩ will limit any current
flowing into MCLR from external capacitor
C in the event of MCLR/VPP pin breakdown
due to Electrostatic Discharge (ESD) or
Electrical Overstress (EOS).
FIGURE 14-12: EXTERNAL BROWN-OUT

PROTECTION CIRCUIT 1
VDD VDD
33k
10k MCLR
40k PIC16F62X
Note 1: This circuit will activate RESET when VDD

goes below (Vz + 0.7V) where Vz = Zener
voltage.
2: Internal Brown-out Detect Reset circuitry
should be disabled when using this circuit.

PIC16F62X
14.6 Interrupts When an interrupt is responded to, the GIE is cleared
to disable any further interrupt, the return address is
The PIC16F62X has 10 sources of interrupt: pushed into the stack and the PC is loaded with 0004h.
• External Interrupt RB0/INT Once in the interrupt service routine the source(s) of
• TMR0 Overflow Interrupt the interrupt can be determined by polling the interrupt
flag bits. The interrupt flag bit(s) must be cleared in soft-
• PORTB Change Interrupts (pins RB7:RB4)
ware before re-enabling interrupts to avoid RB0/INT
• Comparator Interrupt recursive interrupts.
• USART Interrupt TX
For external interrupt events, such as the INT pin or
• USART Interrupt RX PORTB change interrupt, the interrupt latency will be
• CCP Interrupt three or four instruction cycles. The exact latency
• TMR1 Overflow Interrupt depends when the interrupt event occurs (Figure 14-
• TMR2 Match Interrupt 15). The latency is the same for one or two cycle
• EEPROM instructions. Once in the interrupt service routine the
source(s) of the interrupt can be determined by polling
The interrupt control register (INTCON) records the interrupt flag bits. The interrupt flag bit(s) must be
individual interrupt requests in flag bits. It also has cleared in software before re-enabling interrupts to
individual and global interrupt enable bits. avoid multiple interrupt requests. Individual interrupt
A global interrupt enable bit, GIE (INTCON<7>) flag bits are set regardless of the status of their
enables (if set) all un-masked interrupts or disables (if corresponding mask bit or the GIE bit.
cleared) all interrupts. Individual interrupts can be Note 1: Individual interrupt flag bits are set
disabled through their corresponding enable bits in regardless of the status of their
INTCON register. GIE is cleared on RESET. corresponding mask bit or the GIE bit.
The “return from interrupt” instruction, RETFIE, exits 2: When an instruction that clears the GIE
interrupt routine as well as sets the GIE bit, which re- bit is executed, any interrupts that were
enable RB0/INT interrupts. pending for execution in the next cycle
The INT pin interrupt, the RB port change interrupt and are ignored. The CPU will execute a NOP
the TMR0 overflow interrupt flags are contained in the in the cycle immediately following the
INTCON register. instruction which clears the GIE bit. The
The peripheral interrupt flag is contained in the special interrupts which were ignored are still
register PIR1. The corresponding interrupt enable bit is pending to be serviced when the GIE bit
contained in special registers PIE1. is set again.
FIGURE 14-14: INTERRUPT LOGIC
TMR1IF T0IF Wake-up (If in SLEEP mode)

TMR1IE T0IE
TMR2IF INTF
TMR2IE INTE
CCP1IF RBIF
CCP1IE Interrupt to CPU
RBIE
CMIF
CMIE PEIE
TXIF
TXIE
RCIF
RCIE GIE
EEIF
EEIE

PIC16F62X
14.6.1 RB0/INT INTERRUPT 14.6.2 TMR0 INTERRUPT
External interrupt on RB0/INT pin is edge triggered: An overflow (FFh → 00h) in the TMR0 register will
either rising if INTEDG bit (OPTION<6>) is set, or set the T0IF (INTCON<2>) bit. The interrupt can
falling, if INTEDG bit is clear. When a valid edge be enabled/disabled by setting/clearing T0IE
appears on the RB0/INT pin, the INTF bit (INTCON<5>) bit. For operation of the Timer0 module,
(INTCON<1>) is set. This interrupt can be disabled by see Section 6.0.
clearing the INTE control bit (INTCON<4>). The INTF
bit must be cleared in software in the interrupt service 14.6.3 PORTB INTERRUPT
routine before re-enabling this interrupt. The RB0/INT
An input change on PORTB <7:4> sets the RBIF
interrupt can wake-up the processor from SLEEP, if the
(INTCON<0>) bit. The interrupt can be enabled/
INTE bit was set prior to going into SLEEP. The status
disabled by setting/clearing the RBIE (INTCON<4>)
of the GIE bit decides whether or not the processor
bit. For operation of PORTB (Section 5.2).
branches to the interrupt vector following wake-up. See
Section 14.9 for details on SLEEP, and Figure 14-17 Note: If a change on the I/O pin should occur
for timing of wake-up from SLEEP through RB0/INT when the read operation is being executed
interrupt. (start of the Q2 cycle), then the RBIF inter-
rupt flag may not get set.
14.6.4 COMPARATOR INTERRUPT

See Section 9.6 for complete description of comparator
interrupts.
FIGURE 14-15: INT PIN INTERRUPT TIMING

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
(3)
CLKOUT
(4)
INT pin
(1)
(1) (5)
INTF flag Interrupt Latency (2)
(INTCON<1>)
GIE bit
(INTCON<7>)
INSTRUCTION FLOW
PC PC PC+1 PC+1 0004h 0005h
Instruction
Fetched Inst (PC) Inst (PC+1) — Inst (0004h) Inst (0005h)
Instruction Dummy Cycle Dummy Cycle Inst (0004h)

Executed Inst (PC-1) Inst (PC)
Note 1: INTF flag is sampled here (every Q1).

2: Asynchronous interrupt latency = 3-4 Tcy. Synchronous latency = 3 Tcy, where Tcy = instruction cycle time. Latency
is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.
3: CLKOUT is available in ER and INTRC Oscillator mode.
4: For minimum width of INT pulse, refer to AC specs.
5: INTF is enabled to be set anytime during the Q4-Q1 cycles.

PIC16F62X
TABLE 14-9: SUMMARY OF INTERRUPT REGISTERS
Value on all
Value on
POR Reset
RESETS(1)
0Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
Note 1: Other (non Power-up) Resets include MCLR Reset, Brown-out Detect Reset and Watchdog Timer Reset during normal
operation.
14.7 Context Saving During Interrupts 14.8 Watchdog Timer (WDT)

During an interrupt, only the return PC value is saved The Watchdog Timer is a free running on-chip RC
on the stack. Typically, users may wish to save key oscillator which does not require any external compo-
registers during an interrupt (e.g., W register and nents. This RC oscillator is separate from the ER
STATUS register). This will have to be implemented in oscillator of the CLKIN pin. That means that the WDT
software. will run, even if the clock on the OSC1 and OSC2 pins
Example 14-2 stores and restores the STATUS and W of the device has been stopped, for example, by
registers. The user register, W_TEMP, must be defined execution of a SLEEP instruction. During normal
in a common memory location (i.e., W_TEMP is operation, a WDT timeout generates a device RESET.
defined at 0x70 in Bank 0 and is therefore, accessible If the device is in SLEEP mode, a WDT timeout causes
at 0xF0, 0x17 and 0xIFD). The Example 14-2: the device to wake-up and continue with normal opera-
tion. The WDT can be permanently disabled by
• Stores the W register programming the configuration bit WDTE as clear
• Stores the STATUS register (Section 14.1).
• Executes the ISR code
• Restores the STATUS (and bank select bit 14.8.1 WDT PERIOD
register) The WDT has a nominal timeout period of 18 ms (with
• Restores the W register no prescaler). The timeout periods vary with tempera-
ture, VDD and process variations from part to part (see
EXAMPLE 14-2: SAVING THE STATUS DC specs). If longer timeout periods are desired, a
AND W REGISTERS IN postscaler with a division ratio of up to 1:128 can be
RAM assigned to the WDT under software control by writing
to the OPTION register. Thus, timeout periods up to 2.3
MOVWF W_TEMP ;copy W to temp register, seconds can be realized.
could be in either bank
The CLRWDT and SLEEP instructions clear the WDT
SWAPF STATUS,W ;swap status to be saved
into W and the postscaler, if assigned to the WDT, and prevent
BCF STATUS,RP0 ;change to bank 0 regardless it from timing out and generating a device RESET.
of current bank
The TO bit in the STATUS register will be cleared upon
MOVWF STATUS_TEMP ;save status to bank 0 a Watchdog Timer timeout.
register
:
14.8.2 WDT PROGRAMMING
: (ISR)
CONSIDERATIONS
:
SWAPF STATUS_TEMP,W ;swap STATUS_TEMP register It should also be taken in account that under worst case
into W, sets bank to origi- conditions (VDD = Min., Temperature = Max., max.
nal WDT prescaler), it may take several seconds before a
state
WDT timeout occurs.
MOVWF STATUS ;move W into STATUS register
SWAPF W_TEMP,F ;swap W_TEMP
SWAPF W_TEMP,W ;swap W_TEMP into W

PIC16F62X
FIGURE 14-16: WATCHDOG TIMER BLOCK DIAGRAM
From TMR0 Clock Source

(Figure 6-1)
0
M WDT POSTSCALER/
U TMR0 PRESCALER
Watchdog
Timer 1X
8
8 to 1 MUX PS<2:0>
PSA 3
WDT
Enable Bit
To TMR0
(Figure 6-1)
0 1 PSA
MUX
WDT
Timeout
Note 1: T0SE, T0CS, PSA, PS0-PS2 are bits in the OPTION register.
TABLE 14-10: SUMMARY OF WATCHDOG TIMER REGISTERS

Value on all
Value on
POR Reset
RESETS
2007h Config. LVP BODEN MCLRE FOSC2 PWRTE WDTE FOSC1 FOSC0 uuuu uuuu uuuu uuuu
bits
81h OPTION RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
_
Legend: = Unimplemented location, read as “0”, + = Reserved for future use
Note 1: Shaded cells are not used by the Watchdog Timer.
14.9 Power-Down Mode (SLEEP) For lowest current consumption in this mode, all I/O
pins should be either at VDD, or VSS, with no external
The Power-down mode is entered by executing a circuitry drawing current from the I/O pin and the com-
SLEEP instruction. parators, and VREF should be disabled. I/O pins that
If enabled, the Watchdog Timer will be cleared but are hi-impedance inputs should be pulled high or low
keeps running, the PD bit in the STATUS register is externally to avoid switching currents caused by float-
cleared, the TO bit is set, and the oscillator driver is ing inputs. The T0CKI input should also be at VDD or
turned off. The I/O ports maintain the status they had, VSS for lowest current consumption. The contribution
before SLEEP was executed (driving high, low, or hi- from on-chip pull-ups on PORTB should be considered.
impedance). The MCLR pin must be at a logic high level (VIHMC).
Note: It should be noted that a RESET generated
by a WDT timeout does not drive MCLR
pin low.

PIC16F62X
14.9.1 WAKE-UP FROM SLEEP corresponding interrupt enable bit must be set
(enabled). Wake-up is regardless of the state of the
The device can wake-up from SLEEP through one of GIE bit. If the GIE bit is clear (disabled), the device con-
the following events: tinues execution at the instruction after the SLEEP
1. External RESET input on MCLR pin instruction. If the GIE bit is set (enabled), the device
2. Watchdog Timer Wake-up (if WDT was enabled) executes the instruction after the SLEEP instruction
3. Interrupt from RB0/INT pin, RB Port change, or and then branches to the interrupt address (0004h). In
the Peripheral Interrupt (Comparator). cases where the execution of the instruction following
SLEEP is not desirable, the user should have an NOP
The first event will cause a device RESET. The two after the SLEEP instruction.
latter events are considered a continuation of program
execution. The TO and PD bits in the STATUS register Note: If the global interrupts are disabled (GIE is
can be used to determine the cause of device RESET. cleared), but any interrupt source has both
PD bit, which is set on power-up is cleared when its interrupt enable bit and the correspond-
SLEEP is invoked. TO bit is cleared if WDT Wake-up ing interrupt flag bits set, the device will
occurred. immediately wake-up from SLEEP. The
SLEEP instruction is completely executed.
When the SLEEP instruction is being executed, the
next instruction (PC + 1) is pre-fetched. For the device The WDT is cleared when the device wakes-up from
to wake-up through an interrupt event, the SLEEP, regardless of the source of wake-up.
FIGURE 14-17: WAKE-UP FROM SLEEP THROUGH INTERRUPT
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
CLKOUT(4) Tost(2)
INT pin
INTF flag
(INTCON<1>) Interrupt Latency
(Note 2)
GIE bit
(INTCON<7>) Processor in
SLEEP
INSTRUCTION FLOW
PC PC PC+1 PC+2 PC+2 PC + 2 0004h 0005h
Instruction Inst(PC + 1) Inst(PC + 2) Inst(0004h) Inst(0005h)
Fetched Inst(PC) = SLEEP
Instruction SLEEP Inst(PC + 1) Dummy cycle Dummy cycle
Executed Inst(PC - 1) Inst(0004h)
Note 1: XT, HS or LP Oscillator mode assumed.

2: TOST = 1024TOSC (drawing not to scale). Approximately 1 µs delay will be there for ER Osc mode.
3: GIE = '1' assumed. In this case after wake- up, the processor jumps to the interrupt routine. If GIE = '0', execution will continue
in-line.
4: CLKOUT is not available in these Osc modes, but shown here for timing reference.
14.10 Code Protection 14.11 User ID Locations

If the code protection bit(s) have not been Four memory locations (2000h-2003h) are designated
programmed, the on-chip program memory can be as user ID locations where the user can store
read out for verification purposes. checksum or other code-identification numbers. These
locations are not accessible during normal execution
Note: The entire data EEPROM and FLASH
but are readable and writable during program/verify.
program memory will be erased when the
Only the Least Significant 4 bits of the user ID locations
code protection is turned off. The INTRC
are used.
calibration data is not erased.

PIC16F62X
14.12 In-Circuit Serial Programming 14.13 Low Voltage Programming
The PIC16F62X microcontrollers can be serially The LVP bit of the configuration word, enables the low
programmed while in the end application circuit. This is voltage programming. This mode allows the microcon-
simply done with two lines for clock and data, and three troller to be programmed via ICSP using only a 5V
other lines for power, ground, and the programming source. This mode removes the requirement of VIHH to
voltage. This allows customers to manufacture boards be placed on the MCLR pin. The LVP bit is normally
with unprogrammed devices, and then program the erased to '1', which enables the low voltage program-
microcontroller just before shipping the product. This ming. In this mode, the RB4/PGM pin is dedicated to
also allows the most recent firmware, or a custom the programming function and ceases to be a general
firmware to be programmed. purpose I/O pin. The device will enter Programming
The device is placed into a Program/Verify mode by mode when a '1' is placed on the RB4/PGM pin. The
holding the RB6 and RB7 pins low while raising the HV Programming mode is still available by placing VIHH
MCLR (VPP) pin from VIL to VIHH (see programming on the MCLR pin.
specification). RB6 becomes the programming clock Note 1: While in this mode, the RB4 pin can no
and RB7 becomes the programming data. Both RB6 longer be used as a general purpose I/O
and RB7 are Schmitt Trigger inputs in this mode. pin.
After RESET, to place the device into Programming/ 2: VDD must be 5.0V +10% during erase/
Verify mode, the program counter (PC) is at location program operations while in low voltage
00h. A 6-bit command is then supplied to the device. Programming mode.
Depending on the command, 14 bits of program data
are then supplied to or from the device, depending if If Low voltage Programming mode is not used, the LVP
the command was a load or a read. For complete bit can be programmed to a '0', and RB4/PGM
details of serial programming, please refer to the becomes a digital I/O pin. To program the device, VIHH
Programming Specifications. must be placed onto MCLR during programming. The
LVP bit may only be programmed when programming
A typical in-circuit serial programming connection is is entered with VIHH on MCLR. The LVP bit cannot be
shown in Figure 14-18. programmed when programming is entered with RB4/
PGM.
FIGURE 14-18: TYPICAL IN-CIRCUIT
It should be noted, that once the LVP bit is programmed
SERIAL PROGRAMMING
to 0, High voltage Programming mode can be used to
CONNECTION program the device.
To Normal
Connections
External
Connector PIC16F62X
Signals
+5V VDD
0V VSS
VPP RA5/MCLR/VPP
CLK RB6/PGC
Data I/O RB7/PGD
VDD
To Normal
Connections

PIC16F62X
15.0 INSTRUCTION SET SUMMARY The instruction set is highly orthogonal and is grouped
into three basic categories:
Each PIC16F62X instruction is a 14-bit word divided
• Byte-oriented operations
into an OPCODE which specifies the instruction type
and one or more operands which further specify the • Bit-oriented operations
operation of the instruction. The PIC16F62X instruction • Literal and control operations
set summary in Table 15-2 lists byte-oriented, bit- All instructions are executed within one single
oriented, and literal and control operations. Table 15-1 instruction cycle, unless a conditional test is true or the
shows the opcode field descriptions. program counter is changed as a result of an
For byte-oriented instructions, 'f' represents a file instruction. In this case, the execution takes two
register designator and 'd' represents a destination instruction cycles with the second cycle executed as a
designator. The file register designator specifies which NOP. One instruction cycle consists of four oscillator
file register is to be used by the instruction. periods. Thus, for an oscillator frequency of 4 MHz, the
normal instruction execution time is 1 µs. If a
The destination designator specifies where the result of
conditional test is true or the program counter is
the operation is to be placed. If 'd' is zero, the result is
changed as a result of an instruction, the instruction
placed in the W register. If 'd' is one, the result is placed
execution time is 2 µs.
in the file register specified in the instruction.
Table 15-2 lists the instructions recognized by the
For bit-oriented instructions, 'b' represents a bit field
MPASM™ assembler.
designator which selects the number of the bit affected
by the operation, while 'f' represents the number of the Figure 15-1 shows the three general formats that the
file in which the bit is located. instructions can have.
For literal and control operations, 'k' represents an Note 1: Any unused opcode is reserved. Use of
eight or eleven bit constant or literal value. any reserved opcode may cause unex-
pected operation.
TABLE 15-1: OPCODE FIELD 2: To maintain upward compatibility with
DESCRIPTIONS future PICmicro® products, do not use the
Field Description OPTION and TRIS instructions.
f Register file address (0x00 to 0x7F) All examples use the following format to represent a
W Working register (accumulator) hexadecimal number:
b Bit address within an 8-bit file register 0xhh
k Literal field, constant data or label
where h signifies a hexadecimal digit.
x Don't care location (= 0 or 1)
The assembler will generate code with x = 0. It is the
recommended form of use for compatibility with all FIGURE 15-1: GENERAL FORMAT FOR
Microchip software tools. INSTRUCTIONS
d Destination select; d = 0: store result in W,
Byte-oriented file register operations
d = 1: store result in file register f.
13 8 7 6 0
Default is d = 1
OPCODE d f (FILE #)
label Label name
TOS Top of Stack d = 0 for destination W
PC Program Counter d = 1 for destination f
f = 7-bit file register address
PCLA Program Counter High Latch
TH Bit-oriented file register operations
GIE Global Interrupt Enable bit 13 10 9 76 0
WDT Watchdog Timer/Counter OPCODE b (BIT #) f (FILE #)
TO Timeout bit
b = 3-bit bit address
PD Power-down bit
f = 7-bit file register address
dest Destination either the W register or the specified regis-
ter file location Literal and control operations
[ ] Options General
( ) Contents 13 8 7 0
→ Assigned to OPCODE k (literal)
<> Register bit field k = 8-bit immediate value
∈ In the set of CALL and GOTO instructions only
italics User defined term (font is courier) 13 11 10 0
OPCODE k (literal)
k = 11-bit immediate value

PIC16F62X
TABLE 15-2: PIC16F62X INSTRUCTION SET
14-Bit Opcode
Mnemonic, Status
Description Cycles Notes
Operands Affected
MSb LSb
BYTE-ORIENTED FILE REGISTER OPERATIONS

ADDWF f, d Add W and f 1 00 0111 dfff ffff C,DC,Z 1,2
ANDWF f, d AND W with f 1 00 0101 dfff ffff Z 1,2
CLRF f Clear f 1 00 0001 lfff ffff Z 2
CLRW — Clear W 1 00 0001 0000 0011 Z
COMF f, d Complement f 1 00 1001 dfff ffff Z 1,2
DECF f, d Decrement f 1 00 0011 dfff ffff Z 1,2
DECFSZ f, d Decrement f, Skip if 0 1(2) 00 1011 dfff ffff 1,2,3
INCF f, d Increment f 1 00 1010 dfff ffff Z 1,2
INCFSZ f, d Increment f, Skip if 0 1(2) 00 1111 dfff ffff 1,2,3
IORWF f, d Inclusive OR W with f 1 00 0100 dfff ffff Z 1,2
MOVF f, d Move f 1 00 1000 dfff ffff Z 1,2
MOVWF f Move W to f 1 00 0000 lfff ffff
NOP — No Operation 1 00 0000 0xx0 0000
RLF f, d Rotate Left f through Carry 1 00 1101 dfff ffff C 1,2
RRF f, d Rotate Right f through Carry 1 00 1100 dfff ffff C 1,2
SUBWF f, d Subtract W from f 1 00 0010 dfff ffff C,DC,Z 1,2
SWAPF f, d Swap nibbles in f 1 00 1110 dfff ffff 1,2
XORWF f, d Exclusive OR W with f 1 00 0110 dfff ffff Z 1,2
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF f, b Bit Clear f 1 01 00bb bfff ffff 1,2
BSF f, b Bit Set f 1 01 01bb bfff ffff 1,2
BTFSC f, b Bit Test f, Skip if Clear 1(2) 01 10bb bfff ffff 3
BTFSS f, b Bit Test f, Skip if Set 1(2) 01 11bb bfff ffff 3
LITERAL AND CONTROL OPERATIONS
ADDLW k Add literal and W 1 11 111x kkkk kkkk C,DC,Z
ANDLW k AND literal with W 1 11 1001 kkkk kkkk Z
CALL k Call subroutine 2 10 0kkk kkkk kkkk
CLRWDT — Clear Watchdog Timer 1 00 0000 0110 0100 TO,PD
GOTO k Go to address 2 10 1kkk kkkk kkkk
IORLW k Inclusive OR literal with W 1 11 1000 kkkk kkkk Z
MOVLW k Move literal to W 1 11 00xx kkkk kkkk
RETFIE — Return from interrupt 2 00 0000 0000 1001
RETLW k Return with literal in W 2 11 01xx kkkk kkkk
RETURN — Return from Subroutine 2 00 0000 0000 1000
SLEEP — Go into Standby mode 1 00 0000 0110 0011 TO,PD
SUBLW k Subtract W from literal 1 11 110x kkkk kkkk C,DC,Z
XORLW k Exclusive OR literal with W 1 11 1010 kkkk kkkk Z
Note 1: When an I/O register is modified as a function of itself ( e.g., MOVF PORTB, 1), the value used will be that value present on the
pins themselves. For example, if the data latch is '1' for a pin configured as input and is driven low by an external device, the data
will be written back with a '0'.
2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned to the
Timer0 Module.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed
as a NOP.

PIC16F62X
15.1 Instruction Descriptions
ADDLW Add Literal and W ANDLW AND Literal with W
Syntax: [ label ] ADDLW k Syntax: [ label ] ANDLW k
Operands: 0 ≤ k ≤ 255 Operands: 0 ≤ k ≤ 255
Operation: (W) + k → (W) Operation: (W) .AND. (k) → (W)
Status Affected: C, DC, Z Status Affected: Z
Encoding: 11 111x kkkk kkkk Encoding: 11 1001 kkkk kkkk
Description: The contents of the W register Description: The contents of W register are
are added to the eight bit literal AND’ed with the eight bit literal
'k' and the result is placed in the 'k'. The result is placed in the W
W register. register.
Words: 1 Words: 1
Cycles: 1 Cycles: 1
Example ADDLW 0x15 Example ANDLW 0x5F
Before Instruction Before Instruction
W = 0x10 W = 0xA3
After Instruction After Instruction
W = 0x25 W = 0x03
ANDWF AND W with f

ADDWF Add W and f
Syntax: [ label ] ANDWF f,d
Syntax: [ label ] ADDWF f,d Operands: 0 ≤ f ≤ 127
Operands: 0 ≤ f ≤ 127 d ∈ [0,1]
d ∈ [0,1] Operation: (W) .AND. (f) → (dest)
Operation: (W) + (f) → (dest) Status Affected: Z
Status Affected: C, DC, Z Encoding: 00 0101 dfff ffff
Encoding: 00 0111 dfff ffff Description: AND the W register with register
Description: Add the contents of the W regis- 'f'. If 'd' is 0 the result is stored in
ter with register 'f'. If 'd' is 0 the the W register. If 'd' is 1 the
result is stored in the W register. result is stored back in register
If 'd' is 1 the result is stored back 'f'.
in register 'f'. Words: 1
Words: 1 Cycles: 1
Cycles: 1 Example ANDWF REG1, 1
Example ADDWF REG1, 0 Before Instruction
Before Instruction W = 0x17
W = 0x17 REG1 = 0xC2
REG1 = 0xC2 After Instruction
After Instruction W = 0x17
W = 0xD9 REG1 = 0x02
REG1 = 0xC2
Z = 0
C = 0
DC = 0

PIC16F62X
BCF Bit Clear f BTFSC Bit Test f, Skip if Clear

Syntax: [ label ] BCF f,b Syntax: [ label ] BTFSC f,b
Operands: 0 ≤ f ≤ 127 Operands: 0 ≤ f ≤ 127
0≤b≤7 0≤b≤7
Operation: 0 → (f<b>) Operation: skip if (f<b>) = 0
Status Affected: None Status Affected: None
Encoding: 01 00bb bfff ffff Encoding: 01 10bb bfff ffff
Description: Bit 'b' in register 'f' is cleared. Description: If bit 'b' in register 'f' is '0' then the
Words: 1 next instruction is skipped.
If bit 'b' is '0' then the next
Cycles: 1 instruction fetched during the
Example BCF REG1, 7 current instruction execution is
discarded, and a NOP is executed
Before Instruction
instead, making this a two-cycle
REG1 = 0xC7
instruction.
After Instruction
REG1 = 0x47 Words: 1
Cycles: 1(2)
Example HERE BTFSC REG1
BSF Bit Set f FALSE GOTO PROCESS_CODE
TRUE •
Syntax: [ label ] BSF f,b
•
Operands: 0 ≤ f ≤ 127 •
0≤b≤7 Before Instruction
Operation: 1 → (f<b>) PC = address HERE
Status Affected: None After Instruction
if REG<1> = 0,
Encoding: 01 01bb bfff ffff PC = address TRUE
Description: Bit 'b' in register 'f' is set. if REG<1>=1,
PC = address FALSE
Words: 1
Cycles: 1
Example BSF REG1, 7
Before Instruction
REG1 = 0x0A
After Instruction
REG1 = 0x8A

PIC16F62X
BTFSS Bit Test f, Skip if Set CALL Call Subroutine

Syntax: [ label ] BTFSS f,b Syntax: [ label ] CALL k
Operands: 0 ≤ f ≤ 127 Operands: 0 ≤ k ≤ 2047
0≤b<7 Operation: (PC)+ 1→ TOS,
Operation: skip if (f<b>) = 1 k → PC<10:0>,
Status Affected: None (PCLATH<4:3>) → PC<12:11>
Encoding: 01 11bb bfff ffff Status Affected: None
Description: If bit 'b' in register 'f' is '1' then the Encoding: 10 0kkk kkkk kkkk
next instruction is skipped. Description: Call Subroutine. First, return
If bit 'b' is '1', then the next address (PC+1) is pushed onto
instruction fetched during the the stack. The eleven bit
current instruction execution, is immediate address is loaded
discarded and a NOP is executed into PC bits <10:0>. The upper
instead, making this a two-cycle bits of the PC are loaded from
instruction. PCLATH. CALL is a two-cycle
Words: 1 instruction.
Cycles: 1(2) Words: 1
Example HERE BTFSS REG1 Cycles: 2

FALSE GOTO PROCESS_CODE Example HERE CALL THERE
TRUE •
• Before Instruction
• PC = Address HERE
After Instruction
Before Instruction
PC = Address THERE
PC = address HERE
TOS = Address HERE+1
After Instruction
if FLAG<1> = 0,
PC = address FALSE
if FLAG<1> = 1, CLRF Clear f
PC = address TRUE Syntax: [ label ] CLRF f
Operands: 0 ≤ f ≤ 127
Operation: 00h → (f)
1→Z
Status Affected: Z
Encoding: 00 0001 1fff ffff
Description: The contents of register 'f' are
cleared and the Z bit is set.
Words: 1
Cycles: 1
Example CLRF REG1
Before Instruction
REG1 = 0x5A
After Instruction
REG1 = 0x00
Z = 1

PIC16F62X
CLRW Clear W COMF Complement f

Syntax: [ label ] CLRW Syntax: [ label ] COMF f,d
Operands: None Operands: 0 ≤ f ≤ 127
Operation: 00h → (W) d ∈ [0,1]
1→Z Operation: (f) → (dest)
Status Affected: Z Status Affected: Z
Encoding: 00 0001 0000 0011 Encoding: 00 1001 dfff ffff
Description: W register is cleared. Zero bit Description: The contents of register 'f' are
(Z) is set. complemented. If 'd' is 0 the
Words: 1 result is stored in W. If 'd' is 1 the
result is stored back in register
Cycles: 1 'f'.
Example CLRW Words: 1
Before Instruction Cycles: 1
W = 0x5A
After Instruction Example COMF REG1, 0
W = 0x00 Before Instruction
Z = 1 REG1 = 0x13
After Instruction
REG1 = 0x13
W = 0xEC
CLRWDT Clear Watchdog Timer DECF Decrement f

Syntax: [ label ] CLRWDT Syntax: [ label ] DECF f,d
Operands: None Operands: 0 ≤ f ≤ 127
Operation: 00h → WDT d ∈ [0,1]
0 → WDT prescaler, Operation: (f) - 1 → (dest)
1 → TO
1 → PD Status Affected: Z
Status Affected: TO, PD Encoding: 00 0011 dfff ffff
Encoding: 00 0000 0110 0100 Description: Decrement register 'f'. If 'd' is 0

the result is stored in the W
Description: CLRWDT instruction resets the register. If 'd' is 1 the result is
Watchdog Timer. It also resets stored back in register 'f'.
the prescaler of the WDT.
STATUS bits TO and PD are set. Words: 1
Words: 1 Cycles: 1
Cycles: 1 Example DECF CNT, 1
Example CLRWDT Before Instruction

CNT = 0x01
Before Instruction Z = 0
WDT counter = ? After Instruction
After Instruction CNT = 0x00
WDT counter = 0x00 Z = 1
WDT prescaler = 0
TO = 1
PD = 1

PIC16F62X
DECFSZ Decrement f, Skip if 0 GOTO Unconditional Branch

Syntax: [ label ] DECFSZ f,d Syntax: [ label ] GOTO k
d ∈ [0,1]
Operation: k → PC<10:0>
Operation: (f) - 1 → (dest); skip if result = PCLATH<4:3> → PC<12:11>
0
Status Affected: None
Encoding: 10 1kkk kkkk kkkk
Encoding: 00 1011 dfff ffff
Description: GOTO is an unconditional
Description: The contents of register 'f' are branch. The eleven bit
decremented. If 'd' is 0 the result immediate value is loaded into
is placed in the W register. If 'd' PC bits <10:0>. The upper bits
is 1 the result is placed back in of PC are loaded from
register 'f'. PCLATH<4:3>. GOTO is a two-
If the result is 0, the next cycle instruction.
instruction, which is already
fetched, is discarded. A NOP is Words: 1
executed instead making it a Cycles: 2
two-cycle instruction.
Example GOTO THERE
Words: 1
After Instruction
Cycles: 1(2) PC = Address THERE
Example HERE DECFSZ REG1, 1
GOTO LOOP
CONTINUE •
•
•
Before Instruction
PC = address HERE
After Instruction
REG1 = REG1 - 1
if REG1 = 0,
PC = address CONTINUE
if REG1 ≠ 0,
PC = address HERE+1

PIC16F62X
INCF Increment f INCFSZ Increment f, Skip if 0

Syntax: [ label ] INCF f,d Syntax: [ label ] INCFSZ f,d
d ∈ [0,1] d ∈ [0,1]
Operation: (f) + 1 → (dest) Operation: (f) + 1 → (dest), skip if result = 0
Status Affected: Z Status Affected: None
Encoding: 00 1010 dfff ffff Encoding: 00 1111 dfff ffff
Description: The contents of register 'f' are Description: The contents of register 'f' are
incremented. If 'd' is 0 the result incremented. If 'd' is 0 the result
is placed in the W register. If 'd' is placed in the W register. If 'd'
is 1 the result is placed back in is 1 the result is placed back in
register 'f'. register 'f'.
Words: 1 If the result is 0, the next
instruction, which is already
Cycles: 1 fetched, is discarded. A NOP is
Example INCF REG1, 1 executed instead making it a
Before Instruction
REG1 = 0xFF Words: 1
Z = 0 Cycles: 1(2)
After Instruction
REG1 = 0x00 Example HERE INCFSZ REG1, 1
GOTO LOOP
Z = 1 CONTINUE •
•
•
Before Instruction
PC = address HERE
After Instruction
REG1 = REG1 + 1
if CNT = 0,
PC = address CONTINUE
if REG1≠ 0,
PC = address HERE +1

PIC16F62X
IORLW Inclusive OR Literal with W MOVLW Move Literal to W

Syntax: [ label ] IORLW k Syntax: [ label ] MOVLW k
Operands: 0 ≤ k ≤ 255 Operands: 0 ≤ k ≤ 255
Operation: (W) .OR. k → (W) Operation: k → (W)
Status Affected: Z Status Affected: None
Encoding: 11 1000 kkkk kkkk Encoding: 11 00xx kkkk kkkk
Description: The contents of the W register is Description: The eight bit literal 'k' is loaded
OR’ed with the eight bit literal 'k'. into W register. The don’t cares
The result is placed in the W will assemble as 0’s.
register. Words: 1
Words: 1 Cycles: 1
Cycles: 1 Example MOVLW 0x5A
Example IORLW 0x35
After Instruction
Before Instruction W = 0x5A
W = 0x9A
After Instruction
W = 0xBF
Z = 0
IORWF Inclusive OR W with f MOVF Move f

Syntax: [ label ] IORWF f,d Syntax: [ label ] MOVF f,d
d ∈ [0,1] d ∈ [0,1]
Operation: (W) .OR. (f) → (dest) Operation: (f) → (dest)
Status Affected: Z Status Affected: Z
Description: Inclusive OR the W register with Description: The contents of register f is
register 'f'. If 'd' is 0 the result is moved to a destination depen-
placed in the W register. If 'd' is dent upon the status of d. If d =
1 the result is placed back in 0, destination is W register. If d
register 'f'. = 1, the destination is file regis-
Words: 1 ter f itself. d = 1 is useful to test
a file register since status flag Z
Cycles: 1 is affected.
Example IORWF REG1, 0
Words: 1
Before Instruction Cycles: 1
REG1 = 0x13
W = 0x91 Example MOVF REG1, 0
After Instruction After Instruction
REG1 = 0x13 W = value in REG1 register
W = 0x93 Z = 1
Z = 1

PIC16F62X
MOVWF Move W to f OPTION Load Option Register

Syntax: [ label ] MOVWF f Syntax: [ label ] OPTION
Operands: 0 ≤ f ≤ 127 Operands: None
Operation: (W) → (f) Operation: (W) → OPTION
Status Affected: None Status Affected: None

Encoding: 00 0000 0110 0010
Encoding: 00 0000 1fff ffff
Description: The contents of the W register are
Description: Move data from W register to
loaded in the OPTION register.
register 'f'.
This instruction is supported for
Words: 1 code compatibility with PIC16C5X
Cycles: 1 products. Since OPTION is a
readable/writable register, the
Example MOVWF REG1
user can directly address it. Using
Before Instruction only register instruction such as
REG1 = 0xFF MOVWF.
W = 0x4F Words: 1
After Instruction
Cycles: 1
REG1 = 0x4F
W = 0x4F Example
To maintain upward compatibil-
ity with future PICmicro® prod-
ucts, do not use this
instruction.
NOP No Operation RETFIE Return from Interrupt
Syntax: [ label ] NOP Syntax: [ label ] RETFIE
Operands: None Operands: None
Operation: No operation Operation: TOS → PC,

1 → GIE
Encoding: 00 0000 0xx0 0000
Encoding: 00 0000 0000 1001
Description: No operation.
Description: Return from Interrupt. Stack is
Words: 1 POPed and Top of Stack (TOS)
Cycles: 1 is loaded in the PC. Interrupts
Example NOP are enabled by setting Global
Interrupt Enable bit, GIE
(INTCON<7>). This is a two-
cycle instruction.
Words: 1
Cycles: 2
Example RETFIE
After Interrupt
PC = TOS
GIE = 1

PIC16F62X
RETLW Return with Literal in W RLF Rotate Left f through Carry

Syntax: [ label ] RETLW k Syntax: [ label ] RLF f,d
Operands: 0 ≤ k ≤ 255 Operands: 0 ≤ f ≤ 127
Operation: k → (W); d ∈ [0,1]
TOS → PC Operation: See description below
Status Affected: None Status Affected: C
Encoding: 11 01xx kkkk kkkk Encoding: 00 1101 dfff ffff
Description: The W register is loaded with Description: The contents of register 'f' are
the eight bit literal 'k'. The rotated one bit to the left through
program counter is loaded from the Carry Flag. If 'd' is 0 the result
the top of the stack (the return is placed in the W register. If 'd' is
address). This is a two-cycle 1 the result is stored back in
instruction. register 'f'.
Words: 1 C REGISTER F
Cycles: 2
Words: 1
Example CALL TABLE;W contains table
;offset value Cycles: 1
• ;W now has table Example RLF REG1, 0
value
• Before Instruction
TABLE
• REG1 = 1110 0110
ADDWF PC ;W = offset C = 0
RETLW k1 ;Begin table After Instruction
RETLW k2 ; REG1 = 1110 0110
• W = 1100 1100
• C = 1
•
RETLW kn ; End of table
Before Instruction
W = 0x07
After Instruction
W = value of k8
RETURN Return from Subroutine

Syntax: [ label ] RETURN
Operands: None
Operation: TOS → PC
Encoding: 00 0000 0000 1000
Description: Return from subroutine. The
stack is POPed and the top of
the stack (TOS) is loaded into
the program counter. This is a
Words: 1
Cycles: 2
Example RETURN
After Interrupt
PC = TOS

PIC16F62X
RRF Rotate Right f through Carry SUBLW Subtract W from Literal

Syntax: [ label ] RRF f,d Syntax: [ label ] SUBLW k
d ∈ [0,1] Operation: k - (W) → (W)
Operation: See description below Status C, DC, Z
Status Affected: C Affected:
Encoding: 00 1100 dfff ffff Encoding: 11 110x kkkk kkkk
Description: The contents of register 'f' are Description: The W register is subtracted (2’s
rotated one bit to the right complement method) from the eight
through the Carry Flag. If 'd' is 0 bit literal 'k'. The result is placed in
the result is placed in the W the W register.
register. If 'd' is 1 the result is Words: 1
placed back in register 'f'.
Cycles: 1
C REGISTER F
Example 1: SUBLW 0x02
Words: 1 Before Instruction

Cycles: 1 W = 1
C = ?
Example RRF REG1, 0
After Instruction
Before Instruction
REG1 = 1110 0110 W = 1
C = 0 C = 1; result is positive
After Instruction Example 2: Before Instruction
REG1 = 1110 0110
W = 2
W = 0111 0011
C = ?
C = 0
After Instruction
W = 0
SLEEP C = 1; result is zero
Syntax: [ label ] SLEEP Example 3: Before Instruction
Operands: None W = 3
C = ?
Operation: 00h → WDT,
0 → WDT prescaler, After Instruction
1 → TO, W = 0xFF
0 → PD C = 0; result is negative
Status Affected: TO, PD
Encoding: 00 0000 0110 0011
Description: The power-down STATUS bit,
PD is cleared. Timeout
STATUS bit, TO is set.
Watchdog Timer and its
prescaler are cleared.
The processor is put into
SLEEP mode with the
oscillator stopped. See
Section 14.9 for more details.
Words: 1
Cycles: 1
Example: SLEEP

PIC16F62X
SUBWF Subtract W from f SWAPF Swap Nibbles in f

Syntax: [ label ] SUBWF f,d Syntax: [ label ] SWAPF f,d
d ∈ [0,1] d ∈ [0,1]
Operation: (f) - (W) → (dest) Operation: (f<3:0>) → (dest<7:4>),
Status C, DC, Z (f<7:4>) → (dest<3:0>)
Affected: Status Affected: None
Description: Subtract (2’s complement method) Description: The upper and lower nibbles of
W register from register 'f'. If 'd' is 0 register 'f' are exchanged. If 'd' is
the result is stored in the W register. 0 the result is placed in W
If 'd' is 1 the result is stored back in register. If 'd' is 1 the result is
register 'f'. placed in register 'f'.
Words: 1 Words: 1
Cycles: 1 Cycles: 1
Example 1: SUBWF REG1, 1 Example SWAPF REG1, 0
Before Instruction Before Instruction
REG1 = 3 REG1 = 0xA5
W = 2 After Instruction
C = ?
REG1 = 0xA5
After Instruction W = 0x5A
REG1 = 1
W = 2
C = 1; result is positive TRIS Load TRIS Register
Z = DC = 1 Syntax: [ label ] TRIS f
Example 2: Before Instruction Operands: 5≤f≤7
REG1 = 2 Operation: (W) → TRIS register f;
W = 2
C = ?
Encoding: 00 0000 0110 0fff
After Instruction
Description: The instruction is supported for
REG1 = 0 code compatibility with the
W = 2 PIC16C5X products. Since TRIS
C = 1; result is zero registers are readable and
Z = DC = 1 writable, the user can directly
Example 3: Before Instruction address them.
REG1 = 1 Words: 1
W = 2 Cycles: 1
C = ? Example
After Instruction To maintain upward
REG1 = 0xFF compatibility with future
W = 2 PICmicro® products, do not
C = 0; result is negative use this instruction.
Z = DC = 0

PIC16F62X
XORLW Exclusive OR Literal with W XORWF Exclusive OR W with f

Syntax: [ label ] XORLW k Syntax: [ label ] XORWF f,d
Operands: 0 ≤ k ≤ 255 Operands: 0 ≤ f ≤ 127
Operation: (W) .XOR. k → (W) d ∈ [0,1]
Status Affected: Z Operation: (W) .XOR. (f) → (dest)
Encoding: 11 1010 kkkk kkkk Status Affected: Z
Description: The contents of the W register Encoding: 00 0110 dfff ffff

are XOR’ed with the eight bit Description: Exclusive OR the contents of the
literal 'k'. The result is placed in W register with register 'f'. If 'd' is
the W register. 0 the result is stored in the W
Words: 1 register. If 'd' is 1 the result is
stored back in register 'f'.
Cycles: 1
Words: 1
Example: XORLW 0xAF
Cycles: 1
Before Instruction
Example XORWF REG1, 1
W = 0xB5
Before Instruction
After Instruction
REG1 = 0xAF
W = 0x1A W = 0xB5
After Instruction
REG1 = 0x1A
W = 0xB5

Device#
16.0 DEVELOPMENT SUPPORT 16.1 MPLAB Integrated Development
Environment Software
The PICmicro® microcontrollers are supported with a
full range of hardware and software development tools: The MPLAB IDE software brings an ease of software
• Integrated Development Environment development previously unseen in the 8/16-bit micro-
controller market. The MPLAB IDE is a Windows®
- MPLAB® IDE Software
based application that contains:
• Assemblers/Compilers/Linkers
• An interface to debugging tools
- MPASMTM Assembler
- simulator
- MPLAB C17 and MPLAB C18 C Compilers
- programmer (sold separately)
- MPLINKTM Object Linker/
MPLIBTM Object Librarian - emulator (sold separately)
- MPLAB C30 C Compiler - in-circuit debugger (sold separately)
- MPLAB ASM30 Assembler/Linker/Library • A full-featured editor with color coded context
• Simulators • A multiple project manager
- MPLAB SIM Software Simulator • Customizable data windows with direct edit of
contents
- MPLAB dsPIC30 Software Simulator
• High level source code debugging
• Emulators
• Mouse over variable inspection
- MPLAB ICE 2000 In-Circuit Emulator
• Extensive on-line help
- MPLAB ICE 4000 In-Circuit Emulator
• In-Circuit Debugger The MPLAB IDE allows you to:
- MPLAB ICD 2 • Edit your source files (either assembly or C)
• Device Programmers • One touch assemble (or compile) and download
- PRO MATE® II Universal Device Programmer to PICmicro emulator and simulator tools
(automatically updates all project information)
- PICSTART® Plus Development Programmer
• Debug using:
• Low Cost Demonstration Boards
- source files (assembly or C)
- PICDEMTM 1 Demonstration Board
- absolute listing file (mixed assembly and C)
- PICDEM.netTM Demonstration Board
- machine code
- PICDEM 2 Plus Demonstration Board
- PICDEM 3 Demonstration Board MPLAB IDE supports multiple debugging tools in a
single development paradigm, from the cost effective
- PICDEM 17 Demonstration Board
simulators, through low cost in-circuit debuggers, to
- PICDEM 18R Demonstration Board full-featured emulators. This eliminates the learning
- PICDEM LIN Demonstration Board curve when upgrading to tools with increasing flexibility
- PICDEM USB Demonstration Board and power.
• Evaluation Kits
- KEELOQ®
16.2 MPASM Assembler
- PICDEM MSC The MPASM assembler is a full-featured, universal
- microID® macro assembler for all PICmicro MCUs.
- CAN The MPASM assembler generates relocatable object
- PowerSmart® files for the MPLINK object linker, Intel® standard HEX
- Analog files, MAP files to detail memory usage and symbol
reference, absolute LST files that contains source lines
and generated machine code and COFF files for
debugging.
The MPASM assembler features include:
• Integration into MPLAB IDE projects
• User defined macros to streamline assembly code
• Conditional assembly for multi-purpose source files
• Directives that allow complete control over the
assembly process

Device#
16.3 MPLAB C17 and MPLAB C18 16.6 MPLAB ASM30 Assembler, Linker,
C Compilers and Librarian
The MPLAB C17 and MPLAB C18 Code Development MPLAB ASM30 assembler produces relocatable
Systems are complete ANSI C compilers for machine code from symbolic assembly language for
Microchip’s PIC17CXXX and PIC18CXXX family of dsPIC30F devices. MPLAB C30 compiler uses the
microcontrollers. These compilers provide powerful assembler to produce it’s object file. The assembler
integration capabilities, superior code optimization and generates relocatable object files that can then be
ease of use not found with other compilers. archived or linked with other relocatable object files and
For easy source level debugging, the compilers provide archives to create an executable file. Notable features
symbol information that is optimized to the MPLAB IDE of the assembler include:
debugger. • Support for the entire dsPIC30F instruction set
• Support for fixed-point and floating-point data
16.4 MPLINK Object Linker/ • Command line interface
MPLIB Object Librarian • Rich directive set
The MPLINK object linker combines relocatable • Flexible macro language
objects created by the MPASM assembler and the • MPLAB IDE compatibility
MPLAB C17 and MPLAB C18 C compilers. It can link
relocatable objects from pre-compiled libraries, using 16.7 MPLAB SIM Software Simulator
directives from a linker script.
The MPLAB SIM software simulator allows code
The MPLIB object librarian manages the creation and development in a PC hosted environment by simulating
modification of library files of pre-compiled code. When the PICmicro series microcontrollers on an instruction
a routine from a library is called from a source file, only level. On any given instruction, the data areas can be
the modules that contain that routine will be linked in examined or modified and stimuli can be applied from
with the application. This allows large libraries to be a file, or user defined key press, to any pin. The
used efficiently in many different applications. execution can be performed in Single-Step, Execute
The object linker/library features include: Until Break, or Trace mode.
• Efficient linking of single libraries instead of many The MPLAB SIM simulator fully supports symbolic
smaller files debugging using the MPLAB C17 and MPLAB C18
• Enhanced code maintainability by grouping C Compilers, as well as the MPASM assembler. The
related modules together software simulator offers the flexibility to develop and
• Flexible creation of libraries with easy module debug code outside of the laboratory environment,
listing, replacement, deletion and extraction making it an excellent, economical software
development tool.
16.5 MPLAB C30 C Compiler
16.8 MPLAB SIM30 Software Simulator
The MPLAB C30 C compiler is a full-featured, ANSI
compliant, optimizing compiler that translates standard The MPLAB SIM30 software simulator allows code
ANSI C programs into dsPIC30F assembly language development in a PC hosted environment by simulating
source. The compiler also supports many command- the dsPIC30F series microcontrollers on an instruction
line options and language extensions to take full level. On any given instruction, the data areas can be
advantage of the dsPIC30F device hardware capabili- examined or modified and stimuli can be applied from
ties, and afford fine control of the compiler code a file, or user defined key press, to any of the pins.
generator. The MPLAB SIM30 simulator fully supports symbolic
MPLAB C30 is distributed with a complete ANSI C debugging using the MPLAB C30 C Compiler and
standard library. All library functions have been MPLAB ASM30 assembler. The simulator runs in either
validated and conform to the ANSI C library standard. a Command Line mode for automated tasks, or from
The library includes functions for string manipulation, MPLAB IDE. This high speed simulator is designed to
dynamic memory allocation, data conversion, time- debug, analyze and optimize time intensive DSP
keeping, and math functions (trigonometric, routines.
exponential and hyperbolic). The compiler provides
symbolic information for high level source debugging
with the MPLAB IDE.

Device#
16.9 MPLAB ICE 2000 16.11 MPLAB ICD 2 In-Circuit Debugger
High Performance Universal Microchip’s In-Circuit Debugger, MPLAB ICD 2, is a
In-Circuit Emulator powerful, low cost, run-time development tool,
The MPLAB ICE 2000 universal in-circuit emulator is connecting to the host PC via an RS-232 or high speed
intended to provide the product development engineer USB interface. This tool is based on the FLASH
with a complete microcontroller design tool set for PICmicro MCUs and can be used to develop for these
PICmicro microcontrollers. Software control of the and other PICmicro microcontrollers. The MPLAB
MPLAB ICE 2000 in-circuit emulator is advanced by ICD 2 utilizes the in-circuit debugging capability built
the MPLAB Integrated Development Environment, into the FLASH devices. This feature, along with
which allows editing, building, downloading and source Microchip’s In-Circuit Serial ProgrammingTM (ICSPTM)
debugging from a single environment. protocol, offers cost effective in-circuit FLASH
debugging from the graphical user interface of the
The MPLAB ICE 2000 is a full-featured emulator MPLAB Integrated Development Environment. This
system with enhanced trace, trigger and data monitor- enables a designer to develop and debug source code
ing features. Interchangeable processor modules allow by setting breakpoints, single-stepping and watching
the system to be easily reconfigured for emulation of variables, CPU status and peripheral registers.
different processors. The universal architecture of the Running at full speed enables testing hardware and
MPLAB ICE in-circuit emulator allows expansion to applications in real-time. MPLAB ICD 2 also serves as
support new PICmicro microcontrollers. a development programmer for selected PICmicro
The MPLAB ICE 2000 in-circuit emulator system has devices.
been designed as a real-time emulation system with
advanced features that are typically found on more 16.12 PRO MATE II Universal Device
expensive development tools. The PC platform and Programmer
Microsoft® Windows 32-bit operating system were
chosen to best make these features available in a The PRO MATE II is a universal, CE compliant device
simple, unified application. programmer with programmable voltage verification at
VDDMIN and VDDMAX for maximum reliability. It features
16.10 MPLAB ICE 4000 an LCD display for instructions and error messages
and a modular detachable socket assembly to support
High Performance Universal
various package types. In Stand-Alone mode, the
In-Circuit Emulator PRO MATE II device programmer can read, verify, and
The MPLAB ICE 4000 universal in-circuit emulator is program PICmicro devices without a PC connection. It
intended to provide the product development engineer can also set code protection in this mode.
with a complete microcontroller design tool set for high-
end PICmicro microcontrollers. Software control of the 16.13 PICSTART Plus Development
MPLAB ICE in-circuit emulator is provided by the Programmer
MPLAB Integrated Development Environment, which
The PICSTART Plus development programmer is an
allows editing, building, downloading and source
easy-to-use, low cost, prototype programmer. It
debugging from a single environment.
connects to the PC via a COM (RS-232) port. MPLAB
The MPLAB ICD 4000 is a premium emulator system, Integrated Development Environment software makes
providing the features of MPLAB ICE 2000, but with using the programmer simple and efficient. The
increased emulation memory and high speed perfor- PICSTART Plus development programmer supports
mance for dsPIC30F and PIC18XXXX devices. Its most PICmicro devices up to 40 pins. Larger pin count
advanced emulator features include complex triggering devices, such as the PIC16C92X and PIC17C76X,
and timing, up to 2 Mb of emulation memory, and the may be supported with an adapter socket. The
ability to view variables in real-time. PICSTART Plus development programmer is CE
The MPLAB ICE 4000 in-circuit emulator system has compliant.
been designed as a real-time emulation system with
advanced features that are typically found on more
expensive development tools. The PC platform and
Microsoft Windows 32-bit operating system were
chosen to best make these features available in a
simple, unified application.

Device#
16.14 PICDEM 1 PICmicro 16.16 PICDEM 2 Plus
Demonstration Board Demonstration Board
The PICDEM 1 demonstration board demonstrates the The PICDEM 2 Plus demonstration board supports
capabilities of the PIC16C5X (PIC16C54 to many 18-, 28-, and 40-pin microcontrollers, including
PIC16C58A), PIC16C61, PIC16C62X, PIC16C71, PIC16F87X and PIC18FXX2 devices. All the
PIC16C8X, PIC17C42, PIC17C43 and PIC17C44. All necessary hardware and software is included to run the
necessary hardware and software is included to run demonstration programs. The sample microcontrollers
basic demo programs. The sample microcontrollers provided with the PICDEM 2 demonstration board can
provided with the PICDEM 1 demonstration board can be programmed with a PRO MATE II device program-
be programmed with a PRO MATE II device programmer, PICSTART Plus development programmer, or
mer, or a PICSTART Plus development programmer. MPLAB ICD 2 with a Universal Programmer Adapter.
The PICDEM 1 demonstration board can be connected The MPLAB ICD 2 and MPLAB ICE in-circuit emulators
to the MPLAB ICE in-circuit emulator for testing. A may also be used with the PICDEM 2 demonstration
prototype area extends the circuitry for additional board to test firmware. A prototype area extends the
application components. Features include an RS-232 circuitry for additional application components. Some
interface, a potentiometer for simulated analog input, of the features include an RS-232 interface, a 2 x 16
push button switches and eight LEDs. LCD display, a piezo speaker, an on-board temperature
sensor, four LEDs, and sample PIC18F452 and
16.15 PICDEM.net Internet/Ethernet PIC16F877 FLASH microcontrollers.
Demonstration Board
16.17 PICDEM 3 PIC16C92X
The PICDEM.net demonstration board is an Internet/ Demonstration Board
Ethernet demonstration board using the PIC18F452
microcontroller and TCP/IP firmware. The board The PICDEM 3 demonstration board supports the
supports any 40-pin DIP device that conforms to the PIC16C923 and PIC16C924 in the PLCC package. All
standard pinout used by the PIC16F877 or the necessary hardware and software is included to run
PIC18C452. This kit features a user friendly TCP/IP the demonstration programs.
stack, web server with HTML, a 24L256 Serial
EEPROM for Xmodem download to web pages into 16.18 PICDEM 17 Demonstration Board
Serial EEPROM, ICSP/MPLAB ICD 2 interface
The PICDEM 17 demonstration board is an evaluation
connector, an Ethernet interface, RS-232 interface,
board that demonstrates the capabilities of several
and a 16 x 2 LCD display. Also included is the book
Microchip microcontrollers, including PIC17C752,
and CD-ROM “TCP/IP Lean, Web Servers for
PIC17C756A, PIC17C762 and PIC17C766. A
Embedded Systems,” by Jeremy Bentham
programmed sample is included. The PRO MATE II
device programmer, or the PICSTART Plus develop-
ment programmer, can be used to reprogram the
device for user tailored application development. The
PICDEM 17 demonstration board supports program
download and execution from external on-board
FLASH memory. A generous prototype area is
available for user hardware expansion.

Device#
16.19 PICDEM 18R PIC18C601/801 16.21 PICDEM USB PIC16C7X5
Demonstration Board Demonstration Board
The PICDEM 18R demonstration board serves to assist The PICDEM USB Demonstration Board shows off the
development of the PIC18C601/801 family of Microchip capabilities of the PIC16C745 and PIC16C765 USB
microcontrollers. It provides hardware implementation microcontrollers. This board provides the basis for
of both 8-bit Multiplexed/De-multiplexed and 16-bit future USB products.
Memory modes. The board includes 2 Mb external
FLASH memory and 128 Kb SRAM memory, as well as 16.22 Evaluation and
serial EEPROM, allowing access to the wide range of Programming Tools
memory types supported by the PIC18C601/801.
In addition to the PICDEM series of circuits, Microchip
16.20 PICDEM LIN PIC16C43X has a line of evaluation kits and demonstration software
Demonstration Board for these products.
• KEELOQ evaluation and programming tools for
The powerful LIN hardware and software kit includes a Microchip’s HCS Secure Data Products
series of boards and three PICmicro microcontrollers.
• CAN developers kit for automotive network
The small footprint PIC16C432 and PIC16C433 are
applications
used as slaves in the LIN communication and feature
on-board LIN transceivers. A PIC16F874 FLASH • Analog design boards and filter design software
microcontroller serves as the master. All three • PowerSmart battery charging evaluation/
microcontrollers are programmed with firmware to calibration kits
provide LIN bus communication. • IrDA® development kit
• microID development and RFLabTM development
software
• SEEVAL® designer kit for memory evaluation and
endurance calculations
• PICDEM MSC demo boards for Switching mode
power supply, high power IR driver, delta sigma
ADC, and flow rate sensor
Check the Microchip web page and the latest Product
Line Card for the complete list of demonstration and
evaluation kits.

PIC14000
PI18CX01
dsPIC30F
PIC16C5X
PIC16C6X
PIC16C7X
PIC16C8X
PIC17C4X
PIC16F62X
PIC16C43X
PIC16C7X5
PIC16F8XX
PIC12FXXX
PIC16C7XX
PIC16C9XX
PIC17C7XX
PIC18CXX2
PIC18FXXX
PIC12CXXX
PIC16CXXX
MPLAB Integrated
TABLE 16-1:
Development Environment
MPLAB C17 C Compiler
DS40300C-page 126

Device#

MPASM Assembler/
MPLINK Object Linker
Software Tools
MPLAB ASM30
Assembler/Linker/Librarian
MPLAB ICE 2000

In-Circuit Emulator **
MPLAB ICE 4000

In-Circuit Emulator
MPLAB ICD 2 In-Circuit

Debugger * *
PICSTART Plus Entry Level

Development Programmer **
PRO MATE II
Universal Device Programmer **
Preliminary
Programmers Debugger Emulators
†
DEVELOPMENT TOOLS FROM MICROCHIP
PICDEM 1 Demonstration Board

PICDEM.net Demonstration
Board
PICDEM 2 Plus Demonstration † †

Board
PICDEM 3 Demonstration Board

PICDEM 14A Demonstration
Board
PICDEM 17 Demonstration
Board
PICDEM 18R Demonstration

Board
Demo Boards and Eval Kits

PICDEM LIN Demonstration
Board
PICDEM USB Demonstration

Board
* Contact the Microchip web site at www.microchip.com for information on how to use the MPLAB ICD In-Circuit Debugger (DV164001) with PIC16C62, 63, 64, 65, 72, 73, 74, 76, 77.
** Contact Microchip Technology Inc. for availability date.
†
Development tool is available on select devices.
 2003 Microchip Technology Inc.

PIC16F62X
17.0 ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings†
Ambient temperature under bias................................................................................................................. -40 to +125°C
Storage temperature .............................................................................................................................. -65°C to +150°C
Voltage on VDD with respect to VSS ............................................................................................................ -0.3 to +6.5V
Voltage on MCLR and RA4 with respect to VSS ............................................................................................-0.3 to +14V
Voltage on all other pins with respect to VSS ....................................................................................-0.3V to VDD + 0.3V
Total power dissipation(1) .....................................................................................................................................800 mW
Maximum current out of VSS pin ...........................................................................................................................300 mA
Maximum current into VDD pin ..............................................................................................................................250 mA
Input clamp current, IIK (VI < 0 or VI > VDD)..................................................................................................................... ± 20 mA
Output clamp current, IOK (Vo < 0 or Vo >VDD)............................................................................................................... ± 20 mA
Maximum output current sunk by any I/O pin..........................................................................................................25 mA
Maximum output current sourced by any I/O pin ....................................................................................................25 mA
Maximum current sunk by PORTA and PORTB....................................................................................................200 mA
Maximum current sourced by PORTA and PORTB ..............................................................................................200 mA
Note 1: Power dissipation is calculated as follows: PDIS = VDD x {IDD - ∑ IOH} + ∑ {(VDD-VOH) x IOH} + ∑(VOl x IOL)
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
Note: Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80 mA, may cause latchup. Thus,
a series resistor of 50-100 Ω should be used when applying a “low” level to the MCLR pin rather than pulling
this pin directly to VSS

PIC16F62X
FIGURE 17-1: PIC16F62X VOLTAGE-FREQUENCY GRAPH, 0°C ≤ TA ≤ +70°C
6.0
5.5
5.0
4.5
VDD
(VOLTS)
4.0
3.5
3.0
2.5
0 4 10 20 25
FREQUENCY (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
FIGURE 17-2: PIC16F62X VOLTAGE-FREQUENCY GRAPH, -40°C ≤ TA < 0°C, +70°C < TA ≤ 85°C
6.0
5.5
5.0
4.5
VDD
(VOLTS)
4.0
3.5
3.0
2.5
2.0
0 4 10 20 25
FREQUENCY (MHz)

PIC16F62X
FIGURE 17-3: PIC16LF62X VOLTAGE-FREQUENCY GRAPH, 0°C ≤ TA ≤ +70°C
6.0
5.5
5.0
4.5
VDD
(VOLTS)
4.0
3.5
3.0
2.5
2.0
0 4 10 20 25
FREQUENCY (MHz)
FIGURE 17-4: PIC16LF62X VOLTAGE-FREQUENCY GRAPH,

-40°C ≤ TA < 0°C, +70°C < TA ≤ 85°C
6.0
5.5
5.0
4.5
VDD
(VOLTS)
4.0
3.5
3.0
2.5
2.0
0 4 10 20 25
FREQUENCY (MHz)

PIC16F62X
17.1 DC Characteristics: PIC16F62X-04 (Commercial, Industrial, Extended)

PIC16F62X-20 (Commercial, Industrial, Extended)
PIC16LF62X-04 (Commercial, Industrial)
Standard Operating Conditions (unless otherwise stated)
PIC16LF62X-04
Operating temperature -40°C ≤ Ta ≤ +85°C for industrial and
(Commercial, Industrial)
0°C ≤ Ta ≤ +70°C for commercial

PIC16F62X-04
PIC16F62X-20
0°C ≤ Ta ≤ +70°C for commercial and
(Commercial, Industrial, Extended)
-40°C ≤ Ta ≤ +125°C for extended
Param
Sym Characteristic/Device Min Typ† Max Units Conditions
No.
VDD Supply Voltage
D001 PIC16LF62X 2.0 — 5.5 V
D001 PIC16F62X 3.0 — 5.5 V
D002 VDR RAM Data Retention — 1.5 — V Device in SLEEP mode*
Voltage(1)
D003 VPOR VDD Start Voltage — VSS — V See section on Power-on Reset
to ensure Power-on Reset for details
D004 SVDD VDD Rise Rate 0.05 — — V/ms See section on Power-on Reset
to ensure Power-on Reset for details*
D005 VBOD Brown-out Detect Voltage 3.65 4.0 4.35 V BODEN configuration bit is set
3.65 — 4.4 V BODEN configuration bit is set,
Extended
IDD Supply Current(2), (5)
D010 PIC16LF62X — 0.30 0.6 mA Fosc = 4.0 MHz, VDD = 2.0(5)
— 1.10 2.0 mA FOSC = 4.0 MHz, VDD = 5.5*
D013 — 4.0 7.0 mA Fosc = 20.0 MHz, VDD = 5.5
— 3.80 6.0 mA Fosc = 20.0 MHz, VDD = 4.5*
— — 2.0 mA FOSC = 10.0 MHz, VDD = 3.0(6)
— 20 30 µA FOSC = 32 kHz, VDD = 2.0
D010 PIC16F62X — 0.60 0.7 mA Fosc = 4.0 MHz, VDD = 3.0
— 1.10 2.0 mA Fosc = 4.0 MHz, VDD = 5.5*
D013 — 4.0 7.0 mA FOSC = 20.0 MHz, VDD = 5.5
— 3.80 6.0 mA FOSC = 20.0 MHz, VDD = 4.5*
— — 2.0 mA FOSC = 10.0 MHz, VDD = 3.0*(6)
D014 20 30 µA FOSC = 32 kHz, VDD = 3.0*
Legend: Rows with standard voltage device data only are shaded for improved readability.
* These parameters are characterized but not tested.
† Data in “Typ” column is at 5.0V, 25°C, unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and
switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current con-
sumption.
The test conditions for all IDD measurements in active Operation mode are:
OSC1 = external square wave, from rail to rail; all I/O pins tri-stated, pulled to VDD,
MCLR = VDD; WDT enabled/disabled as specified.
3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with
the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD or VSS.
4: The ∆ current is the additional current consumed when this peripheral is enabled. This current should be added to the
base IDD or IPD measurement.
5: For RC osc configuration, current through REXT is not included. The current through the resistor can be estimated by the
formula Ir = VDD/2REXT (mA) with REXT in kΩ.
6: Commercial temperature only.

PIC16F62X
17.1 DC Characteristics: PIC16F62X-04 (Commercial, Industrial, Extended)
PIC16F62X-20 (Commercial, Industrial, Extended)
PIC16LF62X-04 (Commercial, Industrial)
PIC16LF62X-04
(Commercial, Industrial)
0°C ≤ Ta ≤ +70°C for commercial

PIC16F62X-04
PIC16F62X-20
0°C ≤ Ta ≤ +70°C for commercial and
(Commercial, Industrial, Extended)
-40°C ≤ Ta ≤ +125°C for extended
Param
Sym Characteristic/Device Min Typ† Max Units Conditions
No.
IPD Power Down Current*(2), (3)

D020 PIC16LF62X — 0.20 2.0 µA VDD = 2.0
— 0.20 2.2 µA VDD = 5.5
D020 PIC16F62X — 0.20 2.2 µA VDD = 3.0
— 0.20 5.0 µA VDD = 4.5*
— 0.20 9.0 µA VDD = 5.5
— 2.70 15.0 µA VDD = 5.5 Extended
∆IWDT WDT Current(4) — 6.0 15 µA VDD = 3.0V
∆IBOD Brown-out Detect Current(4) — 75 125 µA BOD enabled, VDD = 5.0V
D023 ∆ICOMP Comparator Current for each — 30 50 µA VDD = 3.0V
Comparator(4)
∆IVREF VREF Current(4) — 135 µA VDD = 3.0V
∆IWDT WDT Current(4) — 6.0 20 µA VDD = 4.0V, Commercial,
Industrial
25 µA VDD = 4.0V, Extended
D023 ∆IBOD Brown-out Detect Current(4) — 75 125 µA BOD enabled, VDD = 5.0V
∆ICOMP Comparator Current for each — 30 50 µA VDD = 4.0V
Comparator(4)
∆IVREF VREF Current(4) — 135 µA VDD = 4.0V
Legend: Rows with standard voltage device data only are shaded for improved readability.
† Data in “Typ” column is at 5.0V, 25°C, unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and
switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current con-
sumption.
The test conditions for all IDD measurements in active Operation mode are:
OSC1 = external square wave, from rail to rail; all I/O pins tri-stated, pulled to VDD,
MCLR = VDD; WDT enabled/disabled as specified.
3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with
the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD or VSS.
4: The ∆ current is the additional current consumed when this peripheral is enabled. This current should be added to the
base IDD or IPD measurement.
5: For RC osc configuration, current through REXT is not included. The current through the resistor can be estimated by the
formula Ir = VDD/2REXT (mA) with REXT in kΩ.

PIC16F62X
17.2 DC Characteristics: PIC16F62X (Commercial, Industrial, Extended)
PIC16LF62X (Commercial, Industrial)

Operating temperature -40°C ≤ TA ≤ +85°C for industrial and
DC CHARACTERISTICS 0°C ≤ TA ≤ +70°C for commercial and
-40°C ≤ TA ≤ +125°C for extended
Operating voltage VDD range as described in DC spec Table 17-1 and Table 17-2
Param.
Sym Characteristic/Device Min Typ† Max Unit Conditions
No.
VIL Input Low Voltage
I/O ports
D030 with TTL buffer VSS — 0.8 V VDD = 4.5V to 5.5V
0.15 VDD V otherwise
D031 with Schmitt Trigger input VSS 0.2 VDD V
D032 MCLR, RA4/T0CKI,OSC1 VSS — 0.2 VDD V (Note1)
(in ER mode)
D033 OSC1 (in XT and HS) VSS — 0.3 VDD V
OSC1 (in LP) VSS — 0.6 VDD - 1.0 V
VIH Input High Voltage
I/O ports
D040 with TTL buffer 2.0V — VDD V VDD = 4.5V to 5.5V
.25 VDD + 0.8V VDD V otherwise
D041 with Schmitt Trigger input 0.8 VDD — VDD V
D042 MCLR RA4/T0CKI 0.8 VDD — VDD V
D043 OSC1 (XT, HS and LP) 0.7 VDD — VDD V
D043A OSC1 (in ER mode) 0.9 VDD V (Note1)
D070 IPURB PORTB weak pull-up 50 200 400 µA VDD = 5.0V, VPIN = VSS
current
IIL Input Leakage Current(2), (3)
I/O ports (Except PORTA) ±1.0 µA VSS ≤ VPIN ≤ VDD, pin at hi-impedance
D060 PORTA — — ±0.5 µA VSS ≤ VPIN ≤ VDD, pin at hi-impedance
D061 RA4/T0CKI — — ±1.0 µA VSS ≤ VPIN ≤ VDD
D063 OSC1, MCLR — — ±5.0 µA VSS ≤ VPIN ≤ VDD, XT, HS and LP osc
configuration
VOL Output Low Voltage
D080 I/O ports — — 0.6 V IOL=8.5 mA, VDD=4.5V, -40° to +85°C
— — 0.6 V IOL=7.0 mA, VDD=4.5V, +125°C
D083 OSC2/CLKOUT (ER only) — — 0.6 V IOL=1.6 mA, VDD=4.5V, -40° to +85°C
— — 0.6 V IOL=1.2 mA, VDD=4.5V, +125°C
VOH Output High Voltage(3)
D090 I/O ports (Except RA4) VDD - 0.7 — — V IOH=-3.0 mA, VDD=4.5V, -40° to +85°C
VDD - 0.7 — — V IOH=-2.5 mA, VDD=4.5V, +125°C
D092 OSC2/CLKOUT (ER only) VDD - 0.7 — — V IOH=-1.3 mA, VDD=4.5V, -40° to +85°C
VDD - 0.7 — — V IOH=-1.0 mA, VDD=4.5V, +125°C
D150 VOD Open-Drain High Voltage — 8.5 V RA4 pin PIC16F62X, PIC16LF62X*
Capacitive Loading Specs on Output Pins
D100* COSC2 OSC2 pin — 15 pF In XT, HS and LP modes when external
clock used to drive OSC1.
D101* Cio All I/O pins/OSC2 (in ER mode) — 50 pF
† Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.
Note 1: In ER oscillator configuration, the OSC1 pin is a Schmitt Trigger input. It is not recommended that the PIC16F62X be driven with exter-
nal clock in ER mode.
2: The leakage current on the MCLR pin is strongly dependent on applied voltage level. The specified levels represent normal operating
conditions. Higher leakage current may be measured at different input voltages.
3: Negative current is defined as coming out of the pin.

PIC16F62X
TABLE 17-1: COMPARATOR SPECIFICATIONS
Operating Conditions: 3.0V < VDD <5.5V, -40°C < TA < +125°C, unless otherwise stated.
Param
Characteristics Sym Min Typ Max Units Comments
No.
D300 Input offset voltage VIOFF — ±5.0 ±10 mV

D301* Input Common mode voltage VICM 0 — VDD - 1.5 V
D302* Common Mode Rejection Ratio CMRR 55 — — db
300* Response Time(1) TRESP — 150 400 ns 16F62X
300A 600 ns 16LF62X
301 Comparator Mode Change to TMC2OV — — 10 µs
Output Valid*
Note 1: Response time measured with one comparator input at (VDD - 1.5)/2 while the other input transitions from
VSS to VDD.
TABLE 17-2: VOLTAGE REFERENCE SPECIFICATIONS

Operating Conditions: 3.0V < VDD < 5.5V, -40°C < TA < +125°C, unless otherwise stated.
Spec
Characteristics Sym Min Typ Max Units Comments
No.
D310 Resolution VRES VDD/24 — VDD/32 LSb
D311 Absolute Accuracy VRaa — — 1/4 LSb Low Range (VRR = 1)
— — 1/2 LSb High Range (VRR = 0)
D312* Unit Resistor Value (R) VRur — 2k — Ω
310* Settling Time(1) Tset — — 10 µs
Note 1: Settling time measured while VRR = 1 and VR<3:0> transitions from 0000 to 1111.

PIC16F62X
17.3 Timing Parameter Symbology
The timing parameter symbols have been created with one of the following formats:
1. TppS2ppS
2. TppS
T
F Frequency T Time
Lowercase subscripts (pp) and their meanings:
pp
ck CLKOUT osc OSC1
io I/O port t0 T0CKI
mc MCLR
Uppercase letters and their meanings:
S
F Fall P Period
H High R Rise
I Invalid (Hi-impedance) V Valid
L Low Z Hi-Impedance
FIGURE 17-5: LOAD CONDITIONS
Load Condition 1 Load Condition 2
VDD/2
RL
CL CL
PIN PIN
VSS VSS
RL = 464Ω
CL = 50 pF for all pins except OSC2
15 pF for OSC2 output

PIC16F62X
TABLE 17-3: DC CHARACTERISTICS: PIC16F62X, PIC16LF62X
DC Characteristics Standard Operating Conditions (unless otherwise stated)
Parameter
Sym Characteristic Min Typ† Max Units Conditions
No.
Data EEPROM Memory
D120 ED Endurance 1M* 10M — E/W 25°C at 5V
D121 VDRW VDD for read/write VMIN — 5.5 V VMIN = Minimum operating
voltage
D122 TDEW Erase/Write cycle time — 4 8* ms
Program FLASH Memory
D130 EP Endurance 1000* 10000 — E/W
D131 VPR VDD for read Vmin — 5.5 V VMIN = Minimum operating
voltage
D132 VPEW VDD for erase/write 4.5 — 5.5 V
D133 TPEW Erase/Write cycle time — 4 8* ms
† Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
17.4 Timing Diagrams and Specifications
FIGURE 17-6: EXTERNAL CLOCK TIMING
Q4 Q1 Q2 Q3 Q4 Q1
OSC1
1 3 3
4 4
2
CLKOUT

PIC16F62X
TABLE 17-4: EXTERNAL CLOCK TIMING REQUIREMENTS
Param
No.
Fosc External CLKIN Frequency(1) DC — 4 MHz XT and ER Osc mode,
VDD = 5.0V
DC — 20 MHz HS Osc mode
DC — 200 kHz LP Osc mode
Oscillator Frequency(1) — 4 MHz ER Osc mode, VDD = 5.0V

0.1 — 4 MHz XT Osc mode
1 — 20 MHz HS Osc mode
— 200 kHz LP Osc mode
3.65 4 4.28 MHz INTRC mode (fast), VDD = 5.0V
37 kHz INTRC mode (slow)
4 INTRC Internal Calibrated RC 3.65 4.00 4.28 MHz VDD = 5.0V
5 ER External Biased ER Frequency 10 kHz 8 MHz VDD = 5.0V
1 Tosc External CLKIN Period(1) 250 — — ns XT and ER Osc mode
50 — — ns HS Osc mode
5 — — µs LP Osc mode
Oscillator Period(1) 250 — — ns ER Osc mode

250 — 10,000 ns XT Osc mode
50 — 1,000 ns HS Osc mode
5 µs LP Osc mode
250 ns INTRC mode (fast)
27 µs INTRC mode (slow)
2 Tcy Instruction Cycle Time 1.0 TCY DC ns TCY = 4/FOSC
3 TosL, External CLKIN (OSC1) High 100 * — — ns XT oscillator, TOSC L/H duty
TosH External CLKIN Low cycle*
and are not tested.
Note 1: Instruction cycle period (Tcy) equals four times the input oscillator time-based period. All specified values
are based on characterization data for that particular oscillator type under standard operating conditions
with the device executing code. Exceeding these specified limits may result in an unstable oscillator
operation and/or higher than expected current consumption. All devices are tested to operate at “Min.”
values with an external clock applied to the OSC1 pin. When an external clock input is used, the “Max”
cycle time limit is “DC” (no clock) for all devices.

PIC16F62X
FIGURE 17-7: CLKOUT AND I/O TIMING
Q4 Q1 Q2 Q3
OSC1
11
10
22
CLKOUT 23
13 12
19 18
14 16
I/O PIN
(INPUT)
17 15
I/O PIN NEW VALUE

OLD VALUE
(OUTPUT)
20, 21
TABLE 17-5: CLKOUT AND I/O TIMING REQUIREMENTS

Param
Sym Characteristic Min Typ† Max Units
No.
10* TosH2ckL OSC1↑ to CLKOUT↓ 16F62X — 75 200 ns

10A* 16LF62X — — 400 ns
11* TosH2ckH OSC1↑ to CLKOUT↑ 16F62X — 75 200 ns
11A* 16LF62X — — 400 ns
12* TckR CLKOUT rise time 16F62X — 35 100 ns
12A* 16LF62X — — 200 ns
13* TckF CLKOUT fall time 16F62X — 35 100 ns
13A* 16LF62X — — 200 ns
14* TckL2ioV CLKOUT ↓ to Port out valid — — 20 ns
15* TioV2ckH Port in valid before 16F62X Tosc+200 ns — — ns
CLKOUT ↑ 16LF62X Tosc=400 ns — — ns
16* TckH2ioI Port in hold after CLKOUT ↑ 0 — — ns
17* TosH2ioV OSC1↑ (Q1 cycle) to 16F62X — 50 150* ns
Port out valid 16LF62X — — 300 ns
18* TosH2ioI OSC1↑ (Q2 cycle) to Port input invalid 100 — — ns
(I/O in hold time) 200
and are not tested.

PIC16F62X
FIGURE 17-8: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING
VDD
MCLR
30
Internal
POR
33
PWRT
Timeout 32
OSC
Timeout
Internal
RESET
Watchdog
Timer
RESET
31
34 34
I/O Pins
FIGURE 17-9: BROWN-OUT DETECT TIMING
VDD VBOD
35
TABLE 17-6: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER REQUIREMENTS
Param
No.
30 TmcL MCLR Pulse Width (low) 2000 — — ns VDD = 5V, -40°C to +85°C
TBD TBD TBD ms Extended temperature
31 Twdt Watchdog Timer Timeout Period 7 18 33 ms VDD = 5V, -40°C to +85°C
(No Prescaler) TBD TBD TBD ms Extended temperature
32 Tost Oscillation Start-up Timer Period — 1024TOSC — — TOSC = OSC1 period
33* Tpwrt Power-up Timer Period 28 72 132 ms VDD = 5V, -40°C to +85°C
TBD TBD TBD ms Extended temperature
34 TIOZ I/O Hi-impedance from MCLR Low — — 2.0 µs

or Watchdog Timer Reset
35 TBOD Brown-out Detect pulse width 100 — — µs VDD ≤ VBOD (D005)
† Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.

PIC16F62X
FIGURE 17-10: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS
RA4/T0CKI
40 41
42
RB6/T1OSO/T1CKI
45 46
47 48
TMR0 OR
TMR1

PIC16F62X
TABLE 17-7: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS
Param
No.
40* Tt0H T0CKI High Pulse Width No Prescaler 0.5TCY + 20 — — ns
With Prescaler 10 — — ns
41* Tt0L T0CKI Low Pulse Width No Prescaler 0.5TCY + 20 — — ns
With Prescaler 10 — — ns
42* Tt0P T0CKI Period Greater of: — — ns N = prescale value
TCY + 40 (2, 4, ..., 256)
N
45* Tt1H T1CKI High Synchronous, No Prescaler 0.5TCY + 20 — — ns
Time Synchronous, 16F62X 15 — — ns
with Prescaler 16LF62X 25 — — ns
Asynchronous 16F62X 30 — — ns
16LF62X 50 — — ns
46* Tt1L T1CKI Low Time Synchronous, No Prescaler 0.5TCY + 20 — — ns
Synchronous, 16F62X 15 — — ns
with Prescaler 16LF62X 25 — — ns
16LF62X 50 — — ns
47* Tt1P T1CKI input Synchronous 16F62X Greater of: — — ns N = prescale value
period TCY + 40 (1, 2, 4, 8)
N
16LF62X Greater of: — — —
TCY + 40
N
16LF62X 100 — — ns
Ft1 Timer1 oscillator input frequency range DC — 200 kHz
(oscillator enabled by setting bit T1OSCEN)
48 TCKEZtmr1 Delay from external clock edge to timer 2Tosc — 7Tosc —
increment
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
FIGURE 17-11: CAPTURE/COMPARE/PWM TIMINGS
RB3/CCP1
(CAPTURE MODE)
50 51
52
RB3/CCP1
(COMPARE OR PWM MODE)
53 54

PIC16F62X
TABLE 17-8: CAPTURE/COMPARE/PWM REQUIREMENTS
Param
No.
50* TccL CCP No Prescaler 0.5TCY + 20 — — ns
input low time 16F62X 10 — — ns
With Prescaler 16LF62X 20 — — ns
51* TccH CCP No Prescaler 0.5TCY + 20 — — ns
input high time 16F62X 10 — — ns
With Prescaler 16LF62X 20 — — ns
52* TccP CCP input period 3TCY + 40 — — ns N = prescale value
N (1,4 or 16)
53* TccR CCP output rise time 16F62X 10 25 ns
16LF62X 25 45 ns
54* TccF CCP output fall time 16F62X 10 25 ns
16LF62X 25 45 ns
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
FIGURE 17-12: TIMER0 CLOCK TIMING
RA4/T0CKI
40 41
42
TMR0
TABLE 17-9: TIMER0 CLOCK REQUIREMENTS

Param
No.
40 Tt0H T0CKI High Pulse Width No Prescaler 0.5 TCY + 20* — — ns
With Prescaler 10* — — ns
41 Tt0L T0CKI Low Pulse Width No Prescaler 0.5 TCY + 20* — — ns
With Prescaler 10* — — ns
42 Tt0P T0CKI Period TCY + 40* — — ns N = prescale value (1, 2,
N 4, ..., 256)
† Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.

PIC16F62X
NOTES:

PIC16F62X
18.0 DC AND AC
CHARACTERISTICS GRAPHS
AND TABLES
In some graphs or tables, the data presented is outside
specified operating range (i.e., outside specified VDD
range). This is for information only and devices are
ensured to operate properly only within the specified
range.
The data presented in this section is a statistical
summary of data collected on units from different lots
over a period of time and matrix samples. 'Typical'
represents the mean of the distribution at 25°C. 'max or
min.' represents (mean + 3σ) or (mean - 3σ)
respectively, where σ is standard deviation, over the
whole temperature range.
Note: The graphs and tables provided in this sec-
tion are for design guidance and are not
tested.
FIGURE 18-1: TYPICAL IDD VS FOSC OVER VDD – HS MODE

Typical: statistical mean @ 25°C
Typical IDD vs FOSC over VDD Maximum: mean + 3σ (-40°C to 125°C)
(HS mode) Minimum: mean – 3σ (-40°C to 125°C)
6
5.5V
IDD (mA)
5.0V
3
4.5V
2 4.0V
0
4 6 8 10 12 14 16 18 20
FOSC (MHz)

PIC16F62X
.
Note: The graphs and tables provided in this section are for design guidance and are not tested.
FIGURE 18-2: MAXIMUM IDD VS FOSC OVER VDD (HS MODE)

Maximum IDD vs FOSC over VDD Maximum: mean + 3σ (-40°C to 125°C)
Minimum: mean – 3σ (-40°C to 125°C)
(HS mode)
7
5.5V
4
IDD (mA)
5.0V
3
4.5V
4.0V
2
0
4 6 8 10 12 14 16 18 20
FOSC (MHz)
FIGURE 18-3: TYPICAL IDD VS FOSC OVER VDD (XT MODE)

Maximum: mean + 3σ PIC16LF628
(-40°C to 125°C)
Typical IDD vs F OSC over V DD
(XT mode)
1.2
1.0
0.8
5.5V
IDD (mA)
0.6 5.0V
4.5V
4.0V
0.4
3.5V
3.0V
2.5V
0.2
2.0V
0.0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
F OSC (MHz)

PIC16F62X
.
FIGURE 18-4: TYPICAL IDD VS FOSC OVER VDD (XT MODE)

PIC 16LF628
Maximum: mean + 3σ (-40°C to 125°C)
Typical I DD vs F O SC over V DD
(XT m ode) Minimum: mean – 3σ (-40°C to 125°C)
1.2
1.0
0.8
5.5V
IDD (mA)
0.6 5.0V
4.5V
4.0V
0.4
3.5V
3.0V
2.5V
0.2
2.0V
0.0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
F O SC (M H z)
FIGURE 18-5: TYPICAL IDD VS FOSC OVER VDD (LP MODE)

Typical I DD vs F OSC over V DD Maximum: mean +PIC16LF628
3σ (-40°C to 125°C)
(LP mode)
90
80
70
5.5V
60
5.0V
4.5V
50
Ipd (uA)
4.0V
40
3.5V
30
3.0V
20
2.5V
10
0
30.000 40.000 50.000 60.000 70.000 80.000 90.000 100.000
F OSC (kHz)

PIC16F62X
FIGURE 18-6: MAXIMUM IDD VS FOSC OVER VDD (LP MODE)

Maximum: meanPIC16LF628
+ 3σ (-40°C to 125°C)
Maximum I DD vs F OSC over V DD Minimum: mean – 3σ (-40°C to 125°C)
(LP m ode)
120.00
100.00
80.00 5.5V
5.0V
IDD (uA)
60.00
4.5V
4.0V
40.00 3.5V
3.0V
20.00 2.5V
0.00
30.000 40.000 50.000 60.000 70.000 80.000 90.000 100.000
F OSC (kHz)
FIGURE 18-7: TYPICAL FOSC VS VDD (ER MODE)

T yp ic a l F o s c vs . V D D Maximum: mean + 3σ (-40°C to 125°C)
(E R M o d e ) Minimum: mean – 3σ (-40°C to 125°C)
3.50
R = 50 k Ω
3.00
2.50
Frequency (MHz)
2.00
R = 100 k Ω
1.50
1.00
R = 200 k Ω
0.50
R = 500 k Ω
R = 1 M Ω
0.00
2.0 2.5 3.0 3.5 4.0 4.5 5.0
V D D (V o lts)

PIC16F62X
FIGURE 18-8: TYPICAL INTERNAL RC FOSC VS VDD TEMPERATURE (-40 TO 125°C)

INTERNAL 4 MHz OSCILLATOR
Typical Internal RC FOSC vs VDD over Maximum: mean + 3σ (-40°C to 125°C)
Temperature (-40 to 125 C) Internal 4 MHz Oscillator Minimum: mean – 3σ (-40°C to 125°C)
4.1
125 C
85 C
25 C
4.0
3.9
-40 C
FOSC (MHz)
3.8
3.7
3.6
3.5
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
FIGURE 18-9: TYPICAL INTERNAL RC FOSC VS VDD OVER TEMPERATURE (-40 TO 125°C)
INTERNAL 37 kHz OSCILLATOR
Typical Internal RC F OSC vs V DD over Maximum: mean + 3σ PIC16LF628
(-40°C to 125°C)
Temperature (-40 to 125 C) Minimum: mean – 3σ (-40°C to 125°C)
Internal 37kHz Oscillator
60.000
50.000
125 C
85 C
40.000
25 C
FOSC (KHz)
30.000 -40 C
20.000
10.000
0.000
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
V DD (V)

PIC16F62X
FIGURE 18-10: IPD VS VDD SLEEP MODE, ALL PERIPHERALS DISABLED

IPD vs VDD Minimum: mean – 3σ (-40°C to 125°C)
Sleep mode, all peripherals disabled
4.0
Max (125C)
3.0
IPD (uA)
2.0
1.0
Max (85C)
Typ (25C)
0.0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
FIGURE 18-11: ∆lBOD VS VOH OVER TEMPERATURE (-40 to 125°C)

∆IBOR vs VOH over Temperature (-40 to 125 C) Maximum: mean + 3σ (-40°C to 125°C)
0.120
0.110
0.100
Max
∆IBOR (mA)
0.090 Max
Typ Reset (25C)
Typ Sleep (25C)

0.080
0.070
Indeterminate
Device in Reset Device in Sleep
0.060
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)

PIC16F62X
FIGURE 18-12: ∆lTMR1OSC VS VDD OVER TEMP (0C to +70°C)

SLEEP MODE, TIMER1 OSCILLATOR, 32 kHz XTAL
∆ITMR1OSC vs VDD over Temp (0C to +70C) Maximum: mean + 3σ (-40°C to 125°C)
Sleep mode, Timer1 oscillator, 32 kHz XTAL
90
80
70
60
∆ITMR1OSC (uA)
50
Max
40
Typ (25C)
30
20
10
0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
FIGURE 18-13: ∆lWDT VS VDD SLEEP MODE, WATCH DOG TIMER ENABLED
∆IWDT vs VDD Minimum: mean – 3σ (-40°C to 125°C)
Sleep mode, watch dog timer enabled
13.0
12.0
11.0
10.0
Max (125C)
9.0
8.0
∆IWDT (uA)
7.0
Typ (25C)
6.0
5.0
4.0
3.0
2.0
1.0
0.0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)

PIC16F62X
FIGURE 18-14: ∆lCOMP VS VDD SLEEP MODE, COMPARATORS ENABLED

∆ICOMP vs VDD Minimum: mean – 3σ (-40°C to 125°C)
Sleep mode, Comparators enabled
140.0
120.0
100.0
80.0 Max (125C)

∆ICOMP (uA)
Typ (25C)
60.0
40.0
20.0
0.0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
FIGURE 18-15: ∆lvREF VS VDD SLEEP MODE, VREF ENABLED

∆IVREF vs VDD Maximum: mean + 3σ (-40°C to 125°C)
Sleep mode, VREF enabled
90.0
80.0
70.0
Max (125C)
60.0
Typ (25C)
∆IVREF (uA)
50.0
40.0
30.0
20.0
10.0
0.0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)

PIC16F62X
FIGURE 18-16: MINIMUM, TYPICAL and MAXIMUM WDT PERIOD VS VDD (-40°C to +125°C)
PIC16LF228
Minimum, Typical and Maximum Maximum: mean + 3σ (-40°C to 125°C)
WDT Period vs V DD (-40C to +125C) Minimum: mean – 3σ (-40°C to 125°C)
45
40
35
30
Max 125C
WDT Period (mS)
25 Max 85C
20
Typ 25C
15
Min -40C
10
0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
V DD (V)
FIGURE 18-17: TYPICAL WDT PERIOD VS VDD (-40°C to +125°C)

PIC16LF228
Typical WDT Period Maximum: mean + 3σ (-40°C to 125°C)
vs VDD (-40C to +125C)
45
40
35
30
WDT Period (mS)
125 C
25
85 C
20
25 C
15
-40 C
10
0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)

PIC16F62X
FIGURE 18-18: VOH VS IOH OVER TEMP (C) VDD = 5V

VOH vs IOH over Temp (C) Minimum: mean – 3σ (-40°C to 125°C)
VDD = 5V
5.0
4.5
4.0
3.5 Max (-40C)
3.0
Typ (25C)
VOH (V)
2.5
2.0
1.5
Min (125C)
1.0
0.5
0.0
0.0 5.0 10.0 15.0 20.0 25.0
IOH (-mA)
FIGURE 18-19: VOH VS IOH OVER TEMP (C) VDD = 3V

VOH vs IOH over Temp (C) Minimum: mean – 3σ (-40°C to 125°C)
VDD = 3V
3.0
2.5
2.0
VOH (V)
1.5
1.0
0.5
Min (125C) Typ (25C) Max (-40C)

0.0
0.0 2.0 4.0 6.0 8.0 10.0 12.0 14.0
IOH (-mA)

PIC16F62X
FIGURE 18-20: VOL VS IOL OVER TEMP (C) VDD = 5V

VOL vs IOL over Temp (C) Minimum: mean – 3σ (-40°C to 125°C)
VDD = 5V
0.80
0.70 Max (125C)
0.60
0.50
Typ (25C)
VOL (V)
0.40
Min (-40C)
0.30
0.20
0.10
0.00
0.0 5.0 10.0 15.0 20.0 25.0
IOL (mA)
FIGURE 18-21: VOL VS IOL OVER TEMP (C) VDD = 3V

VOL vs IOL over Temp (C) Minimum: mean – 3σ (-40°C to 125°C)
VDD = 3V
1.40
Max (125C)
1.20
1.00
0.80
Typ (25C)
VOL (V)
0.60
Min (-40C)
0.40
0.20
0.00
0.0 5.0 10.0 15.0 20.0 25.0
IOL (mA)

PIC16F62X
FIGURE 18-22: VIN VS VDD TTL

VIN vs VDD Maximum: mean + 3σ (-40°C to 125°C)
TTL Input
2.0
1.5 Max (-40C)
Min (125C)
Vin (V)
1.0
0.5
0.0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)
FIGURE 18-23: VIN VS VDD ST INPUT

VIN vs VDD Maximum: mean + 3σ (-40°C to 125°C)
ST Input
5.0
4.0
Max High (125C)
3.0
Vin (V)
Min High (-40C)
2.0
Max Low (125C)
Min Low (-40C)

1.0
0.0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
VDD (V)

PIC16F62X
FIGURE 18-24: MAXIMUM IDD VS VDD OVER TEMPERATURE

(-40 TO +125°C) INTERNAL 37 kHz OSCILLATOR
Typical: statistical PIC16LF628
mean @ 25°C
Maximum IDD vs V DD over Temperature Maximum: mean + 3σ (-40°C to 125°C)
(-40 to +125 C) Internal 37kHz Oscillator Minimum: mean – 3σ (-40°C to 125°C)
35.000
30.000
125 C
25.000
IDD (µA)
85
25 C
20.000
-40 C
15.000
10.000
2.5 3.0 3.5 4.0 4.5 5.0 5.5
V DD (Volts)
FIGURE 18-25: TYPICAL IDD VS VDD OVER TEMPERATURE (-40 TO +125°C)

INTERNAL 37 kHz OSCILLATOR
PIC16LF628
Typical IDD vs V DD over Temperature Maximum: mean + 3σ (-40°C to 125°C)
(-40 to +125 C) Internal 37kHz Oscillator Minimum: mean – 3σ (-40°C to 125°C)
35.000
30.000
25.000
IDD (µA)
125 C
20.000 85 C
25 C
-40C
15.000
10.000
2.5 3.0 3.5 4.0 4.5 5.0 5.5
V DD (Volts)

PIC16F62X
FIGURE 18-26: MAXIMUM IDD VS VDD OVER TEMPERATURE

(-40 TO +125°C) INTERNAL 4 MHz OSCILLATOR
PIC16LF628
Maximum IDD vs V DD over Temperature Maximum: mean + 3σ (-40°C to 125°C)
(-40 to +125 C) Internal 4MHz Oscillator Minimum: mean – 3σ (-40°C to 125°C)
1.30
1.20
1.10
1.00
0.90
IDD (mA)
0.80 125 85 25 C -40 C
0.70
0.60
0.50
0.40
2.5 3.0 3.5 4.0 4.5 5.0 5.5
V DD (Volts)
FIGURE 18-27: TYPICAL IDD VS VDD OVER TEMPERATURE

(-40 TO +125°C) INTERNAL 4 MHz OSCILLATOR
Typical IDD vs V DD over Temperature Maximum: mean +PIC16LF628
3σ (-40°C to 125°C)
(-40 to +125 C) Internal 4MHz Oscillator Minimum: mean – 3σ (-40°C to 125°C)
1.200
1.100
1.000
0.900
IDD (mA)
125 C 85 C 25 C -40C
0.800
0.700
0.600
0.500
0.400
2.5 3.0 3.5 4.0 4.5 5.0 5.5
V DD (Volts)

PIC16F62X
19.0 PACKAGING INFORMATION
19.1 Package Marking Information
18-LEAD PDIP EXAMPLE
XXXXXXXXXXXXXXXXX PIC16F628/P
XXXXXXXXXXXXXXXXX
YYWWNNN 9917017
18-LEAD SOIC (.300") EXAMPLE

XXXXXXXXXXXX
XXXXXXXXXXXX
XXXXXXXXXXXX PIC16F628/SO
YYWWNNN 9910017
20-LEAD SSOP EXAMPLE
XXXXXXXXXX PIC16F628/SO
XXXXXXXXXX
YYWWNNN 9910017
Legend: MM...M Microchip part number information

XX...X Customer specific information(1)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Note: In the event the full Microchip part number cannot be marked on one line, it will be carried
over to the next line thus limiting the number of available characters for customer specific
information.
* Standard OTP marking consists of Microchip part number, year code, week code, facility code, mask rev#, and
assembly code. For OTP marking beyond this, certain price adders apply. Please check with your Microchip Sales
Office. For QTP devices, any special marking adders are included in QTP price.

PIC16F62X
K04-007 18-Lead Plastic Dual In-line (P) – 300 mil
E1
n 1 α
E A2
c L
A1
B1
β
B p
eB
Units INCHES* MILLIMETERS

Dimension Limits MIN NOM MAX MIN NOM MAX
Number of Pins n 18 18
Pitch p .100 2.54
Top to Seating Plane A .140 .155 .170 3.56 3.94 4.32
Molded Package Thickness A2 .115 .130 .145 2.92 3.30 3.68
Base to Seating Plane A1 .015 0.38
Shoulder to Shoulder Width E .300 .313 .325 7.62 7.94 8.26
Molded Package Width E1 .240 .250 .260 6.10 6.35 6.60
Overall Length D .890 .898 .905 22.61 22.80 22.99
Tip to Seating Plane L .125 .130 .135 3.18 3.30 3.43
Lead Thickness c .008 .012 .015 0.20 0.29 0.38
Upper Lead Width B1 .045 .058 .070 1.14 1.46 1.78
Lower Lead Width B .014 .018 .022 0.36 0.46 0.56
Overall Row Spacing § eB .310 .370 .430 7.87 9.40 10.92
Mold Draft Angle Top α 5 10 15 5 10 15
Mold Draft Angle Bottom β 5 10 15 5 10 15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-001
Drawing No. C04-007

PIC16F62X
K04-051 18-Lead Plastic Small Outline (SO) – Wide, 300 mil
E
p
E1
2
B n 1
h
α
45°
c
A A2
φ
β L A1

Pitch p .050 1.27
Overall Height A .093 .099 .104 2.36 2.50 2.64
Standoff § A1 .004 .008 .012 0.10 0.20 0.30
Overall Width E .394 .407 .420 10.01 10.34 10.67
Overall Length D .446 .454 .462 11.33 11.53 11.73
Chamfer Distance h .010 .020 .029 0.25 0.50 0.74
Foot Length L .016 .033 .050 0.41 0.84 1.27
Foot Angle φ 0 4 8 0 4 8
Lead Thickness c .009 .011 .012 0.23 0.27 0.30
Lead Width B .014 .017 .020 0.36 0.42 0.51
Notes:
.010” (0.254mm) per side.
JEDEC Equivalent: MS-013
Drawing No. C04-051

PIC16F62X
K04-072 20-Lead Plastic Shrink Small Outline (SS) – 5.30 mm
E1
p
B 2
n 1
c
A A2
L A1
β

Pitch p .026 0.65
Overall Height A .068 .073 .078 1.73 1.85 1.98
Standoff § A1 .002 .006 .010 0.05 0.15 0.25
Overall Width E .299 .309 .322 7.59 7.85 8.18
Overall Length D .278 .284 .289 7.06 7.20 7.34
Foot Length L .022 .030 .037 0.56 0.75 0.94
Lead Thickness c .004 .007 .010 0.10 0.18 0.25
Foot Angle φ 0 4 8 0.00 101.60 203.20
Lead Width B .010 .013 .015 0.25 0.32 0.38
Notes:
.010” (0.254mm) per side.
JEDEC Equivalent: MO-150
Drawing No. C04-072

PIC16F62X
INDEX Comparator Interrupts......................................................... 57
Comparator Module ............................................................ 53
A Comparator Operation ........................................................ 55
A/D Comparator Reference ....................................................... 55
Special Event Trigger (CCP)....................................... 63 Compare (CCP Module) ..................................................... 62
Absolute Maximum Ratings .............................................. 127 Block Diagram ............................................................ 62
ADDLW Instruction ........................................................... 109 CCP Pin Configuration ............................................... 62
ADDWF Instruction ........................................................... 109 CCPR1H:CCPR1L Registers ..................................... 62
ANDLW Instruction ........................................................... 109 Software Interrupt ....................................................... 63
ANDWF Instruction ........................................................... 109 Special Event Trigger ................................................. 63
Architectural Overview .......................................................... 7 Timer1 Mode Selection............................................... 63
Assembler Configuration Bits ............................................................... 91
MPASM Assembler ................................................... 121 Configuring the Voltage Reference..................................... 59
Crystal Operation................................................................ 93
B
Baud Rate Error .................................................................. 69
D
Baud Rate Formula ............................................................. 69 DATA .................................................................................. 89
BCF Instruction ................................................................. 110 Data .................................................................................... 88
Block Diagram Data EEPROM Memory...................................................... 87
TMR0/WDT PRESCALER .......................................... 44 EECON1 Register ...................................................... 87
Block Diagrams EECON2 Register ...................................................... 87
Comparator I/O Operating Modes............................... 54 Data Memory Organization................................................. 13
Comparator Output ..................................................... 56 DECF Instruction .............................................................. 112
RA3:RA0 and RA5 Port Pins ...................................... 35 DECFSZ Instruction.......................................................... 113
Timer1 ......................................................................... 47 Development Support ....................................................... 121
Timer2 ......................................................................... 50
USART Receive.......................................................... 77
E
USART Transmit ......................................................... 75 Errata .................................................................................... 3
BRGH bit ............................................................................. 69 External Crystal Oscillator Circuit ....................................... 93
Brown-Out Detect (BOD) .................................................... 96
BSF Instruction ................................................................. 110
G
BTFSC Instruction............................................................. 110 General purpose Register File............................................ 13
BTFSS Instruction ............................................................. 111 GOTO Instruction.............................................................. 113
C I
CALL Instruction ............................................................... 111 I/O Ports ............................................................................. 29
Capture (CCP Module) ....................................................... 62 I/O Programming Considerations ....................................... 42
Block Diagram............................................................. 62 ID Locations...................................................................... 105
CCP Pin Configuration................................................ 62 INCF Instruction................................................................ 114
CCPR1H:CCPR1L Registers...................................... 62 INCFSZ Instruction ........................................................... 114
Changing Between Capture Prescalers...................... 62 In-Circuit Serial Programming........................................... 106
Software Interrupt ....................................................... 62 Indirect Addressing, INDF and FSR Registers ................... 25
Timer1 Mode Selection ............................................... 62 Instruction Flow/Pipelining .................................................. 11
Capture/Compare/PWM (CCP)........................................... 61 Instruction Set
Capture Mode. See Capture ADDLW ..................................................................... 109
CCP1 .......................................................................... 61 ADDWF .................................................................... 109
CCPR1H Register............................................... 61 ANDLW ..................................................................... 109
CCPR1L Register ............................................... 61 ANDWF .................................................................... 109
CCP2 .......................................................................... 61 BCF .......................................................................... 110
Compare Mode. See Compare BSF........................................................................... 110
PWM Mode. See PWM BTFSC...................................................................... 110
Timer Resources......................................................... 61 BTFSS ...................................................................... 111
CCP1CON Register CALL......................................................................... 111
CCP1M3:CCP1M0 Bits............................................... 61 CLRF ........................................................................ 111
CCP1X:CCP1Y Bits .................................................... 61 CLRW ....................................................................... 112
CCP2CON Register CLRWDT .................................................................. 112
CCP2M3:CCP2M0 Bits............................................... 61 COMF ....................................................................... 112
CCP2X:CCP2Y Bits .................................................... 61 DECF........................................................................ 112
Clocking Scheme/Instruction Cycle .................................... 11 DECFSZ ................................................................... 113
CLRF Instruction ............................................................... 111 GOTO ....................................................................... 113
CLRW Instruction .............................................................. 112 INCF ......................................................................... 114
CLRWDT Instruction ......................................................... 112 INCFSZ..................................................................... 114
Code Protection ................................................................ 105 IORLW ...................................................................... 115
COMF Instruction .............................................................. 112 IORWF...................................................................... 115
Comparator Configuration................................................... 54 MOVF ....................................................................... 115

PIC16F62X
MOVLW..................................................................... 115 Pin Functions
MOVWF .................................................................... 116 RC6/TX/CK ........................................................... 67–84
NOP .......................................................................... 116 RC7/RX/DT........................................................... 67–84
OPTION .................................................................... 116 PIR1.................................................................................... 23
RETFIE ..................................................................... 116 PIR1 Register ..................................................................... 23
RETLW...................................................................... 117 Port RB Interrupt............................................................... 102
RETURN ................................................................... 117 PORTA ............................................................................... 29
RLF ........................................................................... 117 PORTB ............................................................................... 34
RRF........................................................................... 118 Power Control/Status Register (PCON).............................. 97
SLEEP ...................................................................... 118 Power-Down Mode (SLEEP) ............................................ 104
SUBLW...................................................................... 118 Power-On Reset (POR) ...................................................... 96
SUBWF ..................................................................... 119 Power-up Timer (PWRT) .................................................... 96
SWAPF ..................................................................... 119 PR2 Register ...................................................................... 50
TRIS .......................................................................... 119 Prescaler............................................................................. 44
XORLW ..................................................................... 120 Prescaler, Capture.............................................................. 62
XORWF..................................................................... 120 Prescaler, Timer2 ............................................................... 65
Instruction Set Summary................................................... 107 PRO MATE II Universal Device Programmer ................... 123
INT Interrupt ...................................................................... 102 Program Memory Organization........................................... 13
INTCON Register ................................................................ 21 PROTECTION .................................................................... 89
Interrupt Sources PWM (CCP Module) ........................................................... 64
Capture Complete (CCP) ............................................ 62 Block Diagram ............................................................ 64
Compare Complete (CCP) .......................................... 63 CCPR1H:CCPR1L Registers...................................... 64
TMR2 to PR2 Match (PWM) ....................................... 64 Duty Cycle .................................................................. 65
Interrupts ........................................................................... 101 Example Frequencies/Resolutions ............................. 65
Interrupts, Enable Bits Output Diagram .......................................................... 64
CCP1 Enable (CCP1IE Bit)......................................... 62 Period ......................................................................... 64
Interrupts, Flag Bits Set-Up for PWM Operation......................................... 65
CCP1 Flag (CCP1IF Bit) ............................................. 62 TMR2 to PR2 Match ................................................... 64
IORLW Instruction............................................................. 115
IORWF Instruction............................................................. 115 Q
Q-Clock............................................................................... 65
M Quick-Turnaround-Production (QTP) Devices...................... 5
Memory Organization
Data EEPROM Memory .............................................. 87 R
MOVF Instruction .............................................................. 115 RC Oscillator....................................................................... 94
MOVLW Instruction ........................................................... 115 Registers
MOVWF Instruction........................................................... 116 Maps
MPLAB C17 and MPLAB C18 C Compilers...................... 122 PIC16C76 ........................................................... 14
MPLAB ICD In-Circuit Debugger....................................... 123 PIC16C77 ........................................................... 14
MPLAB ICE High Performance Universal In-Circuit Emulator Reset .................................................................................. 95
with MPLAB IDE................................................................ 123 RETFIE Instruction ........................................................... 116
MPLAB Integrated Development Environment Software .. 121 RETLW Instruction............................................................ 117
MPLINK Object Linker/MPLIB Object Librarian ................ 122 RETURN Instruction ......................................................... 117
RLF Instruction ................................................................. 117
N RRF Instruction................................................................. 118
NOP Instruction................................................................. 116
S
O Serial Communication Interface (SCI) Module, See USART
OPTION Instruction........................................................... 116 Serialized Quick-Turnaround-Production (SQTP) Devices... 5
OPTION Register ................................................................ 20 SLEEP Instruction............................................................. 118
Oscillator Configurations ..................................................... 93 Software Simulator (MPLAB SIM) .................................... 122
Oscillator Start-up Timer (OST) .......................................... 96 Special ................................................................................ 95
Output of TMR2................................................................... 50 Special Event Trigger. See Compare
Special Features of the CPU .............................................. 91
P Special Function Registers ................................................. 15
Package Marking Information ........................................... 157 Stack................................................................................... 25
Packaging Information ...................................................... 157 Status Register ................................................................... 19
PCL and PCLATH ............................................................... 25 SUBLW Instruction ........................................................... 118
PCON.................................................................................. 24 SUBWF Instruction ........................................................... 119
PCON Register ................................................................... 24 SWAPF Instruction ........................................................... 119
PICDEM 1 Low Cost PICmicro Demonstration Board ...... 124
PICDEM 17 Demonstration Board .................................... 124 T
PICDEM 2 Low Cost PIC16CXX Demonstration Board.... 124 T1CKPS0 bit ....................................................................... 46
PICSTART Plus Entry Level Development Programmer .. 123 T1CKPS1 bit ....................................................................... 46
PIE1 Register ...................................................................... 22 T1OSCEN bit ...................................................................... 46

PIC16F62X
T1SYNC bit ......................................................................... 46 Asynchronous Reception............................................ 79
T2CKPS0 bit ....................................................................... 51 Asynchronous Transmission....................................... 75
T2CKPS1 bit ....................................................................... 51 Asynchronous Transmitter.......................................... 74
Timer0 Baud Rate Generator (BRG) ...................................... 69
TIMER0 (TMR0) Interrupt ........................................... 43 Sampling......................................................... 70, 71, 72
TIMER0 (TMR0) Module............................................. 43 Synchronous Master Mode......................................... 81
TMR0 with External Clock........................................... 43 Synchronous Master Reception ................................. 83
Timer1 Synchronous Master Transmission ............................ 81
Special Event Trigger (CCP)....................................... 63 Synchronous Slave Mode........................................... 84
Switching Prescaler Assignment................................. 45 Synchronous Slave Reception ................................... 85
Timer2 Synchronous Slave Transmit...................................... 84
PR2 Register............................................................... 64 Transmit Block Diagram ............................................. 75
TMR2 to PR2 Match Interrupt ..................................... 64
Timers V
Timer1 Voltage Reference Module ................................................. 59
Asynchronous Counter Mode ............................. 48
Block Diagram .................................................... 47 W
Capacitor Selection............................................. 49 Watchdog Timer (WDT).................................................... 103
External Clock Input............................................ 47 WRITE ................................................................................ 89
External Clock Input Timing ................................ 48 WRITING ............................................................................ 88
Operation in Timer Mode .................................... 47 WWW, On-Line Support ....................................................... 3
Oscillator ............................................................. 49
Prescaler....................................................... 47, 49 X
Resetting of Timer1 Registers ............................ 49 XORLW Instruction ........................................................... 120
Resetting Timer1 using a CCP Trigger Output ... 49 XORWF Instruction........................................................... 120
Synchronized Counter Mode .............................. 47
TMR1H ............................................................... 48
TMR1L ................................................................ 48
Timer2
Block Diagram .................................................... 50
Module ................................................................ 50
Postscaler ........................................................... 50
Prescaler............................................................. 50
Timing Diagrams
Timer0 ....................................................................... 139
Timer1 ....................................................................... 139
USART Asynchronous Master Transmission.............. 75
USART RX Pin Sampling...................................... 73, 74
USART Synchronous Reception................................. 84
USART Synchronous Transmission............................ 82
USART, Asynchronous Reception .............................. 78
Timing Diagrams and Specifications................................. 135
TMR0 Interrupt .................................................................. 102
TMR1CS bit ........................................................................ 46
TMR1ON bit ........................................................................ 46
TMR2ON bit ........................................................................ 51
TOUTPS0 bit....................................................................... 51
TOUTPS1 bit....................................................................... 51
TOUTPS2 bit....................................................................... 51
TOUTPS3 bit....................................................................... 51
TRIS Instruction ................................................................ 119
TRISA ................................................................................. 29
TRISB ................................................................................. 34
U
Universal Synchronous Asynchronous Receiver Transmitter
(USART) ............................................................................. 67
Asynchronous Receiver
Setting Up Reception .......................................... 80
Timing Diagram .................................................. 78
Asynchronous Receiver Mode
Block Diagram .................................................... 80
Section ................................................................ 80
USART
Asynchronous Mode ................................................... 74
Asynchronous Receiver .............................................. 77

PIC16F62X
NOTES:

PIC16F62X
ON-LINE SUPPORT SYSTEMS INFORMATION AND
Microchip provides on-line support on the Microchip
UPGRADE HOT LINE
World Wide Web site. The Systems Information and Upgrade Line provides
The web site is used by Microchip as a means to make system users a listing of the latest versions of all of
files and information easily available to customers. To Microchip's development systems software products.
view the site, the user must have access to the Internet Plus, this line provides information on how customers
and a web browser, such as Netscape® or Microsoft® can receive the most current upgrade kits.The Hot Line
Internet Explorer. Files are also available for FTP Numbers are:
download from our FTP site. 1-800-755-2345 for U.S. and most of Canada, and
Connecting to the Microchip Internet Web Site 1-480-792-7302 for the rest of the world.
The Microchip web site is available at the following
URL:
092002
www.microchip.com
The file transfer site is available by using an FTP ser-
vice to connect to:
ftp://ftp.microchip.com
The web site and file transfer site provide a variety of
services. Users may download files for the latest
Development Tools, Data Sheets, Application Notes,
User's Guides, Articles and Sample Programs. A
variety of Microchip specific business information is
also available, including listings of Microchip sales
offices, distributors and factory representatives. Other
data available for consideration is:
• Latest Microchip Press Releases
• Technical Support Section with Frequently Asked
Questions
• Design Tips
• Device Errata
• Job Postings
• Microchip Consultant Program Member Listing
• Links to other useful web sites related to
Microchip Products
• Conferences for products, Development Systems,
technical information and more
• Listing of seminars and events
 2003 Microchip Technology Inc. Preliminary DS40300C-page 165

PIC16F62X
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod-
uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation
can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.
Please list the following information, and use this outline to provide us with your comments about this document.
To: Technical Publications Manager Total Pages Sent ________

RE: Reader Response
From: Name
Company
Address
City / State / ZIP / Country
Telephone: (_______) _________ - _________ FAX: (______) _________ - _________
Application (optional):
Would you like a reply? Y N
Device: PIC16F62X Literature Number: DS40300C
Questions:
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
DS40300C-page 166 Preliminary  2003 Microchip Technology Inc.

PIC16F62X
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO. -XX X /XX XXX
Examples:
Device Frequency Temperature Package Pattern a) PIC16F627 - 04/P 301 = Commercial Temp.,
Range Range PDIP package, 4 MHz, normal VDD limits, QTP
pattern #301.
b) PIC16LF627 - 04I/SO = Industrial Temp.,
Device PIC16F62X: Standard VDD range 3.0V to 5.5V SOIC package, 200 kHz, extended VDD limits.
PIC16F62XT VDD range 3.0V to 5.5V (Tape and Reel)
PIC16LF62X: VDD range 2.0V to 5.5V
PIC16LF62XT: VDD range 2.0V to 5.5V (Tape and Reel)
Frequency Range 04 = 200 kHz (LP osc)

04 = 4 MHz (XT and ER osc)
20 = 20 MHz (HS osc)
Temperature Range - = 0°C to +70°C

I = -40°C to +85°C
E = -40°C to +125°C
Package P = PDIP
SO = SOIC (Gull Wing, 300 mil body)
SS = SSOP (209 mil)
Pattern 3-Digit Pattern Code for QTP (blank otherwise).
* JW Devices are UV erasable and can be programmed to any device configuration. JW Devices meet the electrical requirement of
each oscillator type.
Sales and Support

Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and
recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1. Your local Microchip sales office

2. The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277
3. The Microchip Worldwide Site (www.microchip.com)
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.
New Customer Notification System

Register on our web site (www.microchip.com/cn) to receive the most current information on our products.
 2003 Microchip Technology Inc. Preliminary DS40300C-page167

WORLDWIDE SALES AND SERVICE
AMERICAS ASIA/PACIFIC Japan
Microchip Technology Japan K.K.
Corporate Office Australia
Benex S-1 6F
2355 West Chandler Blvd. Microchip Technology Australia Pty Ltd
3-18-20, Shinyokohama
Chandler, AZ 85224-6199 Suite 22, 41 Rawson Street
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Tel: 480-792-7200 Fax: 480-792-7277 Epping 2121, NSW
Kanagawa, 222-0033, Japan
Technical Support: 480-792-7627 Australia
Tel: 81-45-471- 6166 Fax: 81-45-471-6122
Web Address: http://www.microchip.com Tel: 61-2-9868-6733 Fax: 61-2-9868-6755
China - Beijing Korea
Rocky Mountain Microchip Technology Korea
2355 West Chandler Blvd. Microchip Technology Consulting (Shanghai)
168-1, Youngbo Bldg. 3 Floor
Chandler, AZ 85224-6199 Co., Ltd., Beijing Liaison Office
Samsung-Dong, Kangnam-Ku
Tel: 480-792-7966 Fax: 480-792-4338 Unit 915
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No. 6 Chaoyangmen Beidajie
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Tel: 770-640-0034 Fax: 770-640-0307 200 Middle Road
China - Chengdu
#07-02 Prime Centre
Boston Microchip Technology Consulting (Shanghai) Singapore, 188980
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Tel: 44 118 921 5869 Fax: 44-118 921-5820
12/05/02

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PIC16F62X

 2003 Microchip Technology Inc. Preliminary DS40300C

Information contained in this publication regarding device Trademarks

Serialized Quick Turn Programming (SQTP) is a service mark

All other trademarks mentioned herein are property of their

© 2003, Microchip Technology Incorporated, Printed in the

Printed on recycled paper.

Microchip received QS-9000 quality system

DS40300C - page ii Preliminary  2003 Microchip Technology Inc.

 2003 Microchip Technology Inc. Preliminary DS40300C-page 1

DS40300C-page 2 Preliminary  2003 Microchip Technology Inc.

TO OUR VALUED CUSTOMERS

Most Current Data Sheet

Customer Notification System

 2003 Microchip Technology Inc. Preliminary DS40300C-page 3

DS40300C-page 4 Preliminary  2003 Microchip Technology Inc.

 2003 Microchip Technology Inc. Preliminary DS40300C-page 5

DS40300C-page 6 Preliminary  2003 Microchip Technology Inc.

The PIC16F62X can directly or indirectly address its

 2003 Microchip Technology Inc. Preliminary DS40300C-page 7

Addr MUX RA0/AN0

MCLR VDD, VSS

Comparator Timer0 Timer1 Timer2

VREF CCP1 USART Data EEPROM

Note 1: Higher order bits are from the STATUS register.

DS40300C-page 8 Preliminary  2003 Microchip Technology Inc.

TABLE 2-1: PIC16F62X PINOUT DESCRIPTION

MCLR ST — Master clear

 2003 Microchip Technology Inc. Preliminary DS40300C-page 9

DS40300C-page 10 Preliminary  2003 Microchip Technology Inc.

FIGURE 2-2: CLOCK/INSTRUCTION CYCLE

EXAMPLE 2-1: INSTRUCTION PIPELINE FLOW

1. MOVLW 55h Fetch 1 Execute 1

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DS40300C-page 12 Preliminary  2003 Microchip Technology Inc.

Interrupt Vector 0004

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6Fh EFh 16Fh 1EFh

Unimplemented data memory locations, read as '0'.

DS40300C-page 14 Preliminary  2003 Microchip Technology Inc.

TABLE 3-1: SPECIAL REGISTERS SUMMARY BANK 0

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DS40300C-page 16 Preliminary  2003 Microchip Technology Inc.

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DS40300C-page 18 Preliminary  2003 Microchip Technology Inc.

REGISTER 3-1: STATUS REGISTER (ADDRESS: 03h, 83h, 103h, 183h)

 2003 Microchip Technology Inc. Preliminary DS40300C-page 19

REGISTER 3-2: OPTION REGISTER (ADDRESS: 81h, 181h)

bit 7 RBPU: PORTB Pull-up Enable bit

000 1:2 1:1

DS40300C-page 20 Preliminary  2003 Microchip Technology Inc.

REGISTER 3-3: INTCON REGISTER (ADDRESS: 0Bh, 8Bh, 10Bh, 18Bh)

bit 7 GIE: Global Interrupt Enable bit

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REGISTER 3-4: PIE1 REGISTER (ADDRESS: 8Ch)

bit 7 EEIE: EE Write Complete Interrupt Enable Bit

DS40300C-page 22 Preliminary  2003 Microchip Technology Inc.

REGISTER 3-5: PIR1 REGISTER (ADDRESS: 0Ch)

bit 7 EEIF: EEPROM Write Operation Interrupt Flag bit

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